Konrad Dybcio [Mon, 20 Nov 2023 12:12:53 +0000 (13:12 +0100)]
arm64: dts: qcom: sc7280: Fix up GPU SIDs
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute).
On platforms that support it (in firmware), it is necessary to
describe that link, or Adreno register access will hang the board.
The current settings are functionally identical, *but* due to what is
likely hardcoded security policies, the secure firmware rejects them,
resulting in the board hanging. To avoid that, alter the settings such
that SID 0 and 1 are described separately.
Rohit Agarwal [Fri, 17 Nov 2023 08:07:35 +0000 (13:37 +0530)]
arm64: dts: qcom: Add interconnect nodes for SDX75
Add interconnect nodes to support interconnects on SDX75.
Also parallely add the interconnect property for UART required
so that the bootup to shell does not break with interconnects
in place.
Nia Espera [Sat, 11 Nov 2023 22:07:42 +0000 (23:07 +0100)]
arm64: dts: qcom: sm8350: Fix remoteproc interrupt type
In a similar vein to
https://lore.kernel.org/lkml/20220530080842.37024-3-manivannan.sadhasivam@linaro.org/,
the remote processors on sm8350 fail to initialize with the 'correct'
(i.e., specified in downstream) IRQ type. Change this to EDGE_RISING.
The Samsung S6SY761 touchscreen bindings expect AVDD regulator which is
missing in the Sony Xperia PDX225 DTS. There is however pinctrl setting
for in the touchscreen device node with similar name: "avdd", so assume
author wanted to control a fixed regulator with a GPIO.
This fixes dtbs_check warning:
sm6375-sony-xperia-murray-pdx225.dtb: touchscreen@48: 'avdd-supply' is a required property
arm64: dts: qcom: sm6125: add interrupts to DWC3 USB controller
Add interrupts to SM6125 DWC3 USB controller, based on downstream/vendor
code of Trinket DTSI from Xiaomi Laurel device, to fix dtbs_check
warnings:
sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'interrupt-names' is a required property
sm6125-xiaomi-laurel-sprout.dtb: usb@4ef8800: 'oneOf' conditional failed, one must be fixed:
'interrupts' is a required property
'interrupts-extended' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20231111164229.63803-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sm6115: align mem timer size cells with bindings
Commit 70d1e09ebf19 ("arm64: dts: qcom: sm6115: Use 64 bit addressing")
converted all addresses to 64-bit addressing, but the ARMv7 memory
mapped architected timer bindings expect sizes up to 32-bit. Keep
64-bit addressing but change size of memory mapping to 32-bit
(size-cells=1) and adjust the ranges to match this.
This fixes dtbs_check warnings like:
sm6115p-lenovo-j606f.dtb: timer@f120000: #size-cells:0:0: 1 was expected
According to bindings and Linux driver there is no
"multi_channel_register" address space for LLCC. The first "reg" entry
is supposed to be llcc0_base since commit 43aa006e074c ("dt-bindings:
arm: msm: Fix register regions used for LLCC banks"):
qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long
qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected
qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long
Neil Armstrong [Mon, 6 Nov 2023 15:58:33 +0000 (16:58 +0100)]
arm64: dts: qcom: sm8450: fix soundwire controllers node name
Fix the following dt bindings check:
arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: soundwire-controller@31f0000: $nodename:0: 'soundwire-controller@31f0000' does not match '^soundwire(@.*)?$'
from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml#
Neil Armstrong [Mon, 6 Nov 2023 14:23:57 +0000 (15:23 +0100)]
arm64: dts: qcom: sm8550: fix soundwire controllers node name
Fix the following dt bindings check:
arch/arm64/boot/dts/qcom/sm8550-mtp.dtb: soundwire-controller@6ab0000: $nodename:0: 'soundwire-controller@6ab0000' does not match '^soundwire(@.*)?$'
from schema $id: http://devicetree.org/schemas/soundwire/qcom,soundwire.yaml#
arm64: dts: qcom: ipq5018: add few more reserved memory regions
Like all other IPQ SoCs, bootloader will collect the system RAM contents
upon crash for the post morterm analysis. If we don't reserve the memory
region used by bootloader, obviously linux will consume it and upon next
boot on crash, bootloader will be loaded in the same region, which will
lead to loose some of the data, sometimes we may miss out critical
information. So lets reserve the region used by the bootloader.
Similarly SBL copies some data into the reserved region and it will be
used in the crash scenario. So reserve 1MB for SBL as well.
While at it, enable the SMEM support along with TCSR mutex.
Caleb Connolly [Wed, 25 Oct 2023 11:58:00 +0000 (12:58 +0100)]
arm64: dts: qcom: qrb2210-rb1: use USB host mode
The default for the QCM2290 platform that this board is based on is OTG
mode, however the role detection logic is not hooked up for this board
and the dwc3 driver is configured to not allow role switching from
userspace.
Force this board to host mode as this is the preferred usecase until we
get role switching hooked up.
arm64: dts: qcom: sm6350: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
arm64: dts: qcom: sc8280xp: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
arm64: dts: qcom: sa8775p: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
Fixes: 09b701b89a76 ("arm64: dts: qcom: sa8775p: add the watchdog node") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20231106144335.v2.6.I909b7c4453d7b7fb0db4b6e49aa21666279d827d@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sm8250: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
Fixes: 46a4359f9156 ("arm64: dts: qcom: sm8250: Add watchdog bark interrupt") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.5.I2910e7c10493d896841e9785c1817df9b9a58701@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sm8150: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
Fixes: b094c8f8dd2a ("arm64: dts: qcom: sm8150: Add watchdog bark interrupt") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.4.I23d0aa6c8f1fec5c26ad9b3c610df6f4c5392850@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sdm845: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
Fixes: 36c436b03c58 ("arm64: dts: qcom: sdm845: Add watchdog bark interrupt") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.3.I16675ebe5517c68453a1bd7f4334ff885f806c03@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sc7280: Make watchdog bark interrupt edge triggered
As described in the patch ("arm64: dts: qcom: sc7180: Make watchdog
bark interrupt edge triggered"), the Qualcomm watchdog timer's bark
interrupt should be configured as edge triggered. Make the change.
arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered
On sc7180 when the watchdog timer fires your logs get filled with:
watchdog0: pretimeout event
watchdog0: pretimeout event
watchdog0: pretimeout event
...
watchdog0: pretimeout event
If you're using console-ramoops to debug crashes the above gets quite
annoying since it blows away any other log messages that might have
been there.
The issue is that the "bark" interrupt (AKA the "pretimeout"
interrupt) remains high until the watchdog is pet. Since we've got
things configured as "level" triggered we'll keep getting interrupted
over and over.
Let's switch to edge triggered. Now we'll get one interrupt when the
"bark" interrupt goes off and won't get another one until the "bark"
interrupt is cleared and asserts again.
This matches how many older Qualcomm SoCs have things configured.
Fixes: 28cc13e4060c ("arm64: dts: qcom: sc7180: Add watchdog bark interrupt") Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20231106144335.v2.1.Ic7577567baff921347d423b722de8b857602efb1@changeid Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The TX Soundwire controller should take clock from TX macro codec, not
VA macro codec clock, otherwise the clock stays disabled. This looks
like a copy-paste issue, because the SC8280xp code uses here correctly
clock from TX macro. The VA macro clock is already consumed by TX macro
codec, thus it won't be disabled by this change.
Fixes: 61b006389bb7 ("arm64: dts: qcom: sm8550: add Soundwire controllers") Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231129140537.161720-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The TX Soundwire controller should take clock from TX macro codec, not
VA macro codec clock, otherwise the clock stays disabled. This looks
like a copy-paste issue, because the SC8280xp code uses here correctly
clock from TX macro. The VA macro clock is already consumed by TX macro
codec, thus it won't be disabled by this change.
Fixes: 14341e76dbc7 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Reported-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231129140537.161720-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The hall sensor interrupt on the Primus is active low, which means that
with the current configuration the device attempts to suspend when the
LID is open.
Fix the polarity of the HALL_INT GPIO to avoid this.
The sc8280xp Display Port PHYs can be used in either DP or eDP mode and
this is configured using the devicetree compatible string which defaults
to DP mode in the SoC dtsi.
Override the default compatible string for the CRD eDP PHY node so that
the eDP settings are used.
Robert Marko [Sat, 21 Oct 2023 12:00:07 +0000 (14:00 +0200)]
arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
IPQ6018 comes in multiple SKU-s and some of them dont support all of the
OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
supported OPP-s based on the SoC dynamically.
As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
goes up to 1.5GHz and is marked as such via an eFuse.
The RB1 platform doesn't have board-specific board-id programmed, it uses
generic 0xff. Thus add the property with the 'variant' of the
calibration data.
Note: the driver will check for the calibration data for the following
IDs, so existing board-2.bin files will continue to work.
Konrad Dybcio [Wed, 29 Nov 2023 14:44:04 +0000 (15:44 +0100)]
arm64: dts: qcom: sc7280: Add the missing MDSS icc path
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one.
Failing to provide it may result in register accesses failing and that's
never good.
Konrad Dybcio [Wed, 29 Nov 2023 14:44:03 +0000 (15:44 +0100)]
arm64: dts: qcom: sc7180: Add the missing MDSS icc path
MDSS, aside from the MDP-MEM path, also requires the CPU-DISP_CFG one.
Failing to provide it may result in register accesses failing and that's
never good.
Stephen Boyd [Wed, 29 Nov 2023 03:04:41 +0000 (19:04 -0800)]
dt-bindings: arm: qcom: Fix html link
This link got broken by commit e790a4ce5290 ("arm: docs: Move Arm
documentation to Documentation/arch/") when the doc moved from arm/ to
arch/arm/. Fix the link so that it can continue to be followed.
Fixes: e790a4ce5290 ("arm: docs: Move Arm documentation to Documentation/arch/") Cc: Alexandre TORGUE <alexandre.torgue@foss.st.com> Cc: Yanteng Si <siyanteng@loongson.cn> Cc: Jonathan Corbet <corbet@lwn.net> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20231129030443.2753833-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Komal Bajaj [Wed, 29 Nov 2023 06:58:14 +0000 (12:28 +0530)]
dt-bindings: arm: qcom: Add QCM6490 IDP and QCS6490 RB3Gen2 board
Document the qcom,qcm6490-idp and qcs6490-rb3gen2 boards.
qcm6490-idp based off qcm6490 SoC derived from sc7280 meant for
various form factor including IoT and qcs6490-rb3gen2 based off
qcs6490 SoC derivative of qcm6490 without internal modem.
arm64: dts: qcom: sm8250: Add OPP table support to UFSHC
UFS host controller, when scaling gears, should choose appropriate
performance state of RPMh power domain controller along with clock
frequency. So let's add the OPP table support to specify both clock
frequency and RPMh performance states replacing the old "freq-table-hz"
property.
arm64: dts: qcom: sdm845: Add OPP table support to UFSHC
UFS host controller, when scaling gears, should choose appropriate
performance state of RPMh power domain controller along with clock
frequency. So let's add the OPP table support to specify both clock
frequency and RPMh performance states replacing the old "freq-table-hz"
property.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
[mani: Splitted pd change and used rpmhpd_opp_low_svs] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231012172129.65172-5-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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