Jan Beulich [Wed, 7 Jan 2015 08:39:27 +0000 (09:39 +0100)]
arm: fix extension feature disabling
Using e.g.
.arch_extension simd
.arch_extension nocrypto
so far results in SIMD support getting disabled, which I can't see being
the purpose of the "no"-prefixed variants of architecture extension
specifications.
Of course it is questionable whether the current, counter intuitive
behavior needs to be retained, and the new behavior perhaps be made work
through e.g. a newly recognized "no-" prefix.
gas/
2015-01-07 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (struct arm_option_extension_value_table):
Split field "value" into fields "merge_value" and "clear_value".
(arm_extensions): Adjust initializer accordingly.
Matthew Wahab [Mon, 1 Jun 2015 15:00:28 +0000 (16:00 +0100)]
[AArch64][libopcode] Add support for PAN architecture extension
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.
This patch adds support for the PAN architecture feature and processor state
field to libopcode.
include/opcode
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
The first and second exception_code invocations create the
.text.exception and the .init.exception sections respectively. This is
useful e.g. to discriminate between anciliary sections that are tied to
.init code and can be discarded at run time when initialization is over
vs anciliary sections tied to .text sections that need to stay resident.
Marcus Shawcroft [Tue, 24 Feb 2015 12:04:41 +0000 (12:04 +0000)]
Workaround for Cortex A53 erratum 843419
Some early revisions of the Cortex-A53 have an erratum (843419). The
details of the erratum are quite complex and involve dynamic
conditions. For the purposes of the workaround we have simplified the
static conditions to an ADRP in the last two instructions of a 4KByte
page, followed within four instructions by a load/store dependent on
the ADRP.
This patch adds support to conservatively scan for and workaround
Cortex A53 erratum 843419. There are two different workaround
strategies used. The first is to rewrite ADRP instructions which form
part of an erratum sequence with an ADR instruction. In situations
where the ADR provides insufficient offset the dependent load or store
instruction from the sequence is moved to a stub section and branches
are inserted from the original sequence to the relocated instruction
and back again.
Stub section sizes are rounded up to a multiple of 4096 in order to
ensure that the act of inserting work around stubs does not create
more errata sequences.
Workaround stubs are always inserted into the stub section associated
with the input section containing the erratum sequence. This ensures
that the fully relocated form of the veneered load store instruction
is available at the point in time when the stub section is written.
Marcus Shawcroft [Sun, 22 Mar 2015 08:31:18 +0000 (08:31 +0000)]
Implement branch over stub section.
Ensure that injection of a stub section does not break a link where
there is an xpectation that flow of control can pass from one input
section to another simply by linking the input sections in series.
The solution here is to allow stub sections to be inserted after any
input section (existing behaviour), but inject an additional branch at
the start of each stub section such that control flow falling into the
stub section will branch over the stub section.
Marcus Shawcroft [Sat, 28 Feb 2015 00:17:22 +0000 (00:17 +0000)]
Refactor section_group[] representation.
Change the behaviour of section_group[] such that .stub_sec points to
the stub section attached to the indexed section rather than the stub
section attached to the link_section pointed to be the index section.
This provides a mechanism to get to the stub section following any
input section. While still allowing the section grouping mechanism to
find the section group stub section associated with an input section
by first following the link_sec pointer.
Marcus Shawcroft [Fri, 20 Mar 2015 19:08:00 +0000 (19:08 +0000)]
Refactor generation of 835769 workaround stubs.
This patch recognizes that we only need to perform one scan for the
835769 errata and that this scan can take place before we insert
branch stubs. The erratum scan code is relocated and adjusted to
create stub entries directly rather than populating an intermediate
representation. Since stub entries are created immediately we can
drop the adhoc stub size adjustment code and allow the generic stub
sizing code to deal with 835769 stub entries.
This patch restructures the code but does not change the workaround
used to deal with erratum 83679, the exact placement of workaround
stubs in the final image may change slightly after this patch due to
stubs being created in a different order.
H.J. Lu [Mon, 5 Jan 2015 12:42:37 +0000 (04:42 -0800)]
Assign file position for .strtab only if needed
bfd/
PR ld/17773
* elflink.c (bfd_elf_final_link): Assign the file position for
the symbol string table only there are symbols to be emitted.
ld/testsuite/
PR ld/17773
* ld-elf/binutils.exp (binutils_test): Add an optional
readelf_options. Replace -l with $readelf_options. Add a
gap test.
* ld/testsuite/ld-elf/gap.s: New file.
Matthew Fortune [Tue, 16 Dec 2014 12:39:22 +0000 (12:39 +0000)]
Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.
gas/
* config/tc-mips.c (md_apply_fix): Apply alignment check
to the symbol and offset rather than *valP for
BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
for BFD_RELOC_MIPS_19_PCREL_S2.
gas/testsuite/
* gas/mips/r6-64.s: Remove .align directives from LDPC
instructions and add further tests for LDPC.
* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
output and update for new tests.
* gas/mips/r6-64-n64.d: Likewise.
* gas/mips/ldpc-unalign.l: New file.
* gas/mips/ldpc-unalign.s: Likewise.
* gas/mips/mips.exp: Run ldpc-unalign test.
Matthew Fortune [Thu, 18 Dec 2014 20:08:38 +0000 (20:08 +0000)]
Fix undefined weak symbol reloc tests
ld/testsuite/
* ld-mips-elf/mips-elf.exp: Update undefweak-overflow tests.
* ld-mips-elf/undefweak-overflow-n32.d: Remove.
* ld-mips-elf/undefweak-overflow-n64.d: Likewise.
* ld-mips-elf/undefweak-overflow.s: Set mips64r6, noreorder and
add a label to mark the micromips region.
* ld-mips-elf/undefweak-overflow.d: Update expected output.
Andrew Bennett [Thu, 20 Nov 2014 15:40:16 +0000 (15:40 +0000)]
[MIPS] When calculating a relocation using an undefined weak symbol don't check for overflow.
In MIPS the relocation calculation only ignores the overflow checks for undefined
weak symbols on relocations associated with j/jal. This patch extends this to
the relocations used by the: b* instructions; pc/gp relative symbol offsets; and the
lwpc/ldpc MIPS r6 instructions.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Only check for overflow
on non-weak undefined symbols.
ld/testsuite/
* ld-mips-elf/mips-elf.exp: Add in undefined weak overflow tests for
o32, n32 and n64.
* ld-mips-elf/undefweak-overflow.s: New test.
* ld-mips-elf/undefweak-overflow.d: New test.
* ld-mips-elf/undefweak-overflow-n32.d: New test.
* ld-mips-elf/undefweak-overflow-n64.d: New test.
H.J. Lu [Sun, 14 Dec 2014 07:37:22 +0000 (23:37 -0800)]
Handle weak alias for PIE with copy reloc
When there is a weak symbol with a real definition, the processor
independent code will have arranged for us to see the real definition
first. We need to copy the needs_copy bit from the real definition and
check it when allowing copy reloc in PIE.
bfd/
PR ld/17689
* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add needs_copy.
Change has_bnd_reloc to bit field.
(elf_x86_64_link_hash_newfunc): Initialize needs_copy and
has_bnd_reloc to 0.
(elf_x86_64_check_relocs): Set has_bnd_reloc to 1 instead
of TRUE.
(elf_x86_64_adjust_dynamic_symbol): Copy needs_copy from the
real definition to a weak symbol.
(elf_x86_64_allocate_dynrelocs): Also check needs_copy of a
weak symbol for PIE when discarding space for relocs against
symbols which turn out to need copy relocs.
(elf_x86_64_relocate_section): Also check needs_copy of a
weak symbol for PIE with copy reloc.
H.J. Lu [Thu, 4 Dec 2014 22:19:41 +0000 (14:19 -0800)]
Add _bfd_elf_ifunc_get_synthetic_symtab
In i386 and x86-64 binaries with ifunc, relocations against .got.plt
section may not be in the same order as entries in PLT section. This
patch adds _bfd_elf_ifunc_get_synthetic_symtab. It takes a function
pointer which returns an array of PLT entry symbol values. It calls
the function pointer to get the PLT entry symbol value array indexed
by relocation index, instead of calling plt_sym_val on each relocation
index.
Mixing 64-bit and 32-bit types led to the wrong promotions. Keep
calculation in same type. Also fix a case where PLTREL24 reloc addend
should be ignored.
* Powerpc.cc (Target_powerpc::Branch_info::make_stub): Ignore
addend of PLTREL24 reloc when not generating a plt stub. Make
max_branch_offset an "Address".
(Target_powerpc::Relocate::relocate): Make max_branch_offset
an "Address".
Alan Modra [Wed, 3 Dec 2014 05:47:23 +0000 (16:17 +1030)]
powerpc gold, work around pr17670
pr17670 is about an assert triggering on a branch to an undefined
weak symbol, the symbol being undefined due to dropping its comdat
group section. (Well sort of. The symbol is actually defined in
an .opd section which isn't part of the group, but the code section
the opd entry points at is dropped.) So don't assert.
Also, don't make long branch stubs to such symbols, and arrange to
have target-reloc.h code warn when applying relocs that use the sym.
PR 17670
* symtab.cc (Symbol::set_undefined): Remove assertion.
* powerpc.cc (Target_powerpc::symval_for_branch): Don't assert
on symbols defined in discarded sections, instead return false.
Rearrange params, update all callers.
(Target_powerpc::Branch_info::make_stub): Don't make stubs for
branches to syms in discarded sections.
(Global_symbol_visitor_opd::operator()): Set discarded opd syms
undefined and flag as discarded.
(Target_powerpc::Relocate::relocate): Localize variable.
H.J. Lu [Tue, 2 Dec 2014 23:14:28 +0000 (15:14 -0800)]
X86-64: Allow copy relocs for building PIE
This patch allows copy relocs for non-GOT pc-relative relocation in PIE.
bfd/
* elf64-x86-64.c (elf_x86_64_create_dynamic_sections): Always
allow copy relocs for building executables.
(elf_x86_64_adjust_dynamic_symbol): Allocate copy relocs for
PIE.
(elf_x86_64_allocate_dynrelocs): For PIE, discard space for
relocs against symbols which turn out to need copy relocs.
(elf_x86_64_relocate_section): Don't copy a pc-relative
relocation into the output file if the symbol needs copy reloc.
Alan Modra [Thu, 27 Nov 2014 04:46:49 +0000 (15:16 +1030)]
Don't output symbol version definitions for non-DT_NEEDED libs
PR 16452, 16457
* elflink.c (_bfd_elf_link_find_version_dependencies): Exclude
symbols from libraries that won't be listed in DT_NEEDED.
(elf_link_output_extsym): Don't output verdefs for such symbols.
projects / thirdparty / binutils-gdb.git / log
