bfd/
* elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value
plus addend rather than the original st_value when looking up
entries in opd->adjust.
ld/testsuite/
* ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s,
ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s,
ld-powerpc/tocopt6.d: New test.
* ld-powerpc/powerpc.exp (ppc64elftests): Add it.
Alan Modra [Fri, 3 Jul 2015 01:26:26 +0000 (10:56 +0930)]
Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
Peter Bergner [Mon, 22 Jun 2015 19:55:24 +0000 (14:55 -0500)]
PPC sync instruction accepts invalid and incompatible operands
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC. Edmar added
support for this insruction varient here:
Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC. This patch changes the assembler to
error out on invalid and incompatible operand usage.
opcodes/
* ppc-opc.c (insert_ls): Test for invalid LS operands.
(insert_esync): New function.
(LS, WC): Use insert_ls.
(ESYNC): Use insert_esync.
Peter Bergner [Fri, 19 Jun 2015 22:17:07 +0000 (17:17 -0500)]
Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
Peter Bergner [Fri, 12 Jun 2015 20:06:07 +0000 (15:06 -0500)]
Remove unused MTMSRD_L macro and re-add accidentally deleted comment.
In the commit that added PowerPC Pair Singles, Ben accidentally removed
a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
This was probably just an oversite when he was refreshing his patch to
trunk.
opcodes/
* ppc-opc.c: Add comment accidentally removed by old commit.
(MTMSRD_L): Delete.
Alan Modra [Fri, 5 Jun 2015 09:05:40 +0000 (18:35 +0930)]
ppc476 linker workaround shared lib fixes
When building a shared lib from non-PIC objects, we'll get dynamic
text relocations. These need to move with any insns we move.
Otherwise the dynamic reloc will modify the branch, resulting in
crashes and other unpleasant behaviour.
Also, ld -r --ppc476-workaround used with sufficiently aligned PIC
objects needs a fix for emitted REL16 relocs.
bfd/
* elf64-ppc.c (ppc_elf_relocate_section): Move dynamic text
relocs with insns moved by --ppc476-workaround. Correct
output of REL16 relocs.
ld/testsuite/
* ld-powerpc/ppc476-shared.s,
* ld-powerpc/ppc476-shared.lnk,
* ld-powerpc/ppc476-shared.d,
* ld-powerpc/ppc476-shared2.d: New tests.
* ld-powerpc/powerpc.exp: Run them.
Peter Bergner [Fri, 5 Jun 2015 01:27:03 +0000 (20:27 -0500)]
Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.
opcodes/
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
gas/testsuite/
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
* gas/ppc/power4.d: Likewise.
Alan Modra [Fri, 24 Apr 2015 09:49:37 +0000 (19:19 +0930)]
Non-alloc sections don't belong in PT_LOAD segments
Taking them out showed a bug in the powerpc64 backend with .branch_lt
being removed from output_bfd but not from previously set up segment
section maps. Removing the bfd sections meant their sh_flags (and
practically everything else) remaining zero, ie. not SHF_ALLOC,
triggering complaints about "`.branch_lt' can't be allocated in
segment".
include/elf/
* internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and
similar segments only contain alloc sections.
ld/
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation):
Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out.
Alan Modra [Tue, 21 Apr 2015 09:48:24 +0000 (19:18 +0930)]
Align .TOC. for PowerPC64
This change, with prerequisite 0e5fabeb, provides a toc base aligned
to 256 bytes rather than 8 bytes. This is necessary for a minor gcc
optimisation, allowing use of d-form instructions to correctly access
toc-relative items larger than 8 bytes.
Alan Modra [Wed, 22 Apr 2015 13:16:19 +0000 (22:46 +0930)]
Rewrite relro adjusting code
The linker tries to put the end of the last section in the relro
segment exactly on a page boundary, because the relro segment itself
must end on a page boundary. If for any reason this can't be done,
padding is inserted. Since the end of the relro segment is typically
between .got and .got.plt, padding effectively increases the size of
the GOT. This isn't nice for targets and code models with limited GOT
addressing.
The problem with the current code is that it doesn't cope very well
with aligned sections in the relro segment. When making .got aligned
to a 256 byte boundary for PowerPC64, I found that often the initial
alignment attempt failed and the fallback attempt to be less than
adequate. This is a particular problem for PowerPC64 since the
distance between .got and .plt affects the size of plt call stubs,
leading to "stubs don't match calculated size" errors.
So this rewrite takes a direct approach to calculating a new relro
base. Starting from the last section in the segment, we calculate
where it must start to position its end on the boundary, or as near as
possible considering alignment requirements. The new start then
becomes the goal for the previous section to end, and so on for all
sections. This of course ignores the possibility that user scripts
will place . = ALIGN(xxx); in the relro segment, or provide section
address expressions. In those cases we might fail, but the old code
probably did too, and a fallback is provided.
ld/
* ldexp.h (struct ldexp_control): Delete dataseg.min_base. Add
data_seg.relro_offset.
* ldexp.c (fold_binary <DATA_SEGMENT_ALIGN>): Don't set min_base.
(fold_binary <DATA_SEGMENT_RELRO_END>): Do set relro_offset.
* ldlang.c (lang_size_sections): Rewrite code adjusting relro
segment base to line up last section on page boundary.
Anton Blanchard [Wed, 25 Mar 2015 02:44:28 +0000 (13:44 +1100)]
powerpc: Only initialise opcode indices once
The gdb TUI is calling gdb_print_insn() (which calls
disassemble_init_powerpc()) enough to show up high in profiles. As
suggested by Alan, only initialise if the indices are empty.
* ppc-dis.c (disassemble_init_powerpc): Only initialise
powerpc_opcd_indices and vle_opcd_indices once.
Alan Modra [Tue, 24 Mar 2015 07:07:57 +0000 (17:37 +1030)]
Make powerpc bfd ld reloc overflow vs undefined symbols match gold
* elf64-ppc.c (ppc64_elf_relocate_section): Report overflow to
stubs, even those for undefined weak symbols. Otherwise, don't
report relocation overflow on branches to undefined strong
symbols. Fix memory leak.
* elf32-ppc.c (ppc_elf_relocate_section): Don't report relocation
overflow on branches to undefined strong symbols.
Jiong Wang [Tue, 23 Jun 2015 11:19:24 +0000 (12:19 +0100)]
[AArch64][Backport] Generate DT_TEXTREL for relocation against RO section
2015-06-23 Jiong Wang <jiong.wang@arm.com>
Apply from master:
2015-06-23 Jiong. Wang <jiong.wang@arm.com>
bfd/
* elfnn-aarch64.c (aarch64_readonly_dynrelocs): New function.
(elfNN_aarch64_size_dynamic_sections): Traverse hash table to check
relocations against read-only sections.
ld/testsuite/
* ld-aarch64/dt_textrel.s: New testcase.
* ld-aarch64/dt_textrel.d: New expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
projects / thirdparty / binutils-gdb.git / log
