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2 years agoc++: add feature-test macro for auto(x)
Patrick Palka [Mon, 15 May 2023 16:01:07 +0000 (12:01 -0400)] 
c++: add feature-test macro for auto(x)

This adds the feature-test macro for PR0849R8, as per
https://github.com/cplusplus/CWG/issues/281.

gcc/c-family/ChangeLog:

* c-cppbuiltin.cc (c_cpp_builtins): Predefine __cpp_auto_cast
for C++23.

gcc/testsuite/ChangeLog:

* g++.dg/cpp23/feat-cxx2b.C: Test __cpp_auto_cast.

2 years agoRISC-V: Add rounding mode operand for fixed-point patterns
Juzhe-Zhong [Mon, 15 May 2023 14:23:45 +0000 (22:23 +0800)] 
RISC-V: Add rounding mode operand for fixed-point patterns

Since we are going to have fixed-point intrinsics that are modeling
rounding mode
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

We should have operand to specify rounding mode in fixed-point instructions.
We don't support these modeling rounding mode intrinsics yet but we will
definetely support them later.

This is the preparing patch for new coming intrinsics.

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Add default rounding mode operand.
* config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_REGNUM.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_conditional_register_usage): Ditto.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
(VXRM_REG_P): Ditto.
(RISCV_DWARF_VXRM): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector.md: Ditto

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2 years agoOPTABS: Extend the number of expanding instructions pattern
Pan Li [Mon, 15 May 2023 14:05:44 +0000 (22:05 +0800)] 
OPTABS: Extend the number of expanding instructions pattern

We (RVV) is going to add a rounding mode operand into floating-point
instructions which have 11 operands.

Since we are going have intrinsic that is adding rounding mode argument:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226

This is the patch that is adding rounding mode operand in RISC-V port:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
You can see there are 11 operands in these patterns.

gcc/ChangeLog:

* optabs.cc (maybe_gen_insn): Add case to generate instruction
that has 11 operands.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2 years agofix assert in non-atomic path
Thomas Neumann [Mon, 15 May 2023 12:59:22 +0000 (14:59 +0200)] 
fix assert in non-atomic path

The non-atomic path does not have range information,
we have to adjust the assert handle that case, too.

libgcc/ChangeLog:
* unwind-dw2-fde.c: Fix assert in non-atomic path.

2 years agoaarch64: Cost vector comparisons more accurately
Kyrylo Tkachov [Mon, 15 May 2023 11:05:35 +0000 (12:05 +0100)] 
aarch64: Cost vector comparisons more accurately

We are missing cases for combining of FACGE/FACGT instructions. In the testcase of the patch we generate:
foo:
        fabs    v3.4s, v0.4s
        fabs    v0.4s, v1.4s
        fabs    v1.4s, v2.4s
        fcmgt   v0.4s, v3.4s, v0.4s
        fcmgt   v1.4s, v3.4s, v1.4s
        b       g

This is because combine is rejecting the pattern due to costs:
Successfully matched this instruction:
(set (reg:V4SI 106)
    (neg:V4SI (lt:V4SI (abs:V4SF (reg:V4SF 113))
            (abs:V4SF (reg:V4SF 111)))))
rejecting combination of insns 8, 9 and 10
original costs 8 + 8 + 12 = 28
replacement costs 8 + 28 = 36

It is obviously recursing in the various arms of the RTX and such.
This patch teaches the aarch64 rtx costs routine that our vector comparisons are represented as a NEG of
compare operators, with the FACGE/FAGT operations in particular having ABS on each arm. With this patch we get
the much more reasonable dump:
original costs 8 + 8 + 8 = 24
replacement costs 8 + 8 = 16
and generate the optimal assembly:
foo:
        mov     v31.16b, v0.16b
        facgt   v0.4s, v0.4s, v1.4s
        facgt   v1.4s, v31.4s, v2.4s
        b       g

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_rtx_costs, NEG case): Add costing
logic for vector modes.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/facg_1.c: New test.

2 years agoSupport parallel testing in libgomp, part II [PR66005]
Thomas Schwinge [Tue, 25 Apr 2023 21:53:12 +0000 (23:53 +0200)] 
Support parallel testing in libgomp, part II [PR66005]

..., and enable if 'flock' is available for serializing execution testing.

Regarding the default of 19 parallel slots, this turned out to be a local
minimum for wall time when testing this on:

    $ uname -srvi
    Linux 4.2.0-42-generic #49~14.04.1-Ubuntu SMP Wed Jun 29 20:22:11 UTC 2016 x86_64
    $ grep '^model name' < /proc/cpuinfo | uniq -c
         32 model name      : Intel(R) Xeon(R) CPU E5-2640 v3 @ 2.60GHz

... in two configurations: case (a) standard configuration, no offloading
configured, case (b) offloading for GCN and nvptx configured but no devices
available.  For both cases, default plus '-m32' variant.

    $ \time make check-target-libgomp RUNTESTFLAGS="--target_board=unix\{,-m32\}"

Case (a), baseline:

    6432.23user 332.38system 47:32.28elapsed 237%CPU (0avgtext+0avgdata 505044maxresident)k
    6382.43user 319.21system 47:06.04elapsed 237%CPU (0avgtext+0avgdata 505172maxresident)k

This is what people have been complaining about, rightly so, in
<https://gcc.gnu.org/PR66005> "libgomp make check time is excessive" and
elsewhere.

Case (a), parallelized:

    -j12 GCC_TEST_PARALLEL_SLOTS=10
    3088.49user 267.74system 6:43.82elapsed 831%CPU (0avgtext+0avgdata 505188maxresident)k
    -j15 GCC_TEST_PARALLEL_SLOTS=15
    3308.08user 294.79system 5:56.04elapsed 1011%CPU (0avgtext+0avgdata 505360maxresident)k
    -j17 GCC_TEST_PARALLEL_SLOTS=17
    3539.93user 298.99system 5:27.86elapsed 1170%CPU (0avgtext+0avgdata 505112maxresident)k
    -j18 GCC_TEST_PARALLEL_SLOTS=18
    3697.50user 317.18system 5:14.63elapsed 1275%CPU (0avgtext+0avgdata 505360maxresident)k
    -j19 GCC_TEST_PARALLEL_SLOTS=19
    3765.94user 324.27system 5:13.22elapsed 1305%CPU (0avgtext+0avgdata 505128maxresident)k
    -j20 GCC_TEST_PARALLEL_SLOTS=20
    3684.66user 312.32system 5:15.26elapsed 1267%CPU (0avgtext+0avgdata 505100maxresident)k
    -j23 GCC_TEST_PARALLEL_SLOTS=23
    4040.59user 347.10system 5:29.12elapsed 1333%CPU (0avgtext+0avgdata 505200maxresident)k
    -j26 GCC_TEST_PARALLEL_SLOTS=26
    3973.24user 377.96system 5:24.70elapsed 1340%CPU (0avgtext+0avgdata 505160maxresident)k
    -j32 GCC_TEST_PARALLEL_SLOTS=32
    4004.42user 346.10system 5:16.11elapsed 1376%CPU (0avgtext+0avgdata 505160maxresident)k

Yay!

Case (b), baseline; 2+ h:

    7227.58user 700.54system 2:14:33elapsed 98%CPU (0avgtext+0avgdata 994264maxresident)k

Case (b), parallelized:

    -j12 GCC_TEST_PARALLEL_SLOTS=10
    7377.46user 777.52system 16:06.63elapsed 843%CPU (0avgtext+0avgdata 994344maxresident)k
    -j15 GCC_TEST_PARALLEL_SLOTS=15
    8019.18user 721.42system 12:13.56elapsed 1191%CPU (0avgtext+0avgdata 994228maxresident)k
    -j17 GCC_TEST_PARALLEL_SLOTS=17
    8530.11user 716.95system 10:45.92elapsed 1431%CPU (0avgtext+0avgdata 994176maxresident)k
    -j18 GCC_TEST_PARALLEL_SLOTS=18
    8776.79user 645.89system 10:27.20elapsed 1502%CPU (0avgtext+0avgdata 994248maxresident)k
    -j19 GCC_TEST_PARALLEL_SLOTS=19
    9332.37user 641.76system 10:15.09elapsed 1621%CPU (0avgtext+0avgdata 994260maxresident)k
    -j20 GCC_TEST_PARALLEL_SLOTS=20
    9609.54user 789.88system 10:26.94elapsed 1658%CPU (0avgtext+0avgdata 994284maxresident)k
    -j23 GCC_TEST_PARALLEL_SLOTS=23
    10362.40user 911.14system 10:44.47elapsed 1749%CPU (0avgtext+0avgdata 994208maxresident)k
    -j26 GCC_TEST_PARALLEL_SLOTS=26
    11159.44user 850.99system 11:09.25elapsed 1794%CPU (0avgtext+0avgdata 994256maxresident)k
    -j32 GCC_TEST_PARALLEL_SLOTS=32
    11453.50user 939.52system 11:00.38elapsed 1876%CPU (0avgtext+0avgdata 994240maxresident)k

On my Dell Precision 7530 laptop:

    $ uname -srvi
    Linux 5.15.0-71-generic #78-Ubuntu SMP Tue Apr 18 09:00:29 UTC 2023 x86_64
    $ grep '^model name' < /proc/cpuinfo | uniq -c
         12 model name      : Intel(R) Core(TM) i7-8850H CPU @ 2.60GHz
    $ nvidia-smi -L
    GPU 0: Quadro P1000 (UUID: GPU-e043973b-b52a-d02b-c066-a8fdbf64e8ea)

... in two configurations: case (c) standard configuration, no offloading
configured, case (d) offloading for nvptx configured and device available.
For both cases, only default variant, no '-m32'.

    $ \time make check-target-libgomp

Case (c), baseline; roughly half of case (a) (just one variant):

    1180.98user 110.80system 19:36.40elapsed 109%CPU (0avgtext+0avgdata 505148maxresident)k
    1133.22user 111.08system 19:35.75elapsed 105%CPU (0avgtext+0avgdata 505212maxresident)k

Case (c), parallelized:

    -j12 GCC_TEST_PARALLEL_SLOTS=2
    1143.83user 110.76system 10:20.46elapsed 202%CPU (0avgtext+0avgdata 505216maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=6
    1737.08user 143.94system 4:59.48elapsed 628%CPU (0avgtext+0avgdata 505200maxresident)k
    1730.31user 143.02system 4:58.75elapsed 627%CPU (0avgtext+0avgdata 505152maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=8
    2192.63user 169.34system 4:52.96elapsed 806%CPU (0avgtext+0avgdata 505216maxresident)k
    2219.04user 167.67system 4:53.19elapsed 814%CPU (0avgtext+0avgdata 505152maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=10
    2463.93user 184.98system 4:48.39elapsed 918%CPU (0avgtext+0avgdata 505200maxresident)k
    2455.62user 183.68system 4:47.40elapsed 918%CPU (0avgtext+0avgdata 505216maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=12
    2591.04user 192.64system 4:44.98elapsed 976%CPU (0avgtext+0avgdata 505216maxresident)k
    2581.23user 195.21system 4:47.51elapsed 965%CPU (0avgtext+0avgdata 505212maxresident)k
    -j20 GCC_TEST_PARALLEL_SLOTS=20 [oversubscribe]
    2613.18user 199.51system 4:44.06elapsed 990%CPU (0avgtext+0avgdata 505216maxresident)k

Case (d), baseline (compared to case (b): only nvptx offloading compilation,
but also nvptx offloading execution); ~1 h:

    2841.93user 653.68system 1:02:26elapsed 93%CPU (0avgtext+0avgdata 909792maxresident)k
    2842.03user 654.39system 1:02:24elapsed 93%CPU (0avgtext+0avgdata 909880maxresident)k

Case (d), parallelized:

    -j12 GCC_TEST_PARALLEL_SLOTS=2
    2856.39user 606.87system 33:58.64elapsed 169%CPU (0avgtext+0avgdata 909948maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=6
    3444.90user 666.86system 18:37.57elapsed 367%CPU (0avgtext+0avgdata 909856maxresident)k
    3462.13user 667.13system 18:36.87elapsed 369%CPU (0avgtext+0avgdata 909872maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=8
    3929.74user 716.22system 18:02.36elapsed 429%CPU (0avgtext+0avgdata 909832maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=10
    4152.84user 736.16system 17:43.05elapsed 459%CPU (0avgtext+0avgdata 909872maxresident)k
    -j12 GCC_TEST_PARALLEL_SLOTS=12
    4209.60user 749.00system 17:35.20elapsed 469%CPU (0avgtext+0avgdata 909840maxresident)k
    -j20 GCC_TEST_PARALLEL_SLOTS=20 [oversubscribe]
    4255.54user 756.78system 17:29.06elapsed 477%CPU (0avgtext+0avgdata 909868maxresident)k

Worth noting is that with nvptx offloading, there is one execution test case
that times out ('libgomp.fortran/reverse-offload-5.f90').  This effectively
stalls progress for almost 5 min: quickly other executions test cases queue up
on the lock for all parallel slots.  That's working as expected; just noting
this as it accordingly does skew the wall time numbers.

PR testsuite/66005
libgomp/
* configure.ac: Look for 'flock'.
* testsuite/Makefile.am (gcc_test_parallel_slots): Enable parallel testing.
* testsuite/config/default.exp: Don't 'load_lib "standard.exp"' here...
* testsuite/lib/libgomp.exp: ... but here, instead.
(libgomp_load): Override for parallel testing.
* testsuite/libgomp-site-extra.exp.in (FLOCK): Set.
* configure: Regenerate.
* Makefile.in: Regenerate.
* testsuite/Makefile.in: Regenerate.

2 years agoSupport parallel testing in libgomp, part I [PR66005]
Rainer Orth [Thu, 7 May 2015 11:26:57 +0000 (13:26 +0200)] 
Support parallel testing in libgomp, part I [PR66005]

..., while still hard-coding the number of parallel slots to one.

PR testsuite/66005
libgomp/
* testsuite/Makefile.am (PWD_COMMAND): New variable.
(%/site.exp): New target.
(check_p_numbers0, check_p_numbers1, check_p_numbers2)
(check_p_numbers3, check_p_numbers4, check_p_numbers5)
(check_p_numbers6, check_p_numbers, gcc_test_parallel_slots)
(check_p_subdirs)
(check_DEJAGNU_libgomp_targets): New variables.
($(check_DEJAGNU_libgomp_targets)): New target.
($(check_DEJAGNU_libgomp_targets)): New dependency.
(check-DEJAGNU $(check_DEJAGNU_libgomp_targets)): New targets.
* testsuite/Makefile.in: Regenerate.
* testsuite/lib/libgomp.exp: For parallel testing,
'load_file ../libgomp-test-support.exp'.

Co-authored-by: Thomas Schwinge <thomas@codesourcery.com>
2 years agolibgomp testsuite: As appropriate, use the 'gcc', 'g++', 'gfortran' driver [PR91884]
Thomas Schwinge [Wed, 10 May 2023 13:01:55 +0000 (15:01 +0200)] 
libgomp testsuite: As appropriate, use the 'gcc', 'g++', 'gfortran' driver [PR91884]

..., that is, 'GCC_UNDER_TEST', 'GXX_UNDER_TEST', 'GFORTRAN_UNDER_TEST' instead
of 'GCC_UNDER_TEST' for all of them.  No need anymore for 'gcc -lstdc++ -x c++'
for C++ code, or 'gcc -lgfortran' plus conditional '-lquadmath' for Fortran
code.  (Getting rid of explicit '-foffload=-lgfortran' is for another day.)

PR testsuite/91884
libgomp/
* configure.ac: 'AC_SUBST(CXX)'.
* configure: Regenerate.
* Makefile.in: Likewise.
* testsuite/Makefile.in: Likewise.
* testsuite/libgomp-site-extra.exp.in (GXX_UNDER_TEST)
(GFORTRAN_UNDER_TEST): Set.
* testsuite/lib/libgomp.exp (libgomp_init): Adjust.
* testsuite/libgomp.c++/c++.exp: Use 'GXX_UNDER_TEST'.
* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
* testsuite/libgomp.fortran/fortran.exp: Use
'GFORTRAN_UNDER_TEST'.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

2 years agolibgomp testsuite: Have each '*.exp' file specify the compiler to use [PR91884]
Thomas Schwinge [Wed, 10 May 2023 12:43:21 +0000 (14:43 +0200)] 
libgomp testsuite: Have each '*.exp' file specify the compiler to use [PR91884]

..., which is still 'GCC_UNDER_TEST' for all of them; no change in behavior.

PR testsuite/91884
libgomp/
* testsuite/lib/libgomp.exp (libgomp_target_compile): Don't
specify compiler.
* testsuite/libgomp.c++/c++.exp (ALWAYS_CFLAGS): Specify compiler.
* testsuite/libgomp.c/c.exp (ALWAYS_CFLAGS): Likewise.
* testsuite/libgomp.fortran/fortran.exp (ALWAYS_CFLAGS): Likewise.
* testsuite/libgomp.graphite/graphite.exp (ALWAYS_CFLAGS):
Likewise.
* testsuite/libgomp.oacc-c++/c++.exp (ALWAYS_CFLAGS): Likewise.
* testsuite/libgomp.oacc-c/c.exp (ALWAYS_CFLAGS): Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp (ALWAYS_CFLAGS):
Likewise.

2 years agofix assert in __deregister_frame_info_bases
Sören Tempel [Sun, 14 May 2023 17:30:21 +0000 (19:30 +0200)] 
fix assert in __deregister_frame_info_bases

The assertion in __deregister_frame_info_bases assumes that for every
frame something was inserted into the lookup data structure by
__register_frame_info_bases. Unfortunately, this does not necessarily
hold true as the btree_insert call in __register_frame_info_bases will
not insert anything for empty ranges. Therefore, we need to explicitly
account for such empty ranges in the assertion as `ob` will be a null
pointer for such ranges, hence causing the assertion to fail.

Signed-off-by: Sören Tempel <soeren@soeren-tempel.net>
libgcc/ChangeLog:
* unwind-dw2-fde.c: Accept empty ranges when deregistering frames.

2 years agoada: Fix typo in comment
Marc Poulhiès [Mon, 16 Jan 2023 15:31:51 +0000 (16:31 +0100)] 
ada: Fix typo in comment

gcc/ada/

* exp_ch3.adb (Make_Allocator_For_Return): Fix typo in comment.

2 years agoada: Add annotations for proof of termination of runtime units
Yannick Moy [Mon, 16 Jan 2023 11:33:03 +0000 (11:33 +0000)] 
ada: Add annotations for proof of termination of runtime units

String-manipulating functions should always terminate. Add justification
for the termination of Mapping function parameter, and loop variants
where needed. This is needed for GNATprove to prove termination.

gcc/ada/

* libgnat/a-strbou.ads: Add justifications for Mapping.
* libgnat/a-strfix.adb: Same.
* libgnat/a-strfix.ads: Same.
* libgnat/a-strsea.adb: Same.
* libgnat/a-strsea.ads: Same.
* libgnat/a-strsup.adb: Same and add loop variants.
* libgnat/a-strsup.ads: Same and add specification of termination.

2 years agoada: Recover proof of runtime units
Yannick Moy [Mon, 16 Jan 2023 10:55:08 +0000 (10:55 +0000)] 
ada: Recover proof of runtime units

Changes needed to make proof go through, after some change in
GNAT and SPARK.

gcc/ada/

* libgnat/a-strsup.adb (Super_Slice): Reorder component assignment
to avoid failing predicate check related to initialization.
* libgnat/s-expmod.adb (Exp_Modular): Add intermediate assertion.

2 years agoada: Recover proof of Interfaces.C for termination
Yannick Moy [Mon, 16 Jan 2023 10:32:49 +0000 (10:32 +0000)] 
ada: Recover proof of Interfaces.C for termination

GNATprove reports possible non-terminating loops in functions
marked as terminating. Add loop variants to prove loop termination.

gcc/ada/

* libgnat/i-c.adb: Add loop variants. Remove useless
initialization.

2 years agoada: Fix comment related to inlining
Bob Duff [Fri, 13 Jan 2023 21:10:44 +0000 (16:10 -0500)] 
ada: Fix comment related to inlining

Correction to previous check-in: Remove comment about
Proc_Next_... procedures, which were deleted.

gcc/ada/

* einfo-utils.ads: Remove comment.

2 years agoada: Use Inline aspect instead of pragma in Einfo.Utils
Bob Duff [Fri, 13 Jan 2023 19:48:46 +0000 (14:48 -0500)] 
ada: Use Inline aspect instead of pragma in Einfo.Utils

This package was using the Ada 83 renaming idiom for inlining
Next_Component and other Next_... procedures without inlining the
same-named functions. Using the Inline aspect avoids that sort
of horsing around.

We change all the other pragmas Inline in this package to aspects
as well, which is a more-minor improvement. Fix too-long lines
without wrapping lines.

gcc/ada/

* einfo-utils.ads, einfo-utils.adb: Get rid of the Proc_Next_...
procedures. Use Inline aspect instead of pragma Inline.
Is_Discrete_Or_Fixed_Point_Type did not have pragma Inline, but
now has the aspect; this was probably an oversight
(which illustrates why aspects are better).

2 years agoada: Fix formatting inconsistency in User's Guide
Ronan Desplanques [Thu, 12 Jan 2023 14:02:49 +0000 (15:02 +0100)] 
ada: Fix formatting inconsistency in User's Guide

gcc/ada/

* doc/gnat_ugn/gnat_utility_programs.rst: Fix formatting
inconsistency.

2 years agoada: Remove duplicated code in Proc_Next_Component_Or_Discriminant
Bob Duff [Fri, 13 Jan 2023 13:34:45 +0000 (08:34 -0500)] 
ada: Remove duplicated code in Proc_Next_Component_Or_Discriminant

Proc_Next_Component_Or_Discriminant was duplicating the code
in Next_Component_Or_Discriminant.

gcc/ada/

* einfo-utils.adb:
(Proc_Next_Component_Or_Discriminant): Call
Next_Component_Or_Discriminant.

2 years agoada: Improve comment on First_Entity
Bob Duff [Fri, 13 Jan 2023 13:03:08 +0000 (08:03 -0500)] 
ada: Improve comment on First_Entity

Clarify that "act as scope" overlaps with "[sub]type".

gcc/ada/

* einfo.ads:
(First_Entity): Update comment explaining why this exists on all
[sub]types, as opposed to just the ones with associated entities.

2 years agoada: Clean up vanishing entity fields
Bob Duff [Sun, 8 Jan 2023 23:22:17 +0000 (18:22 -0500)] 
ada: Clean up vanishing entity fields

Fix all the failures caused by enabling Check_Vanishing_Fields on
entities in all cases except the case of converting to or from E_Void.
But leave Check_Vanishing_Fields disabled by default (controlled by
-gnatd_v flag), because it might be too slow even for assertions-on
mode, and we should deal with the E_Void cases eventually.

The failures are fixed either by adding calls to Reinit_Field_To_Zero,
or by changing which entities have which fields.

Note that in a series of Reinit_Field_To_Zero calls, the optional
Old_Ekind parameter is only useful on the first such call.

gcc/ada/

* atree.adb
(Check_Vanishing_Fields): Disable the check for "root/base type
only" fields. This is a bug fix -- if we're checking some subtype
S, we don't want to reach over to the root or base type and
Reinit_Field_To_Zero of that, thus modifying the field for lots of
subtypes other than S. Disable in the to/from E_Void cases. Misc
cleanup.
* gen_il-gen-gen_entities.adb: Define First_Entity, Last_Entity,
and Stored_Constraint for all type entities, because there are too
many cases where Reinit_Field_To_Zero would otherwise be needed.
In any case, it seems cleaner to have First_Entity and Last_Entity
defined in the same entity kinds.
* einfo.ads:
(First_Entity, Last_Entity, Stored_Constraint): Update comments to
reflect gen_il-gen-gen_entities.adb changes.
(Lit_Hash): Add missing "[root type only]" comment.
* exp_ch5.adb: Add Reinit_Field_To_Zero calls for vanishing
fields.
* sem_ch10.adb: Likewise.
* sem_ch6.adb: Likewise.
* sem_ch7.adb: Likewise.
* sem_ch8.adb: Likewise.
* sem_ch3.adb: Likewise. Also remove now-unnecessary
Reinit_Field_To_Zero calls.

2 years agoada: Fix internal error on instance in package body with -gnatn
Eric Botcazou [Thu, 12 Jan 2023 14:51:40 +0000 (15:51 +0100)] 
ada: Fix internal error on instance in package body with -gnatn

This plugs a small loophole in the procedure responsible for attempting to
hide entities that have been previously made public by the semantic analyzer
in package bodies.

gcc/ada/

* sem_ch7.adb (Hide_Public_Entities): Use the same condition for
subprogram bodies without specification as for those with one.

2 years agoada: Remove redundant protection against empty lists
Piotr Trojanek [Tue, 10 Jan 2023 23:16:18 +0000 (00:16 +0100)] 
ada: Remove redundant protection against empty lists

Calls to First on No_List intentionally return Empty node, so explicit
guards against No_List are unnecessary. Code cleanup; semantics is
unaffected.

gcc/ada/

* sem_util.adb (New_Copy_Tree): Remove redundant calls to Present.

2 years agoada: Simplify lookup of predecessor in homonym chain
Ronan Desplanques [Tue, 10 Jan 2023 12:49:50 +0000 (13:49 +0100)] 
ada: Simplify lookup of predecessor in homonym chain

gcc/ada/

* sem_ch8.adb (End_Scope): Simplify lookup of predecessor in
homonym chain.

2 years agoada: Accept aggregates with OTHERS clause in unchecked type conversions
Piotr Trojanek [Tue, 10 Jan 2023 23:22:03 +0000 (00:22 +0100)] 
ada: Accept aggregates with OTHERS clause in unchecked type conversions

When inlining subprogram calls in GNATprove mode, the actual parameter
is wrapped in an unchecked conversion. If this actual parameter is an
aggregate OTHERS clause, then the type of unchecked conversion allows us
to resolve this clause (just like for aggregates wrapped in a qualified
expression).

Previously such aggregates were rejected, which caused spurious and
cryptic errors; now they are accepted.

gcc/ada/

* sem_aggr.adb (Resolve_Aggregate): Accept aggregates with OTHERS
appearing inside unchecked conversions.

2 years agoada: Emit warnings for (some) ineffective static predicate tests
Steve Baird [Fri, 16 Dec 2022 00:50:05 +0000 (16:50 -0800)] 
ada: Emit warnings for (some) ineffective static predicate tests

Generate a warning if a static predicate tests for a value that
does not belong to the parent subtype. For example, in
  subtype S is Positive with Static_Predicate => S not in 0 | 11 | 222;
the 0 is ineffective because Positive already excludes that value.
Generation of this new warning is controlled by the -gnatw_s switch,
which can also be enabled via -gnatwa.

gcc/ada/

* warnsw.ads: Add a new element,
Warn_On_Ineffective_Predicate_Test, to the Opt_Warnings_Enum
enumeration type.
* warnsw.adb: Bind "-gnatw_s" to the new
Warn_On_Ineffective_Predicate_Test switch. Add the new switch to
the set of switches enabled by -gnata .
* sem_ch13.adb
(Build_Discrete_Static_Predicate): Declare new local procedure,
Warn_If_Test_Ineffective, which conditionally generates new
warning. Call this new procedure when building a new element of an
RList.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Document the -gnatw_s switch (and the corresponding -gnatw_S
switch).
* gnat_ugn.texi: Regenerate.

2 years agoada: Update comment after SPARK RM change
Yannick Moy [Tue, 24 May 2022 10:13:43 +0000 (12:13 +0200)] 
ada: Update comment after SPARK RM change

gcc/ada/

* sem_attr.adb: Update comment referring to rule number.

2 years agoada: Improve check of attribute reference
Ronan Desplanques [Mon, 9 Jan 2023 10:14:05 +0000 (11:14 +0100)] 
ada: Improve check of attribute reference

Before this patch, the front end failed to catch many illegal uses
of access attributes of task types.

This patch makes referring to the access attributes of a task type
raise an error, except in the current instance case defined in
clause 8.6 of the reference manual.

gcc/ada/

* sem_attr.adb: sem_attr.adb (Analyze_Access_Attribute): Tighten
validity check for task types.

2 years agoada: Fix minor documentation formatting issue
Ronan Desplanques [Fri, 6 Jan 2023 15:10:59 +0000 (16:10 +0100)] 
ada: Fix minor documentation formatting issue

gcc/ada/

* doc/gnat_rm/implementation_defined_characteristics.rst: Fix
minor documentation formatting issue.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

2 years agoada: Optimize 2**N to avoid explicit 'if' in modular case
Bob Duff [Fri, 6 Jan 2023 18:23:36 +0000 (13:23 -0500)] 
ada: Optimize 2**N to avoid explicit 'if' in modular case

The compiler usually turns 2**N into Shift_Left(1,N).
This patch removes the check for "shift amount too big" in the
modular case, because Shift_Left works properly in that case
(i.e. if N is very large, it returns 0).

This removes a redundant check on most hardware; Shift_Left
takes care of large shirt amounts as necessary, even though
most hardware does not.

gcc/ada/

* exp_ch4.adb
(Expand_N_Op_Expon): Remove the too-big check. Simplify. Signed
and modular cases are combined, etc. Remove code with comment "We
only handle cases where the right type is a[sic] integer", because
the right operand must always be an integer at this point.

2 years agoada: Add Check_Error_Detected before "raise Bad_Attribute"
Bob Duff [Fri, 6 Jan 2023 01:21:15 +0000 (20:21 -0500)] 
ada: Add Check_Error_Detected before "raise Bad_Attribute"

We shouldn't raise Bad_Attribute if there is no error.
This patch adds a call to Check_Error_Detected to make sure that's true.
(There are other cases where we raise Bad_Attribute;
this patch doesn't try to fix them all.)

gcc/ada/

* sem_attr.adb
(Analyze_Attribute): Add a call to Check_Error_Detected.

2 years agoada: Fix handling of pragma Warnings (Toolname, Off/On)
Yannick Moy [Fri, 6 Jan 2023 10:10:53 +0000 (11:10 +0100)] 
ada: Fix handling of pragma Warnings (Toolname, Off/On)

Pragma Warnings On/Off with a preceding toolname (which could be GNAT
or GNATprove) was ignored due an error in accessing the expression of
a pragma association in the parser. Now fixed.

gcc/ada/

* par-prag.adb (First_Arg_Is_Matching_Tool_Name): Fix access to
expression in pragma association.

2 years agoada: Fix invalid JSON for extended variant record with -gnatRj
Eric Botcazou [Wed, 4 Jan 2023 15:41:47 +0000 (16:41 +0100)] 
ada: Fix invalid JSON for extended variant record with -gnatRj

This fixes the output of -gnatRj for an extension of a tagged type which has
a variant part and also deals with the case where the parent type is private
with unknown discriminants.

gcc/ada/

* repinfo.ads (JSON output format): Document special case of
Present member of a Variant object.
* repinfo.adb (List_Structural_Record_Layout): Change the type of
Ext_Level parameter to Integer. Restrict the first recursion with
increasing levels to the fixed part and implement a second
recursion with decreasing levels for the variant part. Deal with
an extension of a type with unknown discriminants.

2 years agoada: Fix proof of runtime unit System.Value*
Claire Dross [Wed, 4 Jan 2023 13:41:30 +0000 (14:41 +0100)] 
ada: Fix proof of runtime unit System.Value*

Use cut operations to restore the proof of System.Value*.

gcc/ada/

* libgnat/s-valueu.adb: Use cut operations inside assertion to
restore proofs
* gcc-interface/Make-lang.in (GNAT_ADA_OBJS): Add s-spark and
s-spcuop dependencies.

2 years agoada: Allow pragmas Annotate between loop pragmas
Yannick Moy [Thu, 5 Jan 2023 09:18:51 +0000 (10:18 +0100)] 
ada: Allow pragmas Annotate between loop pragmas

Pragma Annotate is now allowed between loop pragmas, in order to
be able to justify separate loop checks in GNATprove.

gcc/ada/

* sem_prag.adb (Check_Grouping): Allow Annotate pragmas between
loop pragmas.

2 years agoada: INOX: prototype RFC on String Interpolation
Javier Miranda [Wed, 21 Dec 2022 18:55:50 +0000 (18:55 +0000)] 
ada: INOX: prototype RFC on String Interpolation

gcc/ada/

* doc/gnat_rm/implementation_defined_pragmas.rst
(Extensions_Allowed): Document string interpolation.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

2 years agoada: GNAT UGN: Add section documenting PIE being enabled by default on Linux
Joel Brobecker [Tue, 6 Dec 2022 14:25:38 +0000 (18:25 +0400)] 
ada: GNAT UGN: Add section documenting PIE being enabled by default on Linux

This commit updates the Linux-specific chapter to add a new section
documenting the fact that PIE is enabled by default, and provides
some information about the impact that this might have on some
projects, as well as recommendations on how to handle issues.

gcc/ada/

* doc/gnat_ugn/platform_specific_information.rst
(_PIE_Enabled_By_Default_On_Linux): New section.
* gnat-style.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

2 years agoada: Skip dynamic interface conversion under native runtime
Javier Miranda [Mon, 2 Jan 2023 14:03:11 +0000 (14:03 +0000)] 
ada: Skip dynamic interface conversion under native runtime

gcc/ada/

* exp_disp.adb
(Has_Dispatching_Constructor_Call): New subprogram.
(Expand_Interface_Conversion): No need to perform dynamic
interface conversion when the operand and the target type are
interface types and the target interface type is an ancestor of
the operand type. The unique exception to this rule is when the
operand has a dispatching constructor call (as documented in the
sources).

2 years agoada: Reject attribute Initialize on unchecked unions
Piotr Trojanek [Thu, 22 Dec 2022 11:14:08 +0000 (12:14 +0100)] 
ada: Reject attribute Initialize on unchecked unions

Attribute Initialized is expanded into Valid_Scalars, which can't work
on unchecked unions, so Initialized on unchecked unions needs to be
rejected before expansion.

gcc/ada/

* sem_attr.adb (Analyze_Attribute): Reject attribute Initialized
on unchecked unions; fix grammar in comment.

2 years agoada: Fix Unchecked_Conversion in edge case
Ronan Desplanques [Mon, 2 Jan 2023 15:38:36 +0000 (16:38 +0100)] 
ada: Fix Unchecked_Conversion in edge case

Before this patch, Set_Can_Use_Internal_Rep was called on access
to subprogram subtypes when instantiating Unchecked_Conversion
from System.Address to an access to subprogram subtype (or the
reverse). This was incorrect and caused an assertion failure.

This patch fixes that by modifying the Can_Use_Internal_Rep
attribute of the base type of the subtype instead.

gcc/ada/

* sem_ch13.adb (Validate_Unchecked_Conversion): Fix behavior on
System.Address to access to subprogram subtype conversion.

2 years agoada: Fix link to parent when copying with Copy_Separate_Tree
Piotr Trojanek [Thu, 22 Dec 2022 22:36:47 +0000 (23:36 +0100)] 
ada: Fix link to parent when copying with Copy_Separate_Tree

When flag More_Ids is set on a node, then syntactic children will have
their Parent link set to the last node in the chain of Mode_Ids.

For example, parameter associations in declaration like:

   procedure P (X, Y : T);

will have More_Ids set for "X", Prev_Ids set on "Y" and both will have
the same node of "T" as their child. However, "T" will have only one
parent, i.e. "Y".

This anomaly was taken into account in New_Copy_Tree, but not in
Copy_Separate_Tree. This was leading to spurious errors in check for
ghost-correctness applied to copied specs.

gcc/ada/

* atree.ads
(Is_Syntactic_Node): Refactored from New_Copy_Tree.
* atree.adb
(Is_Syntactic_Node): Likewise.
(Copy_Separate_Tree): Use Is_Syntactic_Node.
* sem_util.adb
(Has_More_Ids): Move to Atree.
(Is_Syntactic_Node): Likewise.

2 years agoaarch64: PR target/99195 annotate vector compare patterns for vec-concat-zero
Kyrylo Tkachov [Mon, 15 May 2023 08:55:44 +0000 (09:55 +0100)] 
aarch64: PR target/99195 annotate vector compare patterns for vec-concat-zero

This instalment of the series goes through the vector comparison patterns in the backend.
One wart are the int64x1_t comparisons that this patch doesn't touch.
Those are a bit trickier because they have define_insn_and_split mechanisms for falling back to
GP reg comparisons after reload and I don't think a simple annotation will catch those cases correctly.
Those will need more custom thinking.
As said, this patch doesn't touch those and is a decent straightforward improvement on its own.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_cm<optab><mode>): Rename to...
(aarch64_cm<optab><mode><vczle><vczbe>): ... This.
(aarch64_cmtst<mode>): Rename to...
(aarch64_cmtst<mode><vczle><vczbe>): ... This.
(*aarch64_cmtst_same_<mode>): Rename to...
(*aarch64_cmtst_same_<mode><vczle><vczbe>): ... This.
(*aarch64_cmtstdi): Rename to...
(*aarch64_cmtstdi<vczle><vczbe>): ... This.
(aarch64_fac<optab><mode>): Rename to...
(aarch64_fac<optab><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_7.c: New test.

2 years agoaarch64: PR target/99195 annotate qabs,qneg patterns for vec-concat-zero
Kyrylo Tkachov [Mon, 15 May 2023 08:49:48 +0000 (09:49 +0100)] 
aarch64: PR target/99195 annotate qabs,qneg patterns for vec-concat-zero

Straightforward like previous patches in this series.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>): Rename to...
(aarch64_s<optab><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_4.c: Add testing for qabs, qneg.

2 years agoRISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization
Pan Li [Mon, 15 May 2023 08:18:03 +0000 (16:18 +0800)] 
RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization

This patch is optimizing the AVL for VLS auto-vectorzation.

Given below sample code:

typedef int8_t vnx2qi __attribute__ ((vector_size (2)));

__attribute__ ((noipa)) void
f_vnx2qi (int8_t a, int8_t b, int8_t *out)
{
  vnx2qi v = {a, b};
  *(vnx2qi *) out = v;
}

Before this patch:
f_vnx2qi:
        vsetvli a5,zero,e8,mf8,ta,ma
        vmv.v.x v1,a0
        vslide1down.vx  v1,v1,a1
        vse8.v  v1,0(a2)
        ret

After this patch:
f_vnx2qi:
        vsetivli        zero,2,e8,mf8,ta,ma
        vmv.v.x v1,a0
        vslide1down.vx  v1,v1,a1
        vse8.v  v1,0(a2)
        ret

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>
gcc/ChangeLog:

* config/riscv/riscv-v.cc (const_vlmax_p): New function for
deciding the mode is constant or not.
(set_len_and_policy): Optimize VLS-VLMAX code gen to vsetivli.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vf_avl-1.c: New test.

2 years agotree-optimization/109848 - fix TARGET_MEM_REF store from CTOR simplification
Richard Biener [Mon, 15 May 2023 07:10:08 +0000 (09:10 +0200)] 
tree-optimization/109848 - fix TARGET_MEM_REF store from CTOR simplification

I've put the preparation stmt in the wrong place.

PR tree-optimization/109848
* tree-ssa-forwprop.cc (pass_forwprop::execute): Put the
TARGET_MEM_REF address preparation before the store, not
before the CTOR.

2 years agoFix gcc.dg/vect/pr108950.c
Richard Biener [Thu, 11 May 2023 07:30:52 +0000 (09:30 +0200)] 
Fix gcc.dg/vect/pr108950.c

The following puts the dg-require-effective-target properly after
the dg-do.

* gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target
and dg-do.

2 years agoRISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of...
Juzhe-Zhong [Mon, 15 May 2023 06:00:59 +0000 (14:00 +0800)] 
RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of both VLA && VLS auto-vectorization

This patch optimizes both RVV VLA && VLS vectorization.

Consider this following case:
void __attribute__((noinline, noclone))
f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int
count)
{
  for (int i = 0; i < count; ++i)
    dst[i] = op1[i] + op2[i];
}

VLA:
Before this patch:
        ble a3,zero,.L1
        srli a4,a1,2
        negw a4,a4
        andi a5,a4,3
        sext.w a3,a3
        beq a5,zero,.L3
        lw a7,0(a1)
        lw a6,0(a2)
        andi a4,a4,2
        addw a6,a6,a7
        sw a6,0(a0)
        beq a4,zero,.L3
        lw a7,4(a1)
        lw a4,4(a2)
        li a6,3
        addw a4,a4,a7
        sw a4,4(a0)
        bne a5,a6,.L3
        lw a6,8(a2)
        lw a4,8(a1)
        addw a4,a4,a6
        sw a4,8(a0)
.L3:
        subw a3,a3,a5
        slli a4,a3,32
        csrr a6,vlenb
        srli a4,a4,32
        srli a6,a6,2
        slli a3,a5,2
        mv a5,a4
        bgtu a4,a6,.L17
.L5:
        csrr a6,vlenb
        add a1,a1,a3
        add a2,a2,a3
        add a0,a0,a3
        srli a7,a6,2
        li a3,0
.L8:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v1,0(a1)
        vle32.v v2,0(a2)
        vsetvli t1,zero,e32,m1,ta,ma
        add a3,a3,a7
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        mv a5,a4
        bleu a4,a3,.L6
        mv a5,a3
.L6:
        sub a5,a4,a5
        bleu a5,a7,.L7
        mv a5,a7
.L7:
        add a1,a1,a6
        add a2,a2,a6
        add a0,a0,a6
        bne a5,zero,.L8
.L1:
        ret
.L17:
        mv a5,a6
        j .L5

After this patch:
f:
        ble     a3,zero,.L1
        csrr    a4,vlenb
        srli    a4,a4,2
        mv      a5,a3
        bgtu    a3,a4,.L9
.L3:
        csrr    a6,vlenb
        li      a4,0
        srli    a7,a6,2
.L6:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v2,0(a1)
        vle32.v v1,0(a2)
        vsetvli t1,zero,e32,m1,ta,ma
        add     a4,a4,a7
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        mv      a5,a3
        bleu    a3,a4,.L4
        mv      a5,a4
.L4:
        sub     a5,a3,a5
        bleu    a5,a7,.L5
        mv      a5,a7
.L5:
        add     a0,a0,a6
        add     a2,a2,a6
        add     a1,a1,a6
        bne     a5,zero,.L6
.L1:
        ret
.L9:
        mv      a5,a4
        j       .L3

VLS:
Before this patch:
f3:
        ble a3,zero,.L1
        srli a5,a1,2
        negw a5,a5
        andi a4,a5,3
        sext.w a3,a3
        beq a4,zero,.L3
        lw a7,0(a1)
        lw a6,0(a2)
        andi a5,a5,2
        addw a6,a6,a7
        sw a6,0(a0)
        beq a5,zero,.L3
        lw a7,4(a1)
        lw a5,4(a2)
        li a6,3
        addw a5,a5,a7
        sw a5,4(a0)
        bne a4,a6,.L3
        lw a6,8(a2)
        lw a5,8(a1)
        addw a5,a5,a6
        sw a5,8(a0)
.L3:
        subw a3,a3,a4
        slli a6,a4,2
        slli a5,a3,32
        srli a5,a5,32
        add a1,a1,a6
        add a2,a2,a6
        add a0,a0,a6
        li a3,4
.L6:
        mv a4,a5
        bleu a5,a3,.L5
        li a4,4
.L5:
        vsetvli zero,a4,e32,m1,ta,ma
        vle32.v v1,0(a1)
        vle32.v v2,0(a2)
        vsetivli zero,4,e32,m1,ta,ma
        sub a5,a5,a4
        vadd.vv v1,v1,v2
        vsetvli zero,a4,e32,m1,ta,ma
        vse32.v v1,0(a0)
        addi a1,a1,16
        addi a2,a2,16
        addi a0,a0,16
        bne a5,zero,.L6
.L1:
        ret

After this patch:
f3:
        ble a3,zero,.L1
        li a4,4
.L4:
        mv a5,a3
        bleu a3,a4,.L3
        li a5,4
.L3:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v2,0(a1)
        vle32.v v1,0(a2)
        vsetivli zero,4,e32,m1,ta,ma
        sub a3,a3,a5
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        addi a2,a2,16
        addi a0,a0,16
        addi a1,a1,16
        bne a3,zero,.L4
.L1:
        ret

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

* config/riscv/riscv.cc
(riscv_vectorize_preferred_vector_alignment): New function.
(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): New target hook.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/align-1.c: New test.
* gcc.target/riscv/rvv/autovec/align-2.c: New test.

2 years agoDaily bump.
GCC Administrator [Mon, 15 May 2023 00:16:43 +0000 (00:16 +0000)] 
Daily bump.

2 years agoMATCH: Add pattern for `signbit(x) ? x : -x` into abs (and swapped)
Andrew Pinski [Sat, 13 May 2023 22:25:21 +0000 (22:25 +0000)] 
MATCH: Add pattern for `signbit(x) ? x : -x` into abs (and swapped)

This adds a simple pattern to match.pd for `signbit(x) ? x : -x`
into abs<x>. This can be done for all types even ones that honor
signed zeros and NaNs because both signbit and - are considered
only looking at/touching the sign bit of those types and does
not trap either.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/109829

gcc/ChangeLog:

* match.pd: Add pattern for `signbit(x) !=/== 0 ? x : -x`.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/abs-3.c: New test.
* gcc.dg/tree-ssa/abs-4.c: New test.

2 years agoi386: Handle unsupported modes from ix86_widen_mult_cost [PR109807]
Uros Bizjak [Sun, 14 May 2023 19:53:17 +0000 (21:53 +0200)] 
i386: Handle unsupported modes from ix86_widen_mult_cost [PR109807]

Revert my previous change that faked handling of V4HI and V2SImodes
in ix86_widen_mult_cost and rather return arbitrary high value
for unsupported modes. This should prevent cost estimator from
selecting non-existent vector widen multiply operation.

gcc/ChangeLog:

PR target/109807
* config/i386/i386.cc: Revert the 2023-05-11 change.
(ix86_widen_mult_cost): Return high value instead of
ICEing for unsupported modes.

gcc/testsuite/ChangeLog:

PR target/109807
* gcc.target/i386/pr109825.c: New test.

2 years agoi386: Honour -mdirect-extern-access when calling __fentry__
Ard Biesheuvel [Sun, 14 May 2023 16:18:38 +0000 (18:18 +0200)] 
i386: Honour -mdirect-extern-access when calling __fentry__

The small and medium PIC code models generate profiling calls that
always load the address of __fentry__() via the GOT, even if
-mdirect-extern-access is in effect.

This deviates from the behavior with respect to other external
references, and results in a longer opcode that relies on linker
relaxation to eliminate the GOT load. In this particular case, the
transformation replaces an indirect 'CALL *__fentry__@GOTPCREL(%rip)'
with either 'CALL __fentry__; NOP' or 'NOP; CALL __fentry__', where the
NOP is a 1 byte NOP that preserves the 6 byte length of the sequence.

This is problematic for the Linux kernel, which generally relies on
-mdirect-extern-access and hidden visibility to eliminate GOT based
symbol references in code generated with -fpie/-fpic, without having to
depend on linker relaxation.

The Linux kernel relies on code patching to replace these opcodes with
NOPs at runtime, and this is complicated code that we'd prefer not to
complicate even more by adding support for patching both 5 and 6 byte
sequences as well as parsing the instruction stream to decide which
variant of CALL+NOP we are dealing with.

So let's honour -mdirect-extern-access, and only load the address of
__fentry__ via the GOT if direct references to external symbols are not
permitted.

Note that the GOT reference in question is in fact a data reference: we
explicitly load the address of __fentry__ from the GOT, which amounts to
eager binding, rather than emitting a PLT call that could bind eagerly,
lazily or directly at link time.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
gcc/ChangeLog:

* config/i386/i386.cc (x86_function_profiler): Take
ix86_direct_extern_access into account when generating calls
to __fentry__()

2 years agoRISC-V: Refactor the or pattern to switch cases
Pan Li [Sun, 14 May 2023 08:15:11 +0000 (16:15 +0800)] 
RISC-V: Refactor the or pattern to switch cases

This patch refactor the pattern A or B or C or D, to the switch case for
easy add/remove new types, as well as human reading friendly.

Before this patch:
return A || B || C || D;

After this patch:
switch (type)
  {
    case A:
    case B:
    case C:
    case D:
      return true;
    default:
      return false;
  }

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

* config/riscv/riscv-vector-builtins.cc (required_extensions_p):
Refactor the or pattern to switch cases.

2 years agoDaily bump.
GCC Administrator [Sun, 14 May 2023 00:16:39 +0000 (00:16 +0000)] 
Daily bump.

2 years agoReplace bool as boolean instead of int in libgm2
Gaius Mulley [Sat, 13 May 2023 14:49:50 +0000 (15:49 +0100)] 
Replace bool as boolean instead of int in libgm2

This patch tidies KeyBoardLEDs.cc, RTco.cc, sckt.cc
and wrapc.cc by removing the TRUE/FALSE macros and using
bool, true and false.

libgm2/ChangeLog:

* libm2cor/KeyBoardLEDs.cc (TRUE): Remove.
(FALSE): Remove.
(init): Replace TRUE with true.
* libm2iso/RTco.cc (TRUE): Remove.
(FALSE): Remove.
(initSem): Replace int with bool.
(init): Replace FALSE with false.
* libm2pim/sckt.cc (TRUE): Remove.
(FALSE): Remove.
* libm2pim/wrapc.cc: Replace TRUE with true
and FALSE with false.
(FALSE): Remove.
(TRUE): Remove.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2 years ago[aarch64] Recursively intialize even and odd sub-parts and merge with zip1.
Prathamesh Kulkarni [Sat, 13 May 2023 08:56:51 +0000 (14:26 +0530)] 
[aarch64] Recursively intialize even and odd sub-parts and merge with zip1.

gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename
aarch64_expand_vector_init to this, and remove  interleaving case.
Recursively call aarch64_expand_vector_init_fallback, instead of
aarch64_expand_vector_init.
(aarch64_unzip_vector_init): New function.
(aarch64_expand_vector_init): Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldp_stp_16.c (cons2_8_float): Adjust for new
code-gen.
* gcc.target/aarch64/sve/acle/general/dupq_5.c: Likewise.
* gcc.target/aarch64/sve/acle/general/dupq_6.c: Likewise.
* gcc.target/aarch64/interleave-init-1.c: Rename to ...
* gcc.target/aarch64/vec-init-18.c: ... this.
* gcc.target/aarch64/vec-init-19.c: New test.
* gcc.target/aarch64/vec-init-20.c: Likewise.
* gcc.target/aarch64/vec-init-21.c: Likewise.
* gcc.target/aarch64/vec-init-22-size.c: Likewise.
* gcc.target/aarch64/vec-init-22-speed.c: Likewise.
* gcc.target/aarch64/vec-init-22.h: New header.

2 years agoRISC-V: Pull out function call with side effect from gcc_assert.
Kito Cheng [Sat, 13 May 2023 06:10:53 +0000 (14:10 +0800)] 
RISC-V: Pull out function call with side effect from gcc_assert.

It will broken when release mode.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns):
Pull out function call from the gcc_assert.

2 years agoRISC-V: Improve vector_insn_info::dump for LMUL and policy
Kito Cheng [Thu, 11 May 2023 08:03:55 +0000 (16:03 +0800)] 
RISC-V: Improve vector_insn_info::dump for LMUL and policy

Convert vlmul and policy to human readable string, some example below:

Before:
[VALID,Demand field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)}
AVL=(reg:DI 0 zero)
SEW=16,VLMUL=3,RATIO=2,TAIL_POLICY=1,MASK_POLICY=1]
             ^                     ^             ^

After:
[VALID,Demand field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)}
AVL=(reg:DI 0 zero)
SEW=16,VLMUL=m8,RATIO=2,TAIL_POLICY=agnostic,MASK_POLICY=agnostic]
             ^^                     ^^^^^^^^             ^^^^^^^^

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (vlmul_to_str): New.
(policy_to_str): New.
(vector_insn_info::dump): Use vlmul_to_str and policy_to_str.

2 years agoMATCH: Fix PR 109834, ICE with popcount combined with bswap
Andrew Pinski [Fri, 12 May 2023 23:33:44 +0000 (16:33 -0700)] 
MATCH: Fix PR 109834, ICE with popcount combined with bswap

After r14-673-gc0dd80e4c4c3, there was a check in the match
patterns which was checking the type is unsigned but
instead of using the type, the patch used the expression.
This adds the needed TREE_TYPE so get the correct answer and don't ICE.

Committed as obvious after a bootstrap/test on x86_64-linux-gnu.

PR tree-optimization/109834

gcc/ChangeLog:

* match.pd (popcount(bswap(x))->popcount(x)): Fix up unsigned type checking.
(popcount(rotate(x,y))->popcount(x)): Likewise.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/pr109834-1.c: New test.
* gcc.dg/tree-ssa/pr109834-1.c: New test.

2 years agoDaily bump.
GCC Administrator [Sat, 13 May 2023 00:17:14 +0000 (00:17 +0000)] 
Daily bump.

2 years agoFortran: Revise a namelist test case.
Jerry DeLisle [Fri, 12 May 2023 20:38:25 +0000 (13:38 -0700)] 
Fortran: Revise a namelist test case.

PR fortran/109662

gcc/testsuite/ChangeLog:

* gfortran.dg/pr109662-a.f90: Add a section to verify that
a short namelist read does not modify the variable.

2 years agoFortran: Initialize last_char for internal units.
Jerry DeLisle [Fri, 12 May 2023 19:23:00 +0000 (12:23 -0700)] 
Fortran: Initialize last_char for internal units.

PR fortran/109662

libgfortran/ChangeLog:

* io/unit.c (set_internal_unit): Set the internal unit
last_char to zero so that previous EOF characters do not
influence the next read.

2 years agoi386: Cleanup ix86_expand_vecop_qihi{,2}
Uros Bizjak [Fri, 12 May 2023 17:50:06 +0000 (19:50 +0200)] 
i386: Cleanup ix86_expand_vecop_qihi{,2}

Some cleanups while looking at these two functions.

gcc/ChangeLog:

* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also
reject ymm instructions for TARGET_PREFER_AVX128.  Use generic
gen_extend_insn to generate zero/sign extension instructions.
Fix comments.
(ix86_expand_vecop_qihi): Initialize interleave functions
for MULT code only.  Fix comments.

2 years agolibstdc++: Fix -Wnonnull warnings during configure
Jonathan Wakely [Fri, 12 May 2023 11:17:08 +0000 (12:17 +0100)] 
libstdc++: Fix -Wnonnull warnings during configure

We should not test for nan by passing it a null pointer, as this can
trigger -Wnonnull warnings.

Also fix an outdated comment about the default -std mode.

libstdc++-v3/ChangeLog:

* acinclude.m4 (GLIBCXX_CHECK_C99_TR1): Use a non-null pointer
to check for nan, nanf, and nanl.
* configure: Regenerate.

2 years agolibstdc++: Remove redundant dependencies on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 13:25:50 +0000 (14:25 +0100)] 
libstdc++: Remove redundant dependencies on _GLIBCXX_USE_C99_STDINT_TR1

We never need to use std::make_unsigned in std::char_traits<char16_t>
and std::char_traits<char32_t> because <cstdint> guarantees to provide
the types we need, since r9-2028-g8ba7f29e3dd064.

Similarly, experimental::source_location can just assume uint_least32_t
is defined by <cstdint>.

libstdc++-v3/ChangeLog:

* include/bits/char_traits.h (char_traits<char16_t>): Do not
depend on _GLIBCXX_USE_C99_STDINT_TR1.
(char_traits<char32_t>): Likewise.
* include/experimental/source_location: Likewise.

2 years agolibstdc++: Reduce <atomic> dependency on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 13:04:04 +0000 (14:04 +0100)] 
libstdc++: Reduce <atomic> dependency on _GLIBCXX_USE_C99_STDINT_TR1

Since r9-2028-g8ba7f29e3dd064 we've defined most of <cstdint>
unconditionally, so we can do the same for most of the std::atomic
aliases such as std::atomic_int_least32_t.

The only aliases that need to depend on _GLIBCXX_USE_C99_STDINT_TR1 are
the ones for the integer types that are not guaranteed to be defined,
e.g. std::atomic_int32_t.

libstdc++-v3/ChangeLog:

* include/std/atomic (atomic_int_least8_t, atomic_uint_least8_t)
(atomic_int_least16_t, atomic_uint_least16_t)
(atomic_int_least32_t, atomic_uint_least32_t)
(atomic_int_least64_t, atomic_uint_least64_t)
(atomic_int_fast16_t, atomic_uint_fast16_t)
(atomic_int_fast32_t, atomic_uint_fast32_t)
(atomic_int_fast64_t, atomic_uint_fast64_t)
(atomic_intmax_t, atomic_uintmax_t): Define unconditionally.
* testsuite/29_atomics/headers/stdatomic.h/c_compat.cc: Adjust.

2 years agolibstdc++: Remove <random> dependency on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 12:55:17 +0000 (13:55 +0100)] 
libstdc++: Remove <random> dependency on _GLIBCXX_USE_C99_STDINT_TR1

Since r9-2028-g8ba7f29e3dd064 we've defined most of <cstdint>
unconditionally, including uint_least32_t. This means that all of
<random> can be defined unconditionally, which means that std::shuffle
and std::ranges::shuffle can be too.

libstdc++-v3/ChangeLog:

* include/bits/algorithmfwd.h (shuffle): Do not depend on
_GLIBCXX_USE_C99_STDINT_TR1.
* include/bits/ranges_algo.h (shuffle): Likewise.
* include/bits/stl_algo.h (shuffle): Likewise.
* include/ext/random: Likewise.
* include/ext/throw_allocator.h (random_condition): Likewise.
* include/std/random: Likewise.
* src/c++11/cow-string-inst.cc: Likewise.
* src/c++11/random.cc: Likewise.

2 years agoPR modula2/109830 m2iso library SeqFile.mod appending to a file overwrites content
Gaius Mulley [Fri, 12 May 2023 16:44:29 +0000 (17:44 +0100)] 
PR modula2/109830 m2iso library SeqFile.mod appending to a file overwrites content

This patch is for the m2iso library SeqFile.mod to fix a bug when a
file is opened using OpenAppend.  The patch checks to see if the file
exists and it uses FIO.OpenForRandom to ensure the file is not
overwritten.

gcc/m2/ChangeLog:

PR modula2/109830
* gm2-libs-iso/SeqFile.mod (newCid): New parameter toAppend
used to select FIO.OpenForRandom.
(OpenRead): Pass extra parameter to newCid.
(OpenWrite): Pass extra parameter to newCid.
(OpenAppend): Pass extra parameter to newCid.

gcc/testsuite/ChangeLog:

PR modula2/109830
* gm2/isolib/run/pass/seqappend.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2 years agoi386: Remove mulv2si emulated sequence for TARGET_SSE2 [PR109797]
Uros Bizjak [Fri, 12 May 2023 16:37:13 +0000 (18:37 +0200)] 
i386: Remove mulv2si emulated sequence for TARGET_SSE2 [PR109797]

Remove mulv2si emulated sequence for TARGET_SSE2 and enable
only native PMULLD instruction for TARGET_SSE4_1.  Ideally, the
vectorization for TARGET_SSE2 should depend on more precise cost
estimation (the PR contains patch for ix86_multiplication_cost),
but even with patched cost function the runtime regression
was not fixed.

PR target/109797

gcc/ChangeLog:

* config/i386/mmx.md (mulv2si3): Remove expander.
(mulv2si3): Rename insn pattern from *mulv2si.

2 years agoLTO: Fix writing of toplevel asm with offloading [PR109816]
Tobias Burnus [Fri, 12 May 2023 14:27:40 +0000 (16:27 +0200)] 
LTO: Fix writing of toplevel asm with offloading [PR109816]

When offloading was enabled, top-level 'asm' were added to the offloading
section, confusing assemblers which did not support the syntax. Additionally,
with offloading and -flto, the top-level assembler code did not end up
in the host files.

As r14-321-g9a41d2cdbcd added top-level 'asm' to one libstdc++ header file,
the issue became more apparent, causing fails with nvptx for some
C++ testcases.

PR libstdc++/109816

gcc/ChangeLog:

* lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by
'!lto_stream_offload_p'.

libgomp/ChangeLog:

* testsuite/libgomp.c++/target-map-class-1.C: New test.
* testsuite/libgomp.c++/target-map-class-2.C: New test.

2 years agolibstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 12:44:21 +0000 (13:44 +0100)] 
libstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1

This should have been done in r9-2028-g8ba7f29e3dd064 when
std::shared_mutex was changed to be defined without depending on
_GLIBCXX_USE_C99_STDINT_TR1.

libstdc++-v3/ChangeLog:

* testsuite/experimental/feat-cxx14.cc: Remove dependency on
_GLIBCXX_USE_C99_STDINT_TR1.

2 years agolibstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 12:38:50 +0000 (13:38 +0100)] 
libstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1

This should have been removed in r9-2029-g612c9c702e2c9e when the
char16_t and char32_t specializations of std::codecvt were changed to be
defined unconditionally.

libstdc++-v3/ChangeLog:

* testsuite/22_locale/locale/cons/unicode.cc: Remove dependency
on _GLIBCXX_USE_C99_STDINT_TR1.

2 years agolibstdc++: Remove test dependencies on _GLIBCXX_USE_C99_STDINT_TR1
Jonathan Wakely [Fri, 12 May 2023 12:34:37 +0000 (13:34 +0100)] 
libstdc++: Remove test dependencies on _GLIBCXX_USE_C99_STDINT_TR1

These #ifdef checks should have been removed in r9-2029-g612c9c702e2c9e
when the u16string_view and u32string_view aliases were changed to be
defined unconditionally.

libstdc++-v3/ChangeLog:

* testsuite/21_strings/basic_string_view/typedefs.cc: Remove
dependency on _GLIBCXX_USE_C99_STDINT_TR1.
* testsuite/experimental/string_view/typedefs.cc: Likewise.

2 years agoRISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743]
Kito Cheng [Fri, 12 May 2023 02:26:06 +0000 (10:26 +0800)] 
RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743]

Rebase to trunk and send V3 patch for:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html

This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.

This issue happens is because we are currently very conservative in optimization of user vsetvli.

Consider this following case:

bb 1:
  vsetvli a5,a4... (demand AVL = a4).
bb 2:
  RVV insn use a5 (demand AVL = a5).

LCM will hoist vsetvl of bb 2 into bb 1.
We don't do AVL propagation for this situation since it's complicated that
we should analyze the code sequence between vsetvli in bb 1 and RVV insn in bb 2.
They are not necessary the consecutive blocks.

This patch is doing the optimizations after LCM, we will check and eliminate the vsetvli
in LCM inserted edge if such vsetvli is redundant. Such approach is much simplier and safe.

code:
void
foo2 (int32_t *a, int32_t *b, int n)
{
  if (n <= 0)
      return;
  int i = n;
  size_t vl = __riscv_vsetvl_e32m1 (i);

  for (; i >= 0; i--)
  {
    vint32m1_t v = __riscv_vle32_v_i32m1 (a, vl);
    __riscv_vse32_v_i32m1 (b, v, vl);

    if (i >= vl)
      continue;

    if (i == 0)
      return;

    vl = __riscv_vsetvl_e32m1 (i);
  }
}

Before this patch:
foo2:
.LFB2:
.cfi_startproc
ble     a2,zero,.L1
mv      a4,a2
li      a3,-1
vsetvli a5,a2,e32,m1,ta,mu
vsetvli zero,a5,e32,m1,ta,ma  <- can be eliminated.
.L5:
vle32.v v1,0(a0)
vse32.v v1,0(a1)
bgeu    a4,a5,.L3
.L10:
beq     a2,zero,.L1
vsetvli a5,a4,e32,m1,ta,mu
addi    a4,a4,-1
vsetvli zero,a5,e32,m1,ta,ma  <- can be eliminated.
vle32.v v1,0(a0)
vse32.v v1,0(a1)
addiw   a2,a2,-1
bltu    a4,a5,.L10
.L3:
addiw   a2,a2,-1
addi    a4,a4,-1
bne     a2,a3,.L5
.L1:
ret

After this patch:
f:
ble     a2,zero,.L1
mv      a4,a2
li      a3,-1
vsetvli a5,a2,e32,m1,ta,ma
.L5:
vle32.v v1,0(a0)
vse32.v v1,0(a1)
bgeu    a4,a5,.L3
.L10:
beq     a2,zero,.L1
vsetvli a5,a4,e32,m1,ta,ma
addi    a4,a4,-1
vle32.v v1,0(a0)
vse32.v v1,0(a1)
addiw   a2,a2,-1
bltu    a4,a5,.L10
.L3:
addiw   a2,a2,-1
addi    a4,a4,-1
bne     a2,a3,.L5
.L1:
ret

PR target/109743

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vsetvl_at_end): New.
(local_avl_compatible_p): New.
(pass_vsetvl::local_eliminate_vsetvl_insn): Enhance local optimizations
for LCM, rewrite as a backward algorithm.
(pass_vsetvl::cleanup_insns): Use new local_eliminate_vsetvl_insn
interface, handle a BB at once.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109743-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-4.c: New test.

Co-authored-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2 years agotree-optimization/64731 - extend store-from CTOR lowering to TARGET_MEM_REF
Richard Biener [Fri, 12 May 2023 11:43:27 +0000 (13:43 +0200)] 
tree-optimization/64731 - extend store-from CTOR lowering to TARGET_MEM_REF

The following also covers TARGET_MEM_REF when decomposing stores from
CTORs to supported elementwise operations.  This avoids spilling
and cleans up after vector lowering which doesn't touch loads or
stores.  It also mimics what we already do for loads.

PR tree-optimization/64731
* tree-ssa-forwprop.cc (pass_forwprop::execute): Also
handle TARGET_MEM_REF destinations of stores from vector
CTORs.

* gcc.target/i386/pr64731.c: New testcase.

2 years agoc++: remove redundant testcase [PR83258]
Patrick Palka [Fri, 12 May 2023 12:37:54 +0000 (08:37 -0400)] 
c++: remove redundant testcase [PR83258]

I noticed only after the fact that the new testcase template/function2.C
(from r14-708-gc3afdb8ba8f183) is just a subset of ext/visibility/anon8.C,
so let's get rid of it.

PR c++/83258

gcc/testsuite/ChangeLog:

* g++.dg/ext/visibility/anon8.C: Mention PR83258.
* g++.dg/template/function2.C: Removed.

2 years agoc++: robustify testcase [PR109752]
Patrick Palka [Fri, 12 May 2023 12:36:37 +0000 (08:36 -0400)] 
c++: robustify testcase [PR109752]

This rewrites the testcase for PR109752 to make it simpler and more
robust (i.e. no longer dependent on r13-4035-gc41bbfcaf9d6ef).

PR c++/109752

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-pr109752.C: Rename to ...
* g++.dg/cpp2a/concepts-complete4.C: ... this.  Rewrite.

2 years agotree-optimization/109791 - simplify (unsigned)&foo - (unsigned)(&foo + o)
Richard Biener [Thu, 11 May 2023 12:28:11 +0000 (14:28 +0200)] 
tree-optimization/109791 - simplify (unsigned)&foo - (unsigned)(&foo + o)

The following adds another variant of address difference simplification.
The utility ptr_difference_const only handles constant differences
(we also cannot code generate anything else), so exposing a possible
POINTER_PLUS_EXPR in the match and computing the difference on the
base only makes it possible to handle one case of a variable offset.
This simplifies

(unsigned long) &MEM <char[3]> [(void *)&str + 2B] - (unsigned long) (&str + (_69 + 1))

down to (1 - (unsigned long) _69) during niter analysis, allowing
ranger to eliminate a condition later and avoiding a bogus
-Wstringop-overflow diagnostic for the testcase in the PR.

PR tree-optimization/109791
* match.pd (minus (convert ADDR_EXPR@0) (convert (pointer_plus @1 @2))):
New pattern.
(minus (convert (pointer_plus @1 @2)) (convert ADDR_EXPR@0)):
Likewise.

2 years agoarm: [MVE intrinsics] rework vsriq
Christophe Lyon [Tue, 28 Feb 2023 16:12:44 +0000 (16:12 +0000)] 
arm: [MVE intrinsics] rework vsriq

Implement vsriq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vsriq): New.
* config/arm/arm-mve-builtins-base.def (vsriq): New.
* config/arm/arm-mve-builtins-base.h (vsriq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsriq.
* config/arm/arm_mve.h (vsriq): Remove.
(vsriq_m): Remove.
(vsriq_n_u8): Remove.
(vsriq_n_s8): Remove.
(vsriq_n_u16): Remove.
(vsriq_n_s16): Remove.
(vsriq_n_u32): Remove.
(vsriq_n_s32): Remove.
(vsriq_m_n_s8): Remove.
(vsriq_m_n_u8): Remove.
(vsriq_m_n_s16): Remove.
(vsriq_m_n_u16): Remove.
(vsriq_m_n_s32): Remove.
(vsriq_m_n_u32): Remove.
(__arm_vsriq_n_u8): Remove.
(__arm_vsriq_n_s8): Remove.
(__arm_vsriq_n_u16): Remove.
(__arm_vsriq_n_s16): Remove.
(__arm_vsriq_n_u32): Remove.
(__arm_vsriq_n_s32): Remove.
(__arm_vsriq_m_n_s8): Remove.
(__arm_vsriq_m_n_u8): Remove.
(__arm_vsriq_m_n_s16): Remove.
(__arm_vsriq_m_n_u16): Remove.
(__arm_vsriq_m_n_s32): Remove.
(__arm_vsriq_m_n_u32): Remove.
(__arm_vsriq): Remove.
(__arm_vsriq_m): Remove.

2 years agoarm: [MVE intrinsics] factorize vsriq
Christophe Lyon [Tue, 28 Feb 2023 16:12:29 +0000 (16:12 +0000)] 
arm: [MVE intrinsics] factorize vsriq

Factorize vsriq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vsri.
* config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): .,. this.
(mve_vsriq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

2 years agoarm: [MVE intrinsics] add ternary_rshift shape
Christophe Lyon [Fri, 3 Mar 2023 10:20:29 +0000 (10:20 +0000)] 
arm: [MVE intrinsics] add ternary_rshift shape

This patch adds the ternary_rshift shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.

2 years agoarm: [MVE intrinsics] rework vsliq
Christophe Lyon [Tue, 28 Feb 2023 17:33:36 +0000 (17:33 +0000)] 
arm: [MVE intrinsics] rework vsliq

Implement vsliq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vsliq): New.
* config/arm/arm-mve-builtins-base.def (vsliq): New.
* config/arm/arm-mve-builtins-base.h (vsliq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsliq.
* config/arm/arm_mve.h (vsliq): Remove.
(vsliq_m): Remove.
(vsliq_n_u8): Remove.
(vsliq_n_s8): Remove.
(vsliq_n_u16): Remove.
(vsliq_n_s16): Remove.
(vsliq_n_u32): Remove.
(vsliq_n_s32): Remove.
(vsliq_m_n_s8): Remove.
(vsliq_m_n_s32): Remove.
(vsliq_m_n_s16): Remove.
(vsliq_m_n_u8): Remove.
(vsliq_m_n_u32): Remove.
(vsliq_m_n_u16): Remove.
(__arm_vsliq_n_u8): Remove.
(__arm_vsliq_n_s8): Remove.
(__arm_vsliq_n_u16): Remove.
(__arm_vsliq_n_s16): Remove.
(__arm_vsliq_n_u32): Remove.
(__arm_vsliq_n_s32): Remove.
(__arm_vsliq_m_n_s8): Remove.
(__arm_vsliq_m_n_s32): Remove.
(__arm_vsliq_m_n_s16): Remove.
(__arm_vsliq_m_n_u8): Remove.
(__arm_vsliq_m_n_u32): Remove.
(__arm_vsliq_m_n_u16): Remove.
(__arm_vsliq): Remove.
(__arm_vsliq_m): Remove.

2 years agoarm: [MVE intrinsics] factorize vsliq
Christophe Lyon [Mon, 27 Feb 2023 19:16:43 +0000 (19:16 +0000)] 
arm: [MVE intrinsics] factorize vsliq

Factorize vsliq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vsliq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

2 years agoarm: [MVE intrinsics] add ternary_lshift shape
Christophe Lyon [Tue, 28 Feb 2023 16:00:59 +0000 (16:00 +0000)] 
arm: [MVE intrinsics] add ternary_lshift shape

This patch adds the ternary_lshift shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.

2 years agoarm: [MVE intrinsics] rework vpselq
Christophe Lyon [Tue, 28 Feb 2023 15:51:01 +0000 (15:51 +0000)] 
arm: [MVE intrinsics] rework vpselq

Implement vpselq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vpselq): New.
* config/arm/arm-mve-builtins-base.def (vpselq): New.
* config/arm/arm-mve-builtins-base.h (vpselq): New.
* config/arm/arm_mve.h (vpselq): Remove.
(vpselq_u8): Remove.
(vpselq_s8): Remove.
(vpselq_u16): Remove.
(vpselq_s16): Remove.
(vpselq_u32): Remove.
(vpselq_s32): Remove.
(vpselq_u64): Remove.
(vpselq_s64): Remove.
(vpselq_f16): Remove.
(vpselq_f32): Remove.
(__arm_vpselq_u8): Remove.
(__arm_vpselq_s8): Remove.
(__arm_vpselq_u16): Remove.
(__arm_vpselq_s16): Remove.
(__arm_vpselq_u32): Remove.
(__arm_vpselq_s32): Remove.
(__arm_vpselq_u64): Remove.
(__arm_vpselq_s64): Remove.
(__arm_vpselq_f16): Remove.
(__arm_vpselq_f32): Remove.
(__arm_vpselq): Remove.

2 years agoarm: [MVE intrinsics] add vpsel shape
Christophe Lyon [Tue, 28 Feb 2023 15:50:16 +0000 (15:50 +0000)] 
arm: [MVE intrinsics] add vpsel shape

This patch adds the vpsel shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (vpsel): New.
* config/arm/arm-mve-builtins-shapes.h (vpsel): New.

2 years agoarm: [MVE intrinsics] factorize vpselq
Christophe Lyon [Tue, 28 Feb 2023 15:49:58 +0000 (15:49 +0000)] 
arm: [MVE intrinsics] factorize vpselq

Factorize vpselq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of
gen_mve_vpselq.
* config/arm/iterators.md (MVE_VPSELQ_F): New.
(mve_insn): Add vpsel.
* config/arm/mve.md (@mve_vpselq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(@mve_vpselq_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this.

2 years agoarm: [MVE intrinsics] rework vfmaq vfmasq vfmsq
Christophe Lyon [Tue, 28 Feb 2023 14:37:26 +0000 (14:37 +0000)] 
arm: [MVE intrinsics] rework vfmaq vfmasq vfmsq

Implement vfmaq, vfmasq, vfmsq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.h (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vfmaq, vfmasq,
vfmsq.
* config/arm/arm_mve.h (vfmaq): Remove.
(vfmasq): Remove.
(vfmsq): Remove.
(vfmaq_m): Remove.
(vfmasq_m): Remove.
(vfmsq_m): Remove.
(vfmaq_f16): Remove.
(vfmaq_n_f16): Remove.
(vfmasq_n_f16): Remove.
(vfmsq_f16): Remove.
(vfmaq_f32): Remove.
(vfmaq_n_f32): Remove.
(vfmasq_n_f32): Remove.
(vfmsq_f32): Remove.
(vfmaq_m_f32): Remove.
(vfmaq_m_f16): Remove.
(vfmaq_m_n_f32): Remove.
(vfmaq_m_n_f16): Remove.
(vfmasq_m_n_f32): Remove.
(vfmasq_m_n_f16): Remove.
(vfmsq_m_f32): Remove.
(vfmsq_m_f16): Remove.
(__arm_vfmaq_f16): Remove.
(__arm_vfmaq_n_f16): Remove.
(__arm_vfmasq_n_f16): Remove.
(__arm_vfmsq_f16): Remove.
(__arm_vfmaq_f32): Remove.
(__arm_vfmaq_n_f32): Remove.
(__arm_vfmasq_n_f32): Remove.
(__arm_vfmsq_f32): Remove.
(__arm_vfmaq_m_f32): Remove.
(__arm_vfmaq_m_f16): Remove.
(__arm_vfmaq_m_n_f32): Remove.
(__arm_vfmaq_m_n_f16): Remove.
(__arm_vfmasq_m_n_f32): Remove.
(__arm_vfmasq_m_n_f16): Remove.
(__arm_vfmsq_m_f32): Remove.
(__arm_vfmsq_m_f16): Remove.
(__arm_vfmaq): Remove.
(__arm_vfmasq): Remove.
(__arm_vfmsq): Remove.
(__arm_vfmaq_m): Remove.
(__arm_vfmasq_m): Remove.
(__arm_vfmsq_m): Remove.

2 years agoarm: [MVE intrinsics] factorize vfmaq vfmsq vfmasq
Christophe Lyon [Tue, 28 Feb 2023 14:36:42 +0000 (14:36 +0000)] 
arm: [MVE intrinsics] factorize vfmaq vfmsq vfmasq

Factorize vmvnq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F,
VFMSQ_M_F.
(MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F.
(MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New.
(mve_insn): Add vfma, vfmas, vfms.
* config/arm/mve.md (mve_vfmaq_f<mode>, mve_vfmsq_f<mode>): Merge
into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vfmaq_n_f<mode>, mve_vfmasq_n_f<mode>): Merge into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vfmaq_m_f<mode>, mve_vfmsq_m_f<mode>): Merge into
@mve_<mve_insn>q_m_f<mode>.
(mve_vfmaq_m_n_f<mode>, mve_vfmasq_m_n_f<mode>): Merge into
@mve_<mve_insn>q_m_n_f<mode>.

2 years agoarm: [MVE intrinsics] add ternary_opt_n shape
Christophe Lyon [Tue, 28 Feb 2023 14:37:06 +0000 (14:37 +0000)] 
arm: [MVE intrinsics] add ternary_opt_n shape

This patch adds the ternary_opt_n shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.

2 years agoarm: [MVE intrinsics] rework vmvnq
Christophe Lyon [Mon, 27 Feb 2023 18:50:53 +0000 (18:50 +0000)] 
arm: [MVE intrinsics] rework vmvnq

Implement vmvnq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc
(FUNCTION_WITH_RTX_M_N_NO_F): New.
(vmvnq): New.
* config/arm/arm-mve-builtins-base.def (vmvnq): New.
* config/arm/arm-mve-builtins-base.h (vmvnq): New.
* config/arm/arm_mve.h (vmvnq): Remove.
(vmvnq_m): Remove.
(vmvnq_x): Remove.
(vmvnq_s8): Remove.
(vmvnq_s16): Remove.
(vmvnq_s32): Remove.
(vmvnq_n_s16): Remove.
(vmvnq_n_s32): Remove.
(vmvnq_u8): Remove.
(vmvnq_u16): Remove.
(vmvnq_u32): Remove.
(vmvnq_n_u16): Remove.
(vmvnq_n_u32): Remove.
(vmvnq_m_u8): Remove.
(vmvnq_m_s8): Remove.
(vmvnq_m_u16): Remove.
(vmvnq_m_s16): Remove.
(vmvnq_m_u32): Remove.
(vmvnq_m_s32): Remove.
(vmvnq_m_n_s16): Remove.
(vmvnq_m_n_u16): Remove.
(vmvnq_m_n_s32): Remove.
(vmvnq_m_n_u32): Remove.
(vmvnq_x_s8): Remove.
(vmvnq_x_s16): Remove.
(vmvnq_x_s32): Remove.
(vmvnq_x_u8): Remove.
(vmvnq_x_u16): Remove.
(vmvnq_x_u32): Remove.
(vmvnq_x_n_s16): Remove.
(vmvnq_x_n_s32): Remove.
(vmvnq_x_n_u16): Remove.
(vmvnq_x_n_u32): Remove.
(__arm_vmvnq_s8): Remove.
(__arm_vmvnq_s16): Remove.
(__arm_vmvnq_s32): Remove.
(__arm_vmvnq_n_s16): Remove.
(__arm_vmvnq_n_s32): Remove.
(__arm_vmvnq_u8): Remove.
(__arm_vmvnq_u16): Remove.
(__arm_vmvnq_u32): Remove.
(__arm_vmvnq_n_u16): Remove.
(__arm_vmvnq_n_u32): Remove.
(__arm_vmvnq_m_u8): Remove.
(__arm_vmvnq_m_s8): Remove.
(__arm_vmvnq_m_u16): Remove.
(__arm_vmvnq_m_s16): Remove.
(__arm_vmvnq_m_u32): Remove.
(__arm_vmvnq_m_s32): Remove.
(__arm_vmvnq_m_n_s16): Remove.
(__arm_vmvnq_m_n_u16): Remove.
(__arm_vmvnq_m_n_s32): Remove.
(__arm_vmvnq_m_n_u32): Remove.
(__arm_vmvnq_x_s8): Remove.
(__arm_vmvnq_x_s16): Remove.
(__arm_vmvnq_x_s32): Remove.
(__arm_vmvnq_x_u8): Remove.
(__arm_vmvnq_x_u16): Remove.
(__arm_vmvnq_x_u32): Remove.
(__arm_vmvnq_x_n_s16): Remove.
(__arm_vmvnq_x_n_s32): Remove.
(__arm_vmvnq_x_n_u16): Remove.
(__arm_vmvnq_x_n_u32): Remove.
(__arm_vmvnq): Remove.
(__arm_vmvnq_m): Remove.
(__arm_vmvnq_x): Remove.

2 years agoarm: [MVE intrinsics] factorize vmvnq
Christophe Lyon [Mon, 27 Feb 2023 18:50:28 +0000 (18:50 +0000)] 
arm: [MVE intrinsics] factorize vmvnq

Factorize vmvnq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vmvn.
* config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vmvnq_m_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vmvnq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

2 years agoarm: [MVE intrinsics] add mvn shape
Christophe Lyon [Mon, 27 Feb 2023 18:50:04 +0000 (18:50 +0000)] 
arm: [MVE intrinsics] add mvn shape

This patch adds the mvn shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (mvn): New.
* config/arm/arm-mve-builtins-shapes.h (mvn): New.

2 years agoarm: [MVE intrinsics] rework vbrsrq
Christophe Lyon [Mon, 27 Feb 2023 18:07:40 +0000 (18:07 +0000)] 
arm: [MVE intrinsics] rework vbrsrq

Implement vbrsrq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vbrsrq): New.
* config/arm/arm-mve-builtins-base.def (vbrsrq): New.
* config/arm/arm-mve-builtins-base.h (vbrsrq): New.
* config/arm/arm_mve.h (vbrsrq): Remove.
(vbrsrq_m): Remove.
(vbrsrq_x): Remove.
(vbrsrq_n_f16): Remove.
(vbrsrq_n_f32): Remove.
(vbrsrq_n_u8): Remove.
(vbrsrq_n_s8): Remove.
(vbrsrq_n_u16): Remove.
(vbrsrq_n_s16): Remove.
(vbrsrq_n_u32): Remove.
(vbrsrq_n_s32): Remove.
(vbrsrq_m_n_s8): Remove.
(vbrsrq_m_n_s32): Remove.
(vbrsrq_m_n_s16): Remove.
(vbrsrq_m_n_u8): Remove.
(vbrsrq_m_n_u32): Remove.
(vbrsrq_m_n_u16): Remove.
(vbrsrq_m_n_f32): Remove.
(vbrsrq_m_n_f16): Remove.
(vbrsrq_x_n_s8): Remove.
(vbrsrq_x_n_s16): Remove.
(vbrsrq_x_n_s32): Remove.
(vbrsrq_x_n_u8): Remove.
(vbrsrq_x_n_u16): Remove.
(vbrsrq_x_n_u32): Remove.
(vbrsrq_x_n_f16): Remove.
(vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq_n_u8): Remove.
(__arm_vbrsrq_n_s8): Remove.
(__arm_vbrsrq_n_u16): Remove.
(__arm_vbrsrq_n_s16): Remove.
(__arm_vbrsrq_n_u32): Remove.
(__arm_vbrsrq_n_s32): Remove.
(__arm_vbrsrq_m_n_s8): Remove.
(__arm_vbrsrq_m_n_s32): Remove.
(__arm_vbrsrq_m_n_s16): Remove.
(__arm_vbrsrq_m_n_u8): Remove.
(__arm_vbrsrq_m_n_u32): Remove.
(__arm_vbrsrq_m_n_u16): Remove.
(__arm_vbrsrq_x_n_s8): Remove.
(__arm_vbrsrq_x_n_s16): Remove.
(__arm_vbrsrq_x_n_s32): Remove.
(__arm_vbrsrq_x_n_u8): Remove.
(__arm_vbrsrq_x_n_u16): Remove.
(__arm_vbrsrq_x_n_u32): Remove.
(__arm_vbrsrq_n_f16): Remove.
(__arm_vbrsrq_n_f32): Remove.
(__arm_vbrsrq_m_n_f32): Remove.
(__arm_vbrsrq_m_n_f16): Remove.
(__arm_vbrsrq_x_n_f16): Remove.
(__arm_vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq): Remove.
(__arm_vbrsrq_m): Remove.
(__arm_vbrsrq_x): Remove.

2 years agoarm: [MVE intrinsics] factorize vrbsrq
Christophe Lyon [Mon, 27 Feb 2023 18:06:41 +0000 (18:06 +0000)] 
arm: [MVE intrinsics] factorize vrbsrq

Factorize vrbsrq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vbrsrq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.

2 years agoarm: [MVE intrinsics] add binary_imm32 shape
Christophe Lyon [Mon, 27 Feb 2023 18:25:32 +0000 (18:25 +0000)] 
arm: [MVE intrinsics] add binary_imm32 shape

This patch adds the binary_imm32 shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.

2 years agoarm: [MVE intrinsics] rework vqshluq
Christophe Lyon [Mon, 27 Feb 2023 14:13:47 +0000 (14:13 +0000)] 
arm: [MVE intrinsics] rework vqshluq

Implement vqshluq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vqshluq): New.
* config/arm/arm-mve-builtins-base.def (vqshluq): New.
* config/arm/arm-mve-builtins-base.h (vqshluq): New.
* config/arm/arm_mve.h (vqshluq): Remove.
(vqshluq_m): Remove.
(vqshluq_n_s8): Remove.
(vqshluq_n_s16): Remove.
(vqshluq_n_s32): Remove.
(vqshluq_m_n_s8): Remove.
(vqshluq_m_n_s16): Remove.
(vqshluq_m_n_s32): Remove.
(__arm_vqshluq_n_s8): Remove.
(__arm_vqshluq_n_s16): Remove.
(__arm_vqshluq_n_s32): Remove.
(__arm_vqshluq_m_n_s8): Remove.
(__arm_vqshluq_m_n_s16): Remove.
(__arm_vqshluq_m_n_s32): Remove.
(__arm_vqshluq): Remove.
(__arm_vqshluq_m): Remove.

2 years agoarm: [MVE intrinsics] factorize vqshluq
Christophe Lyon [Mon, 27 Feb 2023 14:13:00 +0000 (14:13 +0000)] 
arm: [MVE intrinsics] factorize vqshluq

Factorize vqshluq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vqshlu.
(supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
(VQSHLUQ_M_N, VQSHLUQ_N): New.
* config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshluq_m_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

2 years agoarm: [MVE intrinsics] add binary_lshift_unsigned shape
Christophe Lyon [Mon, 27 Feb 2023 14:13:26 +0000 (14:13 +0000)] 
arm: [MVE intrinsics] add binary_lshift_unsigned shape

This patch adds the binary_lshift_unsigned shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc
(binary_lshift_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_lshift_unsigned): New.

2 years agoarm: [MVE intrinsics] rework vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq
Christophe Lyon [Mon, 27 Feb 2023 12:38:31 +0000 (12:38 +0000)] 
arm: [MVE intrinsics] rework vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq

Implement vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.def (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.h (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-functions.h: Handle vrmlaldavhaq,
vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq.
* config/arm/arm_mve.h (vrmlaldavhaq): Remove.
(vrmlaldavhaxq): Remove.
(vrmlsldavhaq): Remove.
(vrmlsldavhaxq): Remove.
(vrmlaldavhaq_p): Remove.
(vrmlaldavhaxq_p): Remove.
(vrmlsldavhaq_p): Remove.
(vrmlsldavhaxq_p): Remove.
(vrmlaldavhaq_s32): Remove.
(vrmlaldavhaq_u32): Remove.
(vrmlaldavhaxq_s32): Remove.
(vrmlsldavhaq_s32): Remove.
(vrmlsldavhaxq_s32): Remove.
(vrmlaldavhaq_p_s32): Remove.
(vrmlaldavhaq_p_u32): Remove.
(vrmlaldavhaxq_p_s32): Remove.
(vrmlsldavhaq_p_s32): Remove.
(vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq_s32): Remove.
(__arm_vrmlaldavhaq_u32): Remove.
(__arm_vrmlaldavhaxq_s32): Remove.
(__arm_vrmlsldavhaq_s32): Remove.
(__arm_vrmlsldavhaxq_s32): Remove.
(__arm_vrmlaldavhaq_p_s32): Remove.
(__arm_vrmlaldavhaq_p_u32): Remove.
(__arm_vrmlaldavhaxq_p_s32): Remove.
(__arm_vrmlsldavhaq_p_s32): Remove.
(__arm_vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq): Remove.
(__arm_vrmlaldavhaxq): Remove.
(__arm_vrmlsldavhaq): Remove.
(__arm_vrmlsldavhaxq): Remove.
(__arm_vrmlaldavhaq_p): Remove.
(__arm_vrmlaldavhaxq_p): Remove.
(__arm_vrmlsldavhaq_p): Remove.
(__arm_vrmlsldavhaxq_p): Remove.

2 years agoarm: [MVE intrinsics] factorize vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq
Christophe Lyon [Mon, 27 Feb 2023 12:37:41 +0000 (12:37 +0000)] 
arm: [MVE intrinsics] factorize vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq

Factorize vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
builtins so that they use the same parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
(MVE_VRMLxLDAVHAxQ_P): New.
(mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha,
vrmlsldavhax.
(supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S,
VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S,
VRMLALDAVHAQ_P_S.
* config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si)
(mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhaq_sv4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si)
(mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si)
(mve_vrmlsldavhaxq_p_sv4si): Merge into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.

2 years agoarm: [MVE intrinsics] rework vqdmullbq vqdmulltq
Christophe Lyon [Mon, 27 Feb 2023 10:34:04 +0000 (10:34 +0000)] 
arm: [MVE intrinsics] rework vqdmullbq vqdmulltq

Implement vqdmullbq, vqdmulltq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New.
* config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq):
New.
* config/arm/arm-mve-builtins-base.h (vqdmullbq, vqdmulltq): New.
* config/arm/arm_mve.h (vqdmulltq): Remove.
(vqdmullbq): Remove.
(vqdmullbq_m): Remove.
(vqdmulltq_m): Remove.
(vqdmulltq_s16): Remove.
(vqdmulltq_n_s16): Remove.
(vqdmullbq_s16): Remove.
(vqdmullbq_n_s16): Remove.
(vqdmulltq_s32): Remove.
(vqdmulltq_n_s32): Remove.
(vqdmullbq_s32): Remove.
(vqdmullbq_n_s32): Remove.
(vqdmullbq_m_n_s32): Remove.
(vqdmullbq_m_n_s16): Remove.
(vqdmullbq_m_s32): Remove.
(vqdmullbq_m_s16): Remove.
(vqdmulltq_m_n_s32): Remove.
(vqdmulltq_m_n_s16): Remove.
(vqdmulltq_m_s32): Remove.
(vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq_s16): Remove.
(__arm_vqdmulltq_n_s16): Remove.
(__arm_vqdmullbq_s16): Remove.
(__arm_vqdmullbq_n_s16): Remove.
(__arm_vqdmulltq_s32): Remove.
(__arm_vqdmulltq_n_s32): Remove.
(__arm_vqdmullbq_s32): Remove.
(__arm_vqdmullbq_n_s32): Remove.
(__arm_vqdmullbq_m_n_s32): Remove.
(__arm_vqdmullbq_m_n_s16): Remove.
(__arm_vqdmullbq_m_s32): Remove.
(__arm_vqdmullbq_m_s16): Remove.
(__arm_vqdmulltq_m_n_s32): Remove.
(__arm_vqdmulltq_m_n_s16): Remove.
(__arm_vqdmulltq_m_s32): Remove.
(__arm_vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq): Remove.
(__arm_vqdmullbq): Remove.
(__arm_vqdmullbq_m): Remove.
(__arm_vqdmulltq_m): Remove.