Dylan Yip [Wed, 10 Mar 2021 09:47:40 +0000 (01:47 -0800)]
arm64: zynqmp: Update DPDMA entry
As per Linux commit 7cbb0c63de3f ("dmaengine: xilinx: dpdma: Add the Xilinx
DisplayPort DMA engine driver"), the dt entry for the ZynqMP DPDMA has been
modified. So update the dt entry per the new dt bindings.
Signed-off-by: Dylan Yip <dylan.yip@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Brandon Maier [Wed, 20 Jan 2021 20:28:30 +0000 (14:28 -0600)]
spi: zynqmp_gqspi: fix set_speed bug on multiple runs
If zynqmp_qspi_set_speed() is called multiple times with the same speed,
then on the second call it will skip recalculating the baud_rate_val as
it assumes the speed is already configured correctly. But it will still
write the baud_rate_val to the configuration register and call
zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
baud_rate_val, it will use the initial value of 0 . This causes the
driver to run at maximum speed which for many spi flashes is too fast and
causes data corruption.
Instead only write out a new baud_rate_val if we have calculated the
correct baud_rate_val.
This opens up another issue with the "if (speed == 0)", we don't save
off the new plat->speed_hz value when setting the baud rate on the
speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
have speed==0 just use the same calculation as a normal speed. That will
cause the baud_rate_val to use the slowest speed possible, which is the
safest option.
Michal Simek [Thu, 11 Mar 2021 14:33:25 +0000 (15:33 +0100)]
xilinx: Sync DTs for GTRs with Linux kernel
There are several changes which happen in mainline kernel which should get
also to U-Boot. Here is the list of patches from the kernel:
- arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
- arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
- arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
- arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
but also some other changes have been done.
- Remove USB3.0 serdes configurations
- Remove SATA serdes configuration for zc1232
- Remove comments about sgmii from a2197* boards
- Update all files with psgtr which are not upstream yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 21 Jan 2021 10:26:55 +0000 (11:26 +0100)]
arm64: dts: zynqmp: Add missing mio-bank properties to sdhcis
Add missing xlnx,mio-bank property to sdhci nodes. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Michal Simek [Tue, 9 Mar 2021 11:43:42 +0000 (12:43 +0100)]
arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes
All si570 which are used for ps reference clock generation should contain
silabls,skip-recall property not to cause break on ps clock.
On Versal boards this will cause hang on Versal cpu when it is booted at
the same time with SC.
On zcu670 this can cause PS hang that's why add it for sure.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Jul 2020 09:44:43 +0000 (11:44 +0200)]
arm64: zynqmp: Add support for K26 and KV260
Add support for K26 and KV260
The support is split to 4 files for the following reason.
-k26-revA.dts - This is base DTS file which describes only SOM with
few exceptions.
a) GPIOs
b) uart at MIO34/MIO35
c) Aliases are filled even by IPs which are not enabled to have consistent
numbering scheme
-k26-revA-u-boot.dts - DTS file which targets only U-Boot project and
which is automatically pick up by u-boot at build time. It enables SD card
which is available on CC and it disable all HS modes capabilities to make
sure that u-boot is capable to read data from SD without a need to setup
tap delays for custom CCs.
-kv260-revA.dts - it is device tree overlay automatically built as dtbo
which describes CC and all features on it.
-kv260-revA-pl.dts - ML Vision description for hardware i2c switch which is
connected to PL. As of today it is here just for reference that there is a
node which needs to be described and handled by SW.
Pincntrl description is not present but it could come in future especially
in connection to SD card connection.
There is also high chance that there is going to be a need to detect CC
from u-boot that's why u-boot DTS could also contain eeprom available at CC
for detection. It doesn't need to be there but it is good to list it not to
go around driver model in u-boot.
For checking DTBo fdtoverlay command can be used to make sure that base DT
and overlays are compatible to each other:
fdtoverlay -v -i arch/arm/dts/zynqmp-sm-k26-revA.dtb \
arch/arm/dts/zynqmp-sk-kv260-revA.dtbo -o /tmp/1.dtb
For building u-boots dtb file just run make.
For building Linux dtb files don't include u-boot.dtsi in build
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Christian Kohn [Sat, 30 Jan 2021 02:37:25 +0000 (18:37 -0800)]
arm64: zynqmp: Add labels to DPSub vid and gfx layers
For the SOM aa2 use case where the video mixer PL IP is connected to the DP
subsystem, the video layer needs to be referenced from a dt overlay. Hence,
add labels for the video and graphics layers in the dpsub node.
Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Michal Simek [Mon, 5 Oct 2020 07:35:40 +0000 (09:35 +0200)]
arm64: zynqmp: Add support for SVD devices
SVD are using different name which can't be handled via zynqmp_devices
structure. That's why introduce zynqmp_detect_svd_name() which checks ID
code for these devices and show proper name for them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 18 Jan 2021 12:58:39 +0000 (13:58 +0100)]
arm64: zynqmp: Add support for zcu670-revA board
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 16 Mar 2021 12:44:58 +0000 (13:44 +0100)]
arm64: versal: Define zynqmp_mmio_write() for versal
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 16 Mar 2021 07:17:15 +0000 (08:17 +0100)]
arm64: versal: Rename bus busses to be align with simple-bus yaml
The same change has been done in Linux for Zynq and ZynqMP. Also add gic to
the same bus with other nodes to avoid issues reported on ZynqMP. For more
information please take a look at links below.
Michal Simek [Thu, 26 Nov 2020 13:25:01 +0000 (14:25 +0100)]
ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI
point-to-point channels for communicating addresses, data, and response
transactions between master and slave clients. This ARM AMBA 3.0..."
Issues are reported as:
.. amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
>From schema:
../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml
Similar change has been done for Xilinx ZynqMP SoC.
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
Robert Hancock [Thu, 11 Mar 2021 22:55:50 +0000 (16:55 -0600)]
net: gem: Fix setting PCS auto-negotiation state
The code was trying to disable PCS auto-negotiation when a fixed-link node
is present and enable it otherwise. However, the PCS registers were being
written before the PCSSEL bit was set in the network configuration
register, and it appears that in this state, PCS register writes are
ignored. The result is that the intended change only took effect on the
second network operation that was performed, since at that time PCSSEL is
already enabled.
Fix the order of register writes so that PCS registers are only written to
after the PCS is enabled.
Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Wed, 17 Mar 2021 07:01:52 +0000 (01:01 -0600)]
microblaze: Make extended addressing support default
Axi qspi controller supports 32-bit & 24-bit addressing modes
for micron, macronix & spansion flash parts. But for winbond
flashes it only supports 24-bit addressing mode.
Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode
to make 32-bit addressing mode work on all flashes.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
T Karthik Reddy [Wed, 17 Mar 2021 07:01:51 +0000 (01:01 -0600)]
spi: xilinx_spi: Add support for spi memory operations
Add support for spi memory operations for xilinx AXI qspi driver.
This provides an high-level interface to execute SPI memory
operations by the controller.
Remove existing spi transfer based implementation and use
spi memory based exec_op() implementation for qspi IO operations.
Simplified existing startup_block implementation.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Michal Simek [Thu, 26 Nov 2020 13:25:00 +0000 (14:25 +0100)]
ARM: zynq: Fix compatible string for adi,adxl345 chip
The commit e359a29225dd ("dt-bindings: iio: accel: adxl345: switch to YAML
bindings") switched binding to yaml and the following error pop up:
../zynq-zturn-v5.dt.yaml: accelerometer@53: compatible: 'oneOf' conditional
failed, one must be
fixed:
['adi,adxl345', 'adxl345', 'adi,adxl34x', 'adxl34x'] is too long
Additional items are not allowed ('adi,adxl34x', 'adxl34x' were unexpected)
Additional items are not allowed ('adxl345', 'adi,adxl34x', 'adxl34x' were
unexpected)
'adi,adxl346' was expected
'adi,adxl345' was expected
Use only one compatible string to be aligned with the binding.
Michal Simek [Thu, 26 Nov 2020 13:25:02 +0000 (14:25 +0100)]
ARM: zynq: Fix leds subnode name for zc702/zybo-z7
Fix the leds subnode names to match (^led-[0-9a-f]$|led).
Similar change has been also done by commit 9a19a39ee48b ("arm64: dts:
zynqmp: Fix leds subnode name for zcu100/ultra96 v1").
The patch is fixing these warnings:
.../zynq-zc702.dt.yaml: leds: 'ds23' does not match any of the regexes:
'(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
>From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml
.../zynq-zybo-z7.dt.yaml: gpio-leds: 'ld4' does not match any of the
regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
>From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml
Michal Simek [Mon, 24 Aug 2020 10:28:39 +0000 (12:28 +0200)]
arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
Fix the leds subnode names to match (^led-[0-9a-f]$|led).
Similar change has been also done by commit 08dc0e5dd9aa ("arm64: dts:
meson: fix leds subnodes name").
The patch is fixing this warning:
avnet-ultra96-rev1.dt.yaml: leds: 'ds2', 'ds3', 'ds4', 'ds5' do not match
any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
T Karthik Reddy [Wed, 10 Mar 2021 05:30:02 +0000 (22:30 -0700)]
mtd: spi-nor: Enable strip flag to read configuration register
In dual parallel mode, unable to read configuration register(CR)
from spansion flash to check quad enable bit due to no response
from upper flash. Add SPI_XFER_STRIPE flag to send configuration
register command to both upper and lower flashes and get
response accordingly.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
arm64: zynqmp: Rename clocks as per the Arasan NAND driver
In zynqmp.dtsi file renamed "clk_sys" clock to "controller" and
"clk_flash" clock to "bus" as per upstreamed Arasan NAND driver.
This fixes NAND driver probe failure.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Mon, 22 Feb 2021 15:39:56 +0000 (08:39 -0700)]
mtd: spi-nor: Check if block protection bits are set
When block protection is enabled, erase & write operations should
fail for the blocks which are protected. Add support for this
checking in erase and write functions by reading BP & TB bits,
throw error if the blocks are write protected.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
T Karthik Reddy [Mon, 22 Feb 2021 15:39:55 +0000 (08:39 -0700)]
mtd: spi-nor: Add block protection support for micron flashes
Micron nor flashes provide block protection support using
BP0, BP1, BP2, BP3 & TB bits in status register. This patch
supports only for micron nor flashes with manufacturer id 0x20.
Where BP(Block Protection) bits defines memory to be software
protected against PROGRAM or ERASE operations. When one or more
block protect bits are set to 1, a designated memory area is
protected from PROGRAM and ERASE operations. TB(Top/Bottom) bit
determines whether the protected memory area defined by the block
protect bits starts from the top or bottom of the memory array.
Block Protection table for N25Q00AA with size 128MB, sector size 64KB
and with 2048 sectors.
Top protection:
--------------
TB BP3 BP2 BP1 BP0 Protected Area Un-Protected Area
0 0 0 0 0 None All sectors
0 0 0 0 1 Sector 2047 Sectors (0 to 2046)
0 0 0 1 0 Sectors (2046 to 2047) Sectors (0 to 2045)
0 0 0 1 1 Sectors (2044 to 2047) Sectors (0 to 2043)
0 0 1 0 0 Sectors (2040 to 2047) Sectors (0 to 2039)
0 0 1 0 1 Sectors (2032 to 2047) Sectors (0 to 2031)
0 0 1 1 0 Sectors (2016 to 2047) Sectors (0 to 2015)
0 0 1 1 1 Sectors (1984 to 2047) Sectors (0 to 1983)
0 1 0 0 0 Sectors (1920 to 2047) Sectors (0 to 1919)
0 1 0 0 1 Sectors (1792 to 2047) Sectors (0 to 1791)
0 1 0 1 0 Sectors (1936 to 2047) Sectors (0 to 1535)
0 1 0 1 1 Sectors (1024 to 2047) None
Bottom protection:
-----------------
TB BP3 BP2 BP1 BP0 Protected Area Un-protected Area
1 0 0 0 0 None All sectors
1 0 0 0 1 sector 0 Sectors (1 to 2047)
1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 2047)
1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 2047)
1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 2047)
1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 2047)
1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 2047)
1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 2047)
1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 2047)
1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 2047)
1 1 0 1 0 Sectors (0 to 511) Sectors (512 to 2047)
1 1 0 1 1 Sectors (0 to 1023) Sectors (1024 to 2047)
Michael Walle [Wed, 10 Feb 2021 21:42:29 +0000 (22:42 +0100)]
fpga: zynqpl: fix buffer alignment
Due to pointer arithmetic, "sizeof(u32) * ARCH_DMA_MINALIGN" is
subtracted. It seems that the original intention was to just subtract
ARCH_DMA_MINALIGN. Fix it.
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: upstream (8c02d842b61ebd579e42ff3f0326457e7d10ec95)
Michal Simek [Wed, 17 Feb 2021 07:55:34 +0000 (08:55 +0100)]
arm64: zynqmp: Rename zc1275/zcu1275 to be aligned with DT name
Folder names corresponds to DT name. These boards have been renamed from
zc1275 to zcu1275 by commit shown below and this should be the part of that
commit.
Fixes: 420d44678119 ("arm64: zynqmp: Rename zc1275 to zcu1275") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
EMMC will have bus-width 8 and it is non-removable in general. These
are missing from dt node. Add bus-width and non-removable parameters
to emmc node.
Michal Simek [Tue, 9 Feb 2021 07:50:22 +0000 (08:50 +0100)]
arm64: zynqmp: Do not clear reset reason
There is no need to clear reset reason register because it is protected by
PMUFW already which is reported when verbose log is enabled as:
pm_core.c@733 APU> No write permission to 0xFF5E0220
T Karthik Reddy [Wed, 3 Feb 2021 10:10:48 +0000 (03:10 -0700)]
net: gem: Enable ethernet rx clock for versal
Enable rx clock along with tx clock for versal platform. Use compatible
data to enable/disable clocks in the driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Michal Simek [Tue, 9 Feb 2021 14:28:15 +0000 (15:28 +0100)]
clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 2 Feb 2021 16:23:29 +0000 (17:23 +0100)]
Merge xlnx_rebase_v2021.01' into master
As last year we have prepared rebase branch first and then it was merged to
master. At the same time rebase branch is going to be tuned based on the
latest upstream submission.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 13 Nov 2020 11:33:45 +0000 (12:33 +0100)]
arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending
Michal Simek [Tue, 7 Jan 2020 12:03:10 +0000 (13:03 +0100)]
arm64: versal: Add mini qspi configurations
Not all configurations are supported in mainline yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending
[michal: Squashed with
arm64: versal: Change mini uboot qspi fixed clock
arm64: versal: Disable DDR cache mapping if DDR is not enabled
xilinx: versal: Disable firmware driver for versal mini qspi
config: versal: Update mini u-boot timer clock to 100Mhz
versal: dts: Add mini ospi stacked support
configs: versal: Enable support for Gigadevice flash
+ defconfig syncup
]
Michal Simek [Mon, 11 May 2020 08:14:34 +0000 (10:14 +0200)]
arm64: zynqmp: Disable CCI by default
There is no reason to have CCI no enabled by default. Enable it when your
system configuration requires it. In Xilinx configuration flow this is
work for Device Tree Generator which reads information from HW Design
configuration.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending
Michal Simek [Tue, 11 Feb 2020 08:56:48 +0000 (09:56 +0100)]
arm64: zynqmp: Disable watchdog by default for virt platform
Disable watchdog based on request in past that not all Linux rootfs have
proper utilities ready to service it. Enable it if your rootfs have proper
watchdog handling.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending
ARM: zynq: Add nand controller node in zynq-ces-nand dt
Add memory-controller@e000e000 node in zynq-ces-nand.dts as
zynq_nand driver utilizes flash@e1000000 node. Without this
dt node mini nand u-boot does not probe.
Michal Simek [Tue, 7 Jan 2020 09:13:05 +0000 (10:13 +0100)]
ARM: zynq: Add missing OCM node
This patch is sync with Linux kernel where ocmc node is present.
Linux driver should be changed to different style and this node will likely
be remove in future.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending
T Karthik Reddy [Wed, 6 Jan 2021 04:02:15 +0000 (21:02 -0700)]
spi: zynq: Add support to detect stripe for required cmds
In dual parallel mode commands which are sent with the data
to be written into flash registers should not be striped
and data sent to flash memory regions should be striped.
So update_stripe() function returns appropriate stripe
status for specific commands.
T Karthik Reddy [Wed, 6 Jan 2021 04:02:14 +0000 (21:02 -0700)]
spi: zynq_qspi: Add SPI memory operations to zynq qspi
Spi memory operation interface is added to zynq qspi
driver to provide an high-level interface to execute
qspi controller specific memory operations by avoiding
spi_mem_exec_op() from spi-mem framework.
This change removes all the xilinx specific code from
spi-mem framework.
T Karthik Reddy [Wed, 6 Jan 2021 04:02:13 +0000 (21:02 -0700)]
spi: zynqmp_gqspi: Add SPI memory operations to zynqmp qspi
Spi memory operation interface is added to zynqmp qspi
driver to provide an high-level interface to execute
qspi controller specific memory operations by avoiding
spi_mem_exec_op() from spi-mem framework.
This change removes all the xilinx specific code from
spi-mem framework.
spi: cadence_qspi: Add function to enable/disable linear mode
ahb reads/writes needs linear mode to be enabled, dma mode needs linear
mode to be disabled. Add function to do this and call wherever it is
applicable.
Linear mode bit needs to be enabled in secure mode. Use secure calls to
enable/disable linear mode in SLCR register.
spi: cadence_qspi: Fix function prototypes and include header files
Fix function prottotype for cadence_qspi_apb_dma_read to return type
int. Also make cadence_qspi_apb_exec_flash_cmd() as non static function
as we need to use it in drivers/spi/cadence_ospi_versal.c.
Update the changed function prototypes in headerfile.
Add missing include files in drivers/spi/cadence_ospi_versal.c and
cadence_qspi.h to take care of the compilation warnings.
Michal Simek [Thu, 17 Dec 2020 13:52:08 +0000 (14:52 +0100)]
spi: zynq_qspi: Add support for dual parallel and dual stacked
Add support for dual-parallel and dual-stacked flash configurations in
zynq qspi driver. Read is-dual and is-stacked properties from dts and
populate them in plat structure.
Read spi-rx-bus-width and spi-tx-bus-width from dts and set tx_rx mode
accordingly.
T Karthik Reddy [Thu, 8 Oct 2020 11:27:19 +0000 (05:27 -0600)]
mtd: spi-nor: Fix issue with clearing BP bits for winbond flashes
Flash parts with SPI_NOR_HAS_LOCK flag should clear the status
register(SR) to disable block protection bits. In dual parallel
mode SR is cleared only on single flash instead of both. So set
SPI_XFER_STRIPE flag if dual parallel mode is enabled.
T Karthik Reddy [Thu, 8 Oct 2020 11:27:18 +0000 (05:27 -0600)]
mtd: spi: Specify winbond w25q512jv flash has BP bits set
winbond w25q512jv flash part has Block Protection bits set
on reset and this flash is write protected by default.
So set SPI_NOR_HAS_LOCK flag in the flash id table. SPI_NOR_HAS_TB
specifies status register has Top/Bottom (TB) protect bit. Must be
used with SPI_NOR_HAS_LOCK flag.
In dual parallel case when write/read data operations are performed,
odd data bytes have to be converted to even to avoid a nibble
(of data when programming / dummy when reading) going to
individual flash devices, where a byte is expected. This patch
fixes above issue.
mtd: spi-nor-ids: Fix mt35xl512 flash id and mt35xu01g entry
When mt35xu01g is connected it's size is showing up incorrectly as
512Mb. This is due to the wrong id code of mt35xl512g. Fix mt35xl512g
flash id to 0x2c5a1a, here 5a represents 3v and 1a represents 512Mb.
Also change the name of mt35xl512g to mt35xl512aba to be in sync with
mt35xu512aba. These two flashes are similar except for voltage range.
Entry for mt35xu01g is present with extended id codes. Change INFO to
INFO6 for the extended id's to work. Move the entry to above 2g flash
part. This is for the table to be in order of memory sizes.
projects / thirdparty / u-boot.git / log
