]> git.ipfire.org Git - thirdparty/gcc.git/log
thirdparty/gcc.git
13 months agoarm: [MVE intrinsics] factorize vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq vqrdmladhq...
Christophe Lyon [Fri, 24 Feb 2023 13:27:34 +0000 (13:27 +0000)] 
arm: [MVE intrinsics] factorize vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq vqrdmladhq vqrdmladhxq vqrdmlsdhq vqrdmlsdhxq

Factorize vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqrdmladhq,
vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq builtins so that they use the
same parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New.
(mve_insn): Add vqdmladh, vqdmladhx, vqdmlsdh, vqdmlsdhx,
vqrdmladh, vqrdmladhx, vqrdmlsdh, vqrdmlsdhx.
(supf): Add VQDMLADHQ_S, VQDMLADHXQ_S, VQDMLSDHQ_S, VQDMLSDHXQ_S,
VQRDMLADHQ_S,VQRDMLADHXQ_S, VQRDMLSDHQ_S, VQRDMLSDHXQ_S.
* config/arm/mve.md (mve_vqrdmladhq_s<mode>)
(mve_vqrdmladhxq_s<mode>, mve_vqrdmlsdhq_s<mode>)
(mve_vqrdmlsdhxq_s<mode>, mve_vqdmlsdhxq_s<mode>)
(mve_vqdmlsdhq_s<mode>, mve_vqdmladhxq_s<mode>)
(mve_vqdmladhq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] add ternary shape
Christophe Lyon [Fri, 24 Feb 2023 13:26:39 +0000 (13:26 +0000)] 
arm: [MVE intrinsics] add ternary shape

This patch adds the ternary shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary): New.
* config/arm/arm-mve-builtins-shapes.h (ternary): New.

13 months agoarm: [MVE intrinsics] rework vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq
Christophe Lyon [Fri, 24 Feb 2023 10:47:07 +0000 (10:47 +0000)] 
arm: [MVE intrinsics] rework vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq

Implement vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq using the
new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.h (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm_mve.h (vmlaldavaq): Remove.
(vmlaldavaxq): Remove.
(vmlsldavaq): Remove.
(vmlsldavaxq): Remove.
(vmlaldavaq_p): Remove.
(vmlaldavaxq_p): Remove.
(vmlsldavaq_p): Remove.
(vmlsldavaxq_p): Remove.
(vmlaldavaq_s16): Remove.
(vmlaldavaxq_s16): Remove.
(vmlsldavaq_s16): Remove.
(vmlsldavaxq_s16): Remove.
(vmlaldavaq_u16): Remove.
(vmlaldavaq_s32): Remove.
(vmlaldavaxq_s32): Remove.
(vmlsldavaq_s32): Remove.
(vmlsldavaxq_s32): Remove.
(vmlaldavaq_u32): Remove.
(vmlaldavaq_p_s32): Remove.
(vmlaldavaq_p_s16): Remove.
(vmlaldavaq_p_u32): Remove.
(vmlaldavaq_p_u16): Remove.
(vmlaldavaxq_p_s32): Remove.
(vmlaldavaxq_p_s16): Remove.
(vmlsldavaq_p_s32): Remove.
(vmlsldavaq_p_s16): Remove.
(vmlsldavaxq_p_s32): Remove.
(vmlsldavaxq_p_s16): Remove.
(__arm_vmlaldavaq_s16): Remove.
(__arm_vmlaldavaxq_s16): Remove.
(__arm_vmlsldavaq_s16): Remove.
(__arm_vmlsldavaxq_s16): Remove.
(__arm_vmlaldavaq_u16): Remove.
(__arm_vmlaldavaq_s32): Remove.
(__arm_vmlaldavaxq_s32): Remove.
(__arm_vmlsldavaq_s32): Remove.
(__arm_vmlsldavaxq_s32): Remove.
(__arm_vmlaldavaq_u32): Remove.
(__arm_vmlaldavaq_p_s32): Remove.
(__arm_vmlaldavaq_p_s16): Remove.
(__arm_vmlaldavaq_p_u32): Remove.
(__arm_vmlaldavaq_p_u16): Remove.
(__arm_vmlaldavaxq_p_s32): Remove.
(__arm_vmlaldavaxq_p_s16): Remove.
(__arm_vmlsldavaq_p_s32): Remove.
(__arm_vmlsldavaq_p_s16): Remove.
(__arm_vmlsldavaxq_p_s32): Remove.
(__arm_vmlsldavaxq_p_s16): Remove.
(__arm_vmlaldavaq): Remove.
(__arm_vmlaldavaxq): Remove.
(__arm_vmlsldavaq): Remove.
(__arm_vmlsldavaxq): Remove.
(__arm_vmlaldavaq_p): Remove.
(__arm_vmlaldavaxq_p): Remove.
(__arm_vmlsldavaq_p): Remove.
(__arm_vmlsldavaxq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq
Christophe Lyon [Fri, 24 Feb 2023 10:38:02 +0000 (10:38 +0000)] 
arm: [MVE intrinsics] factorize vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq

Factorize vmlaldavaq, vmlaldavaxq, vmlsldavaq, vmlsldavaxq builtins so
that they use the same parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
New.
(mve_insn): Add vmlaldava, vmlaldavax, vmlsldava, vmlsldavax.
(supf): Add VMLALDAVAXQ_P_S, VMLALDAVAXQ_S, VMLSLDAVAQ_P_S,
VMLSLDAVAQ_S, VMLSLDAVAXQ_P_S, VMLSLDAVAXQ_S.
* config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
(mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
(mve_vmlaldavaxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlaldavaq_p_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>)
(mve_vmlsldavaq_p_s<mode>, mve_vmlsldavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] add binary_acca_int64 shape
Christophe Lyon [Fri, 24 Feb 2023 10:38:26 +0000 (10:38 +0000)] 
arm: [MVE intrinsics] add binary_acca_int64 shape

This patch adds the binary_acca_int64 shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int64): New.

13 months agoarm: [MVE intrinsics] rework vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq
Christophe Lyon [Thu, 23 Feb 2023 11:56:47 +0000 (11:56 +0000)] 
arm: [MVE intrinsics] rework vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq

Implement vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq using
the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-base.def (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-base.h (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Handle vrmlaldavhq,
vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq.
* config/arm/arm_mve.h (vrmlaldavhq): Remove.
(vrmlsldavhxq): Remove.
(vrmlsldavhq): Remove.
(vrmlaldavhxq): Remove.
(vrmlaldavhq_p): Remove.
(vrmlaldavhxq_p): Remove.
(vrmlsldavhq_p): Remove.
(vrmlsldavhxq_p): Remove.
(vrmlaldavhq_u32): Remove.
(vrmlsldavhxq_s32): Remove.
(vrmlsldavhq_s32): Remove.
(vrmlaldavhxq_s32): Remove.
(vrmlaldavhq_s32): Remove.
(vrmlaldavhq_p_s32): Remove.
(vrmlaldavhxq_p_s32): Remove.
(vrmlsldavhq_p_s32): Remove.
(vrmlsldavhxq_p_s32): Remove.
(vrmlaldavhq_p_u32): Remove.
(__arm_vrmlaldavhq_u32): Remove.
(__arm_vrmlsldavhxq_s32): Remove.
(__arm_vrmlsldavhq_s32): Remove.
(__arm_vrmlaldavhxq_s32): Remove.
(__arm_vrmlaldavhq_s32): Remove.
(__arm_vrmlaldavhq_p_s32): Remove.
(__arm_vrmlaldavhxq_p_s32): Remove.
(__arm_vrmlsldavhq_p_s32): Remove.
(__arm_vrmlsldavhxq_p_s32): Remove.
(__arm_vrmlaldavhq_p_u32): Remove.
(__arm_vrmlaldavhq): Remove.
(__arm_vrmlsldavhxq): Remove.
(__arm_vrmlsldavhq): Remove.
(__arm_vrmlaldavhxq): Remove.
(__arm_vrmlaldavhq_p): Remove.
(__arm_vrmlaldavhxq_p): Remove.
(__arm_vrmlsldavhq_p): Remove.
(__arm_vrmlsldavhxq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq
Christophe Lyon [Thu, 23 Feb 2023 11:52:18 +0000 (11:52 +0000)] 
arm: [MVE intrinsics] factorize vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq

Factorize vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq
builtins so that they use the same parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P):
New.
(mve_insn): Add vrmlaldavh, vrmlaldavhx, vrmlsldavh, vrmlsldavhx.
(supf): Add VRMLALDAVHXQ_P_S, VRMLALDAVHXQ_S, VRMLSLDAVHQ_P_S,
VRMLSLDAVHQ_S, VRMLSLDAVHXQ_P_S, VRMLSLDAVHXQ_S.
* config/arm/mve.md (mve_vrmlaldavhxq_sv4si)
(mve_vrmlsldavhq_sv4si, mve_vrmlsldavhxq_sv4si)
(mve_vrmlaldavhq_<supf>v4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhq_p_sv4si)
(mve_vrmlsldavhxq_p_sv4si, mve_vrmlaldavhq_p_<supf>v4si): Merge
into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.

13 months agoarm: [MVE intrinsics] rework vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq
Christophe Lyon [Wed, 22 Feb 2023 17:09:18 +0000 (17:09 +0000)] 
arm: [MVE intrinsics] rework vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq

Implement vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq using the new
MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm-mve-builtins-base.def (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm-mve-builtins-base.h (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm_mve.h (vmlaldavq): Remove.
(vmlsldavxq): Remove.
(vmlsldavq): Remove.
(vmlaldavxq): Remove.
(vmlaldavq_p): Remove.
(vmlaldavxq_p): Remove.
(vmlsldavq_p): Remove.
(vmlsldavxq_p): Remove.
(vmlaldavq_u16): Remove.
(vmlsldavxq_s16): Remove.
(vmlsldavq_s16): Remove.
(vmlaldavxq_s16): Remove.
(vmlaldavq_s16): Remove.
(vmlaldavq_u32): Remove.
(vmlsldavxq_s32): Remove.
(vmlsldavq_s32): Remove.
(vmlaldavxq_s32): Remove.
(vmlaldavq_s32): Remove.
(vmlaldavq_p_s16): Remove.
(vmlaldavxq_p_s16): Remove.
(vmlsldavq_p_s16): Remove.
(vmlsldavxq_p_s16): Remove.
(vmlaldavq_p_u16): Remove.
(vmlaldavq_p_s32): Remove.
(vmlaldavxq_p_s32): Remove.
(vmlsldavq_p_s32): Remove.
(vmlsldavxq_p_s32): Remove.
(vmlaldavq_p_u32): Remove.
(__arm_vmlaldavq_u16): Remove.
(__arm_vmlsldavxq_s16): Remove.
(__arm_vmlsldavq_s16): Remove.
(__arm_vmlaldavxq_s16): Remove.
(__arm_vmlaldavq_s16): Remove.
(__arm_vmlaldavq_u32): Remove.
(__arm_vmlsldavxq_s32): Remove.
(__arm_vmlsldavq_s32): Remove.
(__arm_vmlaldavxq_s32): Remove.
(__arm_vmlaldavq_s32): Remove.
(__arm_vmlaldavq_p_s16): Remove.
(__arm_vmlaldavxq_p_s16): Remove.
(__arm_vmlsldavq_p_s16): Remove.
(__arm_vmlsldavxq_p_s16): Remove.
(__arm_vmlaldavq_p_u16): Remove.
(__arm_vmlaldavq_p_s32): Remove.
(__arm_vmlaldavxq_p_s32): Remove.
(__arm_vmlsldavq_p_s32): Remove.
(__arm_vmlsldavxq_p_s32): Remove.
(__arm_vmlaldavq_p_u32): Remove.
(__arm_vmlaldavq): Remove.
(__arm_vmlsldavxq): Remove.
(__arm_vmlsldavq): Remove.
(__arm_vmlaldavxq): Remove.
(__arm_vmlaldavq_p): Remove.
(__arm_vmlaldavxq_p): Remove.
(__arm_vmlsldavq_p): Remove.
(__arm_vmlsldavxq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq
Christophe Lyon [Wed, 22 Feb 2023 16:36:11 +0000 (16:36 +0000)] 
arm: [MVE intrinsics] factorize vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq

Factorize vmlaldavq, vmlaldavxq, vmlsldavq, vmlsldavxq builtins so
that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New.
(mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx.
(supf): Add VMLALDAVXQ_S, VMLSLDAVQ_S, VMLSLDAVXQ_S,
VMLALDAVXQ_P_S, VMLSLDAVQ_P_S, VMLSLDAVXQ_P_S.
* config/arm/mve.md (mve_vmlaldavq_<supf><mode>)
(mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
(mve_vmlsldavxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlaldavq_p_<supf><mode>, mve_vmlaldavxq_p_s<mode>)
(mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] add binary_acc_int64 shape
Christophe Lyon [Wed, 22 Feb 2023 16:36:38 +0000 (16:36 +0000)] 
arm: [MVE intrinsics] add binary_acc_int64 shape

This patch adds the binary_acc_int64 shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int64): New.

13 months agoarm: [MVE intrinsics] rework vabavq
Christophe Lyon [Tue, 21 Feb 2023 23:05:21 +0000 (23:05 +0000)] 
arm: [MVE intrinsics] rework vabavq

Implement vabavq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vabavq): New.
* config/arm/arm-mve-builtins-base.def (vabavq): New.
* config/arm/arm-mve-builtins-base.h (vabavq): New.
* config/arm/arm_mve.h (vabavq): Remove.
(vabavq_p): Remove.
(vabavq_s8): Remove.
(vabavq_s16): Remove.
(vabavq_s32): Remove.
(vabavq_u8): Remove.
(vabavq_u16): Remove.
(vabavq_u32): Remove.
(vabavq_p_s8): Remove.
(vabavq_p_u8): Remove.
(vabavq_p_s16): Remove.
(vabavq_p_u16): Remove.
(vabavq_p_s32): Remove.
(vabavq_p_u32): Remove.
(__arm_vabavq_s8): Remove.
(__arm_vabavq_s16): Remove.
(__arm_vabavq_s32): Remove.
(__arm_vabavq_u8): Remove.
(__arm_vabavq_u16): Remove.
(__arm_vabavq_u32): Remove.
(__arm_vabavq_p_s8): Remove.
(__arm_vabavq_p_u8): Remove.
(__arm_vabavq_p_s16): Remove.
(__arm_vabavq_p_u16): Remove.
(__arm_vabavq_p_s32): Remove.
(__arm_vabavq_p_u32): Remove.
(__arm_vabavq): Remove.
(__arm_vabavq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vabavq
Christophe Lyon [Tue, 21 Feb 2023 23:05:14 +0000 (23:05 +0000)] 
arm: [MVE intrinsics] factorize vabavq

Factorize vabavq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vabav.
* config/arm/mve.md (mve_vabavq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this,.
(mve_vabavq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this,.

13 months agoarm: [MVE intrinsics] rework vmladavaq vmladavaxq vmlsdavaq vmlsdavaxq
Christophe Lyon [Tue, 21 Feb 2023 22:49:30 +0000 (22:49 +0000)] 
arm: [MVE intrinsics] rework vmladavaq vmladavaxq vmlsdavaq vmlsdavaxq

Implement vmladavaq, vmladavaxq, vmlsdavaq, vmlsdavaxq using the new
MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.h (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm_mve.h (vmladavaq): Remove.
(vmlsdavaxq): Remove.
(vmlsdavaq): Remove.
(vmladavaxq): Remove.
(vmladavaq_p): Remove.
(vmladavaxq_p): Remove.
(vmlsdavaq_p): Remove.
(vmlsdavaxq_p): Remove.
(vmladavaq_u8): Remove.
(vmlsdavaxq_s8): Remove.
(vmlsdavaq_s8): Remove.
(vmladavaxq_s8): Remove.
(vmladavaq_s8): Remove.
(vmladavaq_u16): Remove.
(vmlsdavaxq_s16): Remove.
(vmlsdavaq_s16): Remove.
(vmladavaxq_s16): Remove.
(vmladavaq_s16): Remove.
(vmladavaq_u32): Remove.
(vmlsdavaxq_s32): Remove.
(vmlsdavaq_s32): Remove.
(vmladavaxq_s32): Remove.
(vmladavaq_s32): Remove.
(vmladavaq_p_s8): Remove.
(vmladavaq_p_s32): Remove.
(vmladavaq_p_s16): Remove.
(vmladavaq_p_u8): Remove.
(vmladavaq_p_u32): Remove.
(vmladavaq_p_u16): Remove.
(vmladavaxq_p_s8): Remove.
(vmladavaxq_p_s32): Remove.
(vmladavaxq_p_s16): Remove.
(vmlsdavaq_p_s8): Remove.
(vmlsdavaq_p_s32): Remove.
(vmlsdavaq_p_s16): Remove.
(vmlsdavaxq_p_s8): Remove.
(vmlsdavaxq_p_s32): Remove.
(vmlsdavaxq_p_s16): Remove.
(__arm_vmladavaq_u8): Remove.
(__arm_vmlsdavaxq_s8): Remove.
(__arm_vmlsdavaq_s8): Remove.
(__arm_vmladavaxq_s8): Remove.
(__arm_vmladavaq_s8): Remove.
(__arm_vmladavaq_u16): Remove.
(__arm_vmlsdavaxq_s16): Remove.
(__arm_vmlsdavaq_s16): Remove.
(__arm_vmladavaxq_s16): Remove.
(__arm_vmladavaq_s16): Remove.
(__arm_vmladavaq_u32): Remove.
(__arm_vmlsdavaxq_s32): Remove.
(__arm_vmlsdavaq_s32): Remove.
(__arm_vmladavaxq_s32): Remove.
(__arm_vmladavaq_s32): Remove.
(__arm_vmladavaq_p_s8): Remove.
(__arm_vmladavaq_p_s32): Remove.
(__arm_vmladavaq_p_s16): Remove.
(__arm_vmladavaq_p_u8): Remove.
(__arm_vmladavaq_p_u32): Remove.
(__arm_vmladavaq_p_u16): Remove.
(__arm_vmladavaxq_p_s8): Remove.
(__arm_vmladavaxq_p_s32): Remove.
(__arm_vmladavaxq_p_s16): Remove.
(__arm_vmlsdavaq_p_s8): Remove.
(__arm_vmlsdavaq_p_s32): Remove.
(__arm_vmlsdavaq_p_s16): Remove.
(__arm_vmlsdavaxq_p_s8): Remove.
(__arm_vmlsdavaxq_p_s32): Remove.
(__arm_vmlsdavaxq_p_s16): Remove.
(__arm_vmladavaq): Remove.
(__arm_vmlsdavaxq): Remove.
(__arm_vmlsdavaq): Remove.
(__arm_vmladavaxq): Remove.
(__arm_vmladavaq_p): Remove.
(__arm_vmladavaxq_p): Remove.
(__arm_vmlsdavaq_p): Remove.
(__arm_vmlsdavaxq_p): Remove.

13 months agoarm: [MVE intrinsics] add binary_acca_int32 shape
Christophe Lyon [Tue, 21 Feb 2023 22:49:16 +0000 (22:49 +0000)] 
arm: [MVE intrinsics] add binary_acca_int32 shape

This patch adds the binary_acca_int32 shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int32): New.

13 months agoarm: [MVE intrinsics] rework vmladavq vmladavxq vmlsdavq vmlsdavxq
Christophe Lyon [Tue, 21 Feb 2023 22:31:42 +0000 (22:31 +0000)] 
arm: [MVE intrinsics] rework vmladavq vmladavxq vmlsdavq vmlsdavxq

Implement vmladavq, vmladavxq, vmlsdavq, vmlsdavxq using the new MVE
builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm-mve-builtins-base.def (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm-mve-builtins-base.h (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm_mve.h (vmladavq): Remove.
(vmlsdavxq): Remove.
(vmlsdavq): Remove.
(vmladavxq): Remove.
(vmladavq_p): Remove.
(vmlsdavxq_p): Remove.
(vmlsdavq_p): Remove.
(vmladavxq_p): Remove.
(vmladavq_u8): Remove.
(vmlsdavxq_s8): Remove.
(vmlsdavq_s8): Remove.
(vmladavxq_s8): Remove.
(vmladavq_s8): Remove.
(vmladavq_u16): Remove.
(vmlsdavxq_s16): Remove.
(vmlsdavq_s16): Remove.
(vmladavxq_s16): Remove.
(vmladavq_s16): Remove.
(vmladavq_u32): Remove.
(vmlsdavxq_s32): Remove.
(vmlsdavq_s32): Remove.
(vmladavxq_s32): Remove.
(vmladavq_s32): Remove.
(vmladavq_p_u8): Remove.
(vmlsdavxq_p_s8): Remove.
(vmlsdavq_p_s8): Remove.
(vmladavxq_p_s8): Remove.
(vmladavq_p_s8): Remove.
(vmladavq_p_u16): Remove.
(vmlsdavxq_p_s16): Remove.
(vmlsdavq_p_s16): Remove.
(vmladavxq_p_s16): Remove.
(vmladavq_p_s16): Remove.
(vmladavq_p_u32): Remove.
(vmlsdavxq_p_s32): Remove.
(vmlsdavq_p_s32): Remove.
(vmladavxq_p_s32): Remove.
(vmladavq_p_s32): Remove.
(__arm_vmladavq_u8): Remove.
(__arm_vmlsdavxq_s8): Remove.
(__arm_vmlsdavq_s8): Remove.
(__arm_vmladavxq_s8): Remove.
(__arm_vmladavq_s8): Remove.
(__arm_vmladavq_u16): Remove.
(__arm_vmlsdavxq_s16): Remove.
(__arm_vmlsdavq_s16): Remove.
(__arm_vmladavxq_s16): Remove.
(__arm_vmladavq_s16): Remove.
(__arm_vmladavq_u32): Remove.
(__arm_vmlsdavxq_s32): Remove.
(__arm_vmlsdavq_s32): Remove.
(__arm_vmladavxq_s32): Remove.
(__arm_vmladavq_s32): Remove.
(__arm_vmladavq_p_u8): Remove.
(__arm_vmlsdavxq_p_s8): Remove.
(__arm_vmlsdavq_p_s8): Remove.
(__arm_vmladavxq_p_s8): Remove.
(__arm_vmladavq_p_s8): Remove.
(__arm_vmladavq_p_u16): Remove.
(__arm_vmlsdavxq_p_s16): Remove.
(__arm_vmlsdavq_p_s16): Remove.
(__arm_vmladavxq_p_s16): Remove.
(__arm_vmladavq_p_s16): Remove.
(__arm_vmladavq_p_u32): Remove.
(__arm_vmlsdavxq_p_s32): Remove.
(__arm_vmlsdavq_p_s32): Remove.
(__arm_vmladavxq_p_s32): Remove.
(__arm_vmladavq_p_s32): Remove.
(__arm_vmladavq): Remove.
(__arm_vmlsdavxq): Remove.
(__arm_vmlsdavq): Remove.
(__arm_vmladavxq): Remove.
(__arm_vmladavq_p): Remove.
(__arm_vmlsdavxq_p): Remove.
(__arm_vmlsdavq_p): Remove.
(__arm_vmladavxq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vmladav vmladavx vmlsdav vmlsdavx vmladava vmladavax...
Christophe Lyon [Tue, 21 Feb 2023 22:31:22 +0000 (22:31 +0000)] 
arm: [MVE intrinsics] factorize vmladav vmladavx vmlsdav vmlsdavx vmladava vmladavax vmlsdava vmlsdavax

Factorize vmladav, vmladavx, vmlsdav, vmlsdavx, vmladava, vmladavax,
vmlsdava, vmlsdavax builtins so that they use the same parameterized
names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P)
(MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): New.
(mve_insn): Add vmladava, vmladavax, vmladav, vmladavx, vmlsdava,
vmlsdavax, vmlsdav, vmlsdavx.
(supf): Add VMLADAVAXQ_P_S, VMLADAVAXQ_S, VMLADAVXQ_P_S,
VMLADAVXQ_S, VMLSDAVAQ_P_S, VMLSDAVAQ_S, VMLSDAVAXQ_P_S,
VMLSDAVAXQ_S, VMLSDAVQ_P_S, VMLSDAVQ_S, VMLSDAVXQ_P_S,
VMLSDAVXQ_S.
* config/arm/mve.md (mve_vmladavq_<supf><mode>)
(mve_vmladavxq_s<mode>, mve_vmlsdavq_s<mode>)
(mve_vmlsdavxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlsdavaq_s<mode>, mve_vmladavaxq_s<mode>)
(mve_vmlsdavaxq_s<mode>, mve_vmladavaq_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmladavq_p_<supf><mode>, mve_vmladavxq_p_s<mode>)
(mve_vmlsdavq_p_s<mode>, mve_vmlsdavxq_p_s<mode>): Merge into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
(mve_vmladavaq_p_<supf><mode>, mve_vmladavaxq_p_s<mode>)
(mve_vmlsdavaq_p_s<mode>, mve_vmlsdavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] add binary_acc_int32 shape
Christophe Lyon [Tue, 21 Feb 2023 22:30:25 +0000 (22:30 +0000)] 
arm: [MVE intrinsics] add binary_acc_int32 shape

This patch adds the binary_acc_int32 shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int32): New.

13 months agoarm: [MVE intrinsics] rework vaddlvaq
Christophe Lyon [Tue, 21 Feb 2023 21:36:57 +0000 (21:36 +0000)] 
arm: [MVE intrinsics] rework vaddlvaq

Implement vaddlvaq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.def (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.h (vaddlvaq): New.
* config/arm/arm_mve.h (vaddlvaq): Remove.
(vaddlvaq_p): Remove.
(vaddlvaq_u32): Remove.
(vaddlvaq_s32): Remove.
(vaddlvaq_p_s32): Remove.
(vaddlvaq_p_u32): Remove.
(__arm_vaddlvaq_u32): Remove.
(__arm_vaddlvaq_s32): Remove.
(__arm_vaddlvaq_p_s32): Remove.
(__arm_vaddlvaq_p_u32): Remove.
(__arm_vaddlvaq): Remove.
(__arm_vaddlvaq_p): Remove.

13 months agoarm: [MVE intrinsics] add unary_widen_acc shape
Christophe Lyon [Tue, 21 Feb 2023 21:36:44 +0000 (21:36 +0000)] 
arm: [MVE intrinsics] add unary_widen_acc shape

This patch adds the unary_widen_acc shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_widen_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_widen_acc): New.

13 months agoarm: [MVE intrinsics] factorize vaddlvaq
Christophe Lyon [Tue, 21 Feb 2023 21:36:19 +0000 (21:36 +0000)] 
arm: [MVE intrinsics] factorize vaddlvaq

Factorize vaddlvaq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vaddlva.
* config/arm/mve.md (mve_vaddlvaq_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vaddlvaq_p_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.

13 months agoi386: Handle V4HI and V2SImode in ix86_widen_mult_cost [PR109807]
Uros Bizjak [Thu, 11 May 2023 18:54:24 +0000 (20:54 +0200)] 
i386: Handle V4HI and V2SImode in ix86_widen_mult_cost [PR109807]

Do not crash when asking ix86_widen_mult_cost for the cost of
a widening mul operation to V4HI or V2SImode.

gcc/ChangeLog:

PR target/109807
* config/i386/i386.cc (ix86_widen_mult_cost):
Handle V4HImode and V2SImode.

gcc/testsuite/ChangeLog:

PR target/109807
* gcc.target/i386/pr109807.c: New test.

13 months agoImprove simple_dce for phis that only used in itself
Andrew Pinski [Thu, 11 May 2023 14:59:06 +0000 (07:59 -0700)] 
Improve simple_dce for phis that only used in itself

While I was looking at differences before and after
r14-569-g21e2ef2dc25de3, I noticed that one phi node was
not being removed.
For an example, while compiling combine.cc, in expand_field_assignment,
we would remove `# pos_51 = PHI <pos_221(31), pos_51(30)>`
but we don't any more since pos_51 has more than zero users
but in this case it is only itself.
This patch improves simple_dce_from_worklist to detect that
case and now we able to remove this phi statement again.

OK? Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

* tree-ssa-dce.cc (simple_dce_from_worklist): For ssa names
defined by a phi node with more than one uses, allow for the
only uses are in that same defining statement.

13 months agosyscall: add prlimit
Ian Lance Taylor [Wed, 19 Apr 2023 22:05:54 +0000 (15:05 -0700)] 
syscall: add prlimit

As of https://go.dev/cl/476695 golang.org/x/sys/unix can call
syscall.prlimit, so we need such a function in libgo.

For golang/go#46279
Fixes golang/go#59712

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/486576

13 months agoc++: Add testcase for already fixed PR [PR103807]
Patrick Palka [Thu, 11 May 2023 14:38:02 +0000 (10:38 -0400)] 
c++: Add testcase for already fixed PR [PR103807]

We accept this testcase since r13-806-g221acd67ca50f8.

PR c++/103807

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/lambda-targ1.C: New test.

13 months agoRISC-V: Allow vector constants in riscv_const_insns.
Robin Dapp [Wed, 26 Apr 2023 18:32:36 +0000 (20:32 +0200)] 
RISC-V: Allow vector constants in riscv_const_insns.

This patch adds various vector constants to riscv_const_insns in order
for them to be properly recognized as immediate operands.  This then
allows to emit vmv.v.i instructions via autovectorization.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_const_insns): Add permissible
vector constants.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: New test.
* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: New test.
* gcc.target/riscv/rvv/autovec/vmv-imm-template.h: New test.
* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: New test.

13 months agoc++: converted lambda as template argument [PR83258, ...]
Patrick Palka [Thu, 11 May 2023 14:04:25 +0000 (10:04 -0400)] 
c++: converted lambda as template argument [PR83258, ...]

r8-1253-g3d2e25a240c711 removed the template argument linkage requirement
in convert_nontype_argument for C++17 (which r9-3836-g4be5c72cf3ea3e later
factored out into invalid_tparm_referent_p), but we need to also remove
the one in convert_nontype_argument_function for benefit of the first and
third testcase which we currently reject even in C++17/20 mode.

And in invalid_tparm_referent_p we're inadvertendly returning false for
the address of a lambda's static op() since it's DECL_ARTIFICIAL, which
currently causes us to reject the second (C++20) testcase.  But this
DECL_ARTIFICIAL check seems to be relevant only for VAR_DECL, and in fact
this code path was originally reachable only for VAR_DECL until recently
(r13-6970-gb5e38b1c166357).  So this patch restricts the check to VAR_DECL.

Co-authored-by: Jonathan Wakely <jwakely@redhat.com>
PR c++/83258
PR c++/80488
PR c++/97700

gcc/cp/ChangeLog:

* pt.cc (convert_nontype_argument_function): Remove linkage
requirement for C++17 and later.
(invalid_tparm_referent_p) <case ADDR_EXPR>: Restrict
DECL_ARTIFICIAL rejection test to VAR_DECL.

gcc/testsuite/ChangeLog:

* g++.dg/ext/visibility/anon8.C: Don't expect a "no linkage"
error for the template argument &B2:fn in C++17 mode.
* g++.dg/cpp0x/lambda/lambda-conv15.C: New test.
* g++.dg/cpp2a/nontype-class56.C: New test.
* g++.dg/template/function2.C: New test.

13 months ago[vxworks] [testsuite] [aarch64] use builtin in pred-not-gen-4.c
Alexandre Oliva [Thu, 11 May 2023 13:06:25 +0000 (10:06 -0300)] 
[vxworks] [testsuite] [aarch64] use builtin in pred-not-gen-4.c

On vxworks, isunordered is defined as a macro that ultimately calls a
_Fpcomp function, that GCC doesn't recognize as a builtin, so it
can't optimize accordingly.

Use __builtin_isunordered instead to get the desired code for the
test.

for  gcc/testsuite/ChangeLog

* gcc.target/aarch64/sve/pred-not-gen-4.c: Drop math.h
include, call builtin.

13 months agoMAINTAINERS: Fix alphabetic sorting.
Robin Dapp [Thu, 11 May 2023 12:27:48 +0000 (14:27 +0200)] 
MAINTAINERS: Fix alphabetic sorting.

ChangeLog:

* MAINTAINERS: Sort.

13 months agoRISC-V: Update RVV integer compare simplification comments
Pan Li [Mon, 8 May 2023 08:48:54 +0000 (16:48 +0800)] 
RISC-V: Update RVV integer compare simplification comments

The VMSET simplification RVV integer comparision has merged already.
This patch would like to update the comments for the cases that the
define_split will act on.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

* config/riscv/vector.md: Add comments for simplifying to vmset.

Signed-off-by: Pan Li <pan2.li@intel.com>
13 months agoRISC-V: Add autovectorization tests for binary integer operations.
Robin Dapp [Thu, 11 May 2023 08:32:21 +0000 (10:32 +0200)] 
RISC-V: Add autovectorization tests for binary integer operations.

This patchs adds scan as well as execution tests for vectorized
binary integer operations.  The tests are not comprehensive as
the vector type promotions (vec_unpack, extend etc.) are not implemented
yet.  Also, vmulh, vmulhu, and vmulhsu and others are still missing.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/shift-template.h: New test.
* gcc.target/riscv/rvv/autovec/shift-run.c: New test.
* gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/shift-scalar-template.h: New test.
* gcc.target/riscv/rvv/autovec/shift-scalar-run.c: New test.
* gcc.target/riscv/rvv/autovec/vadd-run-template.h: New test.
* gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vadd-template.h: New test.
* gcc.target/riscv/rvv/autovec/vand-run.c: New test.
* gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vand-template.h: New test.
* gcc.target/riscv/rvv/autovec/vdiv-run.c: New test.
* gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vdiv-template.h: New test.
* gcc.target/riscv/rvv/autovec/vmax-run.c: New test.
* gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmax-template.h: New test.
* gcc.target/riscv/rvv/autovec/vmin-run.c: New test.
* gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmin-template.h: New test.
* gcc.target/riscv/rvv/autovec/vmul-run.c: New test.
* gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vmul-template.h: New test.
* gcc.target/riscv/rvv/autovec/vor-run.c: New test.
* gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vor-template.h: New test.
* gcc.target/riscv/rvv/autovec/vrem-run.c: New test.
* gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vrem-template.h: New test.
* gcc.target/riscv/rvv/autovec/vsub-run.c: New test.
* gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vsub-template.h: New test.
* gcc.target/riscv/rvv/autovec/vxor-run.c: New test.
* gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/vxor-template.h: New test.

Co-authored-by: Michael Collison <collison@rivosinc.com>
13 months agoRISC-V: Split off shift patterns for autovectorization.
Robin Dapp [Wed, 10 May 2023 07:52:43 +0000 (09:52 +0200)] 
RISC-V: Split off shift patterns for autovectorization.

This patch splits off the shift patterns of the binop patterns.
This is necessary as the scalar shifts require a Pmode operand
as shift count.  To this end, a new iterator any_int_binop_no_shift
is introduced.  At a later point when the binops are split up
further in commutative and non-commutative patterns (which both
do not include the shift patterns) we might not need this anymore.

gcc/ChangeLog:

* config/riscv/autovec.md (<optab><mode>3): Add scalar shift
pattern.
(v<optab><mode>3): Add vector shift pattern.
* config/riscv/vector-iterators.md: New iterator.

13 months agoRISC-V: Clarify vlmax and length handling.
Robin Dapp [Wed, 10 May 2023 07:52:37 +0000 (09:52 +0200)] 
RISC-V: Clarify vlmax and length handling.

This patch tries to improve the wrappers that emit either vlmax or
non-vlmax operations.  Now, emit_len_op can be used to
emit a regular operation.  Depending on whether a length != NULL
is passed either no VLMAX flags are set or we emit a vsetvli and
set VLMAX flags.  The patch also adds some comments that describes
some of the rationale of the current handling of vlmax/nonvlmax
operations.

gcc/ChangeLog:

* config/riscv/autovec.md: Use renamed functions.
* config/riscv/riscv-protos.h (emit_vlmax_op): Rename.
(emit_vlmax_reg_op): To this.
(emit_nonvlmax_op): Rename.
(emit_len_op): To this.
(emit_nonvlmax_binop): Rename.
(emit_len_binop): To this.
* config/riscv/riscv-v.cc (emit_pred_op): Add default parameter.
(emit_pred_binop): Remove vlmax_p.
(emit_vlmax_op): Rename.
(emit_vlmax_reg_op): To this.
(emit_nonvlmax_op): Rename.
(emit_len_op): To this.
(emit_nonvlmax_binop): Rename.
(emit_len_binop): To this.
(sew64_scalar_helper): Use renamed functions.
(expand_tuple_move): Use renamed functions.
* config/riscv/riscv.cc (vector_zero_call_used_regs): Use
renamed functions.
* config/riscv/vector.md: Use renamed functions.

13 months agoRISC-V: Add vectorized binops and insn_expander helpers.
Robin Dapp [Mon, 24 Apr 2023 06:27:52 +0000 (08:27 +0200)] 
RISC-V: Add vectorized binops and insn_expander helpers.

This patch adds basic binary integer operations support.  It is based
on Michael Collison's work and makes use of the existing helpers in
riscv-c.cc.  It introduces emit_nonvlmax_binop which, in turn, uses
emit_pred_binop.  Setting the destination as well as the mask and the
length are factored out into separate functions.

gcc/ChangeLog:

* config/riscv/autovec.md (<optab><mode>3): Add integer binops.
* config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare.
* config/riscv/riscv-v.cc (emit_pred_op): New function.
(set_expander_dest_and_mask): New function.
(emit_pred_binop): New function.
(emit_nonvlmax_binop): New function.

Co-authored-by: Michael Collison <collison@rivosinc.com>
13 months agolibstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758]
Jonathan Wakely [Wed, 10 May 2023 11:20:58 +0000 (12:20 +0100)] 
libstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758]

The current implementation of this non-standard overload of std::abs
incorrectly returns a negative value for negative NaNs and negative
zero, because x < 0 is false in both cases.

Use fabsl(long double) or fabsf128(_Float128) if those do the right
thing.  Otherwise, use __builtin_signbit(x) instead of x < 0 to detect
negative inputs. This assumes that __builtin_signbit handles __float128
correctly, but that seems to be true for all of GCC, clang and icc.

libstdc++-v3/ChangeLog:

PR libstdc++/109758
* include/bits/std_abs.h (abs(__float128)): Handle negative NaN
and negative zero correctly.
* testsuite/26_numerics/headers/cmath/109758.cc: New test.

13 months agoVECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV
Pan Li [Thu, 11 May 2023 10:50:56 +0000 (18:50 +0800)] 
VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV

This patch is going to be commited after bootstrap && regression on X86
PASSED.

Thanks Richards.

gcc/ChangeLog:

* cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
* gimple-loop-interchange.cc
(tree_loop_interchange::map_inductions_to_loop): Ditto.
* tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto.
* tree-ssa-loop-ivopts.cc (create_new_iv): Ditto.
* tree-ssa-loop-manip.cc (create_iv): Ditto.
(tree_transform_and_unroll_loop): Ditto.
(canonicalize_loop_ivs): Ditto.
* tree-ssa-loop-manip.h (create_iv): Ditto.
* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto.
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
Ditto.
(vect_set_loop_condition_normal): Ditto.
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto.
* tree-vect-stmts.cc (vectorizable_store): Ditto.
(vectorizable_load): Ditto.

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
13 months agofortran: use grep instead of fgrep
Xi Ruoyao [Fri, 24 Jun 2022 12:23:13 +0000 (20:23 +0800)] 
fortran: use grep instead of fgrep

fgrep has been deprecated in favor of grep -F for a long time, and the
curren grep release (3.10) prints a warning of fgrep is used.  Stop
using fgrep so we won't see the warning.

We can't hard code grep -F here or it may break build on hosts w/o GNU
grep.  autoconf documentation contains a warning about this issue and
suggest to use AC_PROG_FGREP and $FGREP, but these are too overkill in
the specific case: there is no way "debian" could be interpreted as an
non-trivial regex, so we can use a plain grep here.

gcc/fortran/ChangeLog:

* Make-lang.in: Use grep instead of fgrep.

13 months agoarm: [MVE intrinsics] rework vmovlbq vmovltq
Christophe Lyon [Tue, 21 Feb 2023 15:46:17 +0000 (15:46 +0000)] 
arm: [MVE intrinsics] rework vmovlbq vmovltq

Implement vmovlbq, vmovltq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New.
* config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New.
* config/arm/arm-mve-builtins-base.h (vmovlbq, vmovltq): New.
* config/arm/arm_mve.h (vmovlbq): Remove.
(vmovltq): Remove.
(vmovlbq_m): Remove.
(vmovltq_m): Remove.
(vmovlbq_x): Remove.
(vmovltq_x): Remove.
(vmovlbq_s8): Remove.
(vmovlbq_s16): Remove.
(vmovltq_s8): Remove.
(vmovltq_s16): Remove.
(vmovltq_u8): Remove.
(vmovltq_u16): Remove.
(vmovlbq_u8): Remove.
(vmovlbq_u16): Remove.
(vmovlbq_m_s8): Remove.
(vmovltq_m_s8): Remove.
(vmovlbq_m_u8): Remove.
(vmovltq_m_u8): Remove.
(vmovlbq_m_s16): Remove.
(vmovltq_m_s16): Remove.
(vmovlbq_m_u16): Remove.
(vmovltq_m_u16): Remove.
(vmovlbq_x_s8): Remove.
(vmovlbq_x_s16): Remove.
(vmovlbq_x_u8): Remove.
(vmovlbq_x_u16): Remove.
(vmovltq_x_s8): Remove.
(vmovltq_x_s16): Remove.
(vmovltq_x_u8): Remove.
(vmovltq_x_u16): Remove.
(__arm_vmovlbq_s8): Remove.
(__arm_vmovlbq_s16): Remove.
(__arm_vmovltq_s8): Remove.
(__arm_vmovltq_s16): Remove.
(__arm_vmovltq_u8): Remove.
(__arm_vmovltq_u16): Remove.
(__arm_vmovlbq_u8): Remove.
(__arm_vmovlbq_u16): Remove.
(__arm_vmovlbq_m_s8): Remove.
(__arm_vmovltq_m_s8): Remove.
(__arm_vmovlbq_m_u8): Remove.
(__arm_vmovltq_m_u8): Remove.
(__arm_vmovlbq_m_s16): Remove.
(__arm_vmovltq_m_s16): Remove.
(__arm_vmovlbq_m_u16): Remove.
(__arm_vmovltq_m_u16): Remove.
(__arm_vmovlbq_x_s8): Remove.
(__arm_vmovlbq_x_s16): Remove.
(__arm_vmovlbq_x_u8): Remove.
(__arm_vmovlbq_x_u16): Remove.
(__arm_vmovltq_x_s8): Remove.
(__arm_vmovltq_x_s16): Remove.
(__arm_vmovltq_x_u8): Remove.
(__arm_vmovltq_x_u16): Remove.
(__arm_vmovlbq): Remove.
(__arm_vmovltq): Remove.
(__arm_vmovlbq_m): Remove.
(__arm_vmovltq_m): Remove.
(__arm_vmovlbq_x): Remove.
(__arm_vmovltq_x): Remove.

13 months agoarm: [MVE intrinsics] add unary_widen shape
Christophe Lyon [Tue, 21 Feb 2023 15:45:53 +0000 (15:45 +0000)] 
arm: [MVE intrinsics] add unary_widen shape

This patch adds the unary_widen shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_widen): New.
* config/arm/arm-mve-builtins-shapes.h (unary_widen): New.

13 months agoarm: [MVE intrinsics] factorize vmovlbq vmovltq
Christophe Lyon [Tue, 21 Feb 2023 15:45:27 +0000 (15:45 +0000)] 
arm: [MVE intrinsics] factorize vmovlbq vmovltq

Factorize vmovlbq, vmovltq builtins so that they use the same
parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt.
(VMOVLBQ, VMOVLTQ): Merge into ...
(VMOVLxQ): ... this.
(VMOVLTQ_M, VMOVLBQ_M): Merge into ...
(VMOVLxQ_M): ... this.
* config/arm/mve.md (mve_vmovltq_<supf><mode>)
(mve_vmovlbq_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmovlbq_m_<supf><mode>, mve_vmovltq_m_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] rework vaddlvq
Christophe Lyon [Tue, 21 Feb 2023 13:33:34 +0000 (13:33 +0000)] 
arm: [MVE intrinsics] rework vaddlvq

Implement vaddlvq using the new MVE builtins framework.

Since we kept v4si hardcoded in the builtin name, we need to
special-case it in unspec_mve_function_exact_insn_pred_p.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vaddlvq): New.
* config/arm/arm-mve-builtins-base.def (vaddlvq): New.
* config/arm/arm-mve-builtins-base.h (vaddlvq): New.
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Handle vaddlvq.
* config/arm/arm_mve.h (vaddlvq): Remove.
(vaddlvq_p): Remove.
(vaddlvq_s32): Remove.
(vaddlvq_u32): Remove.
(vaddlvq_p_s32): Remove.
(vaddlvq_p_u32): Remove.
(__arm_vaddlvq_s32): Remove.
(__arm_vaddlvq_u32): Remove.
(__arm_vaddlvq_p_s32): Remove.
(__arm_vaddlvq_p_u32): Remove.
(__arm_vaddlvq): Remove.
(__arm_vaddlvq_p): Remove.

13 months agoarm: [MVE intrinsics] factorize vaddlvq
Christophe Lyon [Tue, 21 Feb 2023 13:33:28 +0000 (13:33 +0000)] 
arm: [MVE intrinsics] factorize vaddlvq

Factorize vaddlvq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vaddlv.
* config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vaddlvq_p_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.

13 months agoarm: [MVE intrinsics] add unary_acc shape
Christophe Lyon [Tue, 21 Feb 2023 13:33:10 +0000 (13:33 +0000)] 
arm: [MVE intrinsics] add unary_acc shape

This patch adds the unary_acc shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_acc): New.

13 months agoarm: [MVE intrinsics] rework vaddvaq
Christophe Lyon [Tue, 21 Feb 2023 13:16:20 +0000 (13:16 +0000)] 
arm: [MVE intrinsics] rework vaddvaq

Implement vaddvaq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vaddvaq): New.
* config/arm/arm-mve-builtins-base.def (vaddvaq): New.
* config/arm/arm-mve-builtins-base.h (vaddvaq): New.
* config/arm/arm_mve.h (vaddvaq): Remove.
(vaddvaq_p): Remove.
(vaddvaq_u8): Remove.
(vaddvaq_s8): Remove.
(vaddvaq_u16): Remove.
(vaddvaq_s16): Remove.
(vaddvaq_u32): Remove.
(vaddvaq_s32): Remove.
(vaddvaq_p_u8): Remove.
(vaddvaq_p_s8): Remove.
(vaddvaq_p_u16): Remove.
(vaddvaq_p_s16): Remove.
(vaddvaq_p_u32): Remove.
(vaddvaq_p_s32): Remove.
(__arm_vaddvaq_u8): Remove.
(__arm_vaddvaq_s8): Remove.
(__arm_vaddvaq_u16): Remove.
(__arm_vaddvaq_s16): Remove.
(__arm_vaddvaq_u32): Remove.
(__arm_vaddvaq_s32): Remove.
(__arm_vaddvaq_p_u8): Remove.
(__arm_vaddvaq_p_s8): Remove.
(__arm_vaddvaq_p_u16): Remove.
(__arm_vaddvaq_p_s16): Remove.
(__arm_vaddvaq_p_u32): Remove.
(__arm_vaddvaq_p_s32): Remove.
(__arm_vaddvaq): Remove.
(__arm_vaddvaq_p): Remove.

13 months agoarm: [MVE intrinsics] add unary_int32_acc shape
Christophe Lyon [Tue, 21 Feb 2023 13:15:38 +0000 (13:15 +0000)] 
arm: [MVE intrinsics] add unary_int32_acc shape

This patch adds the unary_int32_acc shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New.

13 months agoarm: [MVE intrinsics] factorize vaddvaq
Christophe Lyon [Tue, 21 Feb 2023 13:15:18 +0000 (13:15 +0000)] 
arm: [MVE intrinsics] factorize vaddvaq

Factorize vaddvaq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vaddva.
* config/arm/mve.md (mve_vaddvaq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vaddvaq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] rework vaddvq
Christophe Lyon [Tue, 21 Feb 2023 11:44:36 +0000 (11:44 +0000)] 
arm: [MVE intrinsics] rework vaddvq

Implement vaddvq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vaddvq): New.
* config/arm/arm-mve-builtins-base.def (vaddvq): New.
* config/arm/arm-mve-builtins-base.h (vaddvq): New.
* config/arm/arm_mve.h (vaddvq): Remove.
(vaddvq_p): Remove.
(vaddvq_s8): Remove.
(vaddvq_s16): Remove.
(vaddvq_s32): Remove.
(vaddvq_u8): Remove.
(vaddvq_u16): Remove.
(vaddvq_u32): Remove.
(vaddvq_p_u8): Remove.
(vaddvq_p_s8): Remove.
(vaddvq_p_u16): Remove.
(vaddvq_p_s16): Remove.
(vaddvq_p_u32): Remove.
(vaddvq_p_s32): Remove.
(__arm_vaddvq_s8): Remove.
(__arm_vaddvq_s16): Remove.
(__arm_vaddvq_s32): Remove.
(__arm_vaddvq_u8): Remove.
(__arm_vaddvq_u16): Remove.
(__arm_vaddvq_u32): Remove.
(__arm_vaddvq_p_u8): Remove.
(__arm_vaddvq_p_s8): Remove.
(__arm_vaddvq_p_u16): Remove.
(__arm_vaddvq_p_s16): Remove.
(__arm_vaddvq_p_u32): Remove.
(__arm_vaddvq_p_s32): Remove.
(__arm_vaddvq): Remove.
(__arm_vaddvq_p): Remove.

13 months agoarm: [MVE intrinsics] add unary_int32 shape
Christophe Lyon [Tue, 21 Feb 2023 11:44:12 +0000 (11:44 +0000)] 
arm: [MVE intrinsics] add unary_int32 shape

This patch adds the unary_int32 shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_int32): New.
* config/arm/arm-mve-builtins-shapes.h (unary_int32): New.

13 months agoarm: [MVE intrinsics] factorize vaddvq
Christophe Lyon [Tue, 21 Feb 2023 11:42:41 +0000 (11:42 +0000)] 
arm: [MVE intrinsics] factorize vaddvq

Factorize vaddvq builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vaddv.
* config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vaddvq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
* config/arm/vec-common.md: Use gen_mve_q instead of
gen_mve_vaddvq.

13 months agoarm: [MVE intrinsics] rework vdupq
Christophe Lyon [Tue, 21 Feb 2023 10:55:45 +0000 (10:55 +0000)] 
arm: [MVE intrinsics] rework vdupq

Implement vdupq using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New.
(vdupq): New.
* config/arm/arm-mve-builtins-base.def (vdupq): New.
* config/arm/arm-mve-builtins-base.h: (vdupq): New.
* config/arm/arm_mve.h (vdupq_n): Remove.
(vdupq_m): Remove.
(vdupq_n_f16): Remove.
(vdupq_n_f32): Remove.
(vdupq_n_s8): Remove.
(vdupq_n_s16): Remove.
(vdupq_n_s32): Remove.
(vdupq_n_u8): Remove.
(vdupq_n_u16): Remove.
(vdupq_n_u32): Remove.
(vdupq_m_n_u8): Remove.
(vdupq_m_n_s8): Remove.
(vdupq_m_n_u16): Remove.
(vdupq_m_n_s16): Remove.
(vdupq_m_n_u32): Remove.
(vdupq_m_n_s32): Remove.
(vdupq_m_n_f16): Remove.
(vdupq_m_n_f32): Remove.
(vdupq_x_n_s8): Remove.
(vdupq_x_n_s16): Remove.
(vdupq_x_n_s32): Remove.
(vdupq_x_n_u8): Remove.
(vdupq_x_n_u16): Remove.
(vdupq_x_n_u32): Remove.
(vdupq_x_n_f16): Remove.
(vdupq_x_n_f32): Remove.
(__arm_vdupq_n_s8): Remove.
(__arm_vdupq_n_s16): Remove.
(__arm_vdupq_n_s32): Remove.
(__arm_vdupq_n_u8): Remove.
(__arm_vdupq_n_u16): Remove.
(__arm_vdupq_n_u32): Remove.
(__arm_vdupq_m_n_u8): Remove.
(__arm_vdupq_m_n_s8): Remove.
(__arm_vdupq_m_n_u16): Remove.
(__arm_vdupq_m_n_s16): Remove.
(__arm_vdupq_m_n_u32): Remove.
(__arm_vdupq_m_n_s32): Remove.
(__arm_vdupq_x_n_s8): Remove.
(__arm_vdupq_x_n_s16): Remove.
(__arm_vdupq_x_n_s32): Remove.
(__arm_vdupq_x_n_u8): Remove.
(__arm_vdupq_x_n_u16): Remove.
(__arm_vdupq_x_n_u32): Remove.
(__arm_vdupq_n_f16): Remove.
(__arm_vdupq_n_f32): Remove.
(__arm_vdupq_m_n_f16): Remove.
(__arm_vdupq_m_n_f32): Remove.
(__arm_vdupq_x_n_f16): Remove.
(__arm_vdupq_x_n_f32): Remove.
(__arm_vdupq_n): Remove.
(__arm_vdupq_m): Remove.

13 months agoarm: [MVE intrinsics] add unary_n shape
Christophe Lyon [Tue, 21 Feb 2023 10:55:29 +0000 (10:55 +0000)] 
arm: [MVE intrinsics] add unary_n shape

This patch adds the unary_n shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (unary_n): New.
* config/arm/arm-mve-builtins-shapes.h (unary_n): New.

13 months agoarm: [MVE intrinsics] factorize vdupq
Christophe Lyon [Tue, 21 Feb 2023 10:54:40 +0000 (10:54 +0000)] 
arm: [MVE intrinsics] factorize vdupq

Factorize vdup builtins so that they use parameterized names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY)
(MVE_FP_N_VDUPQ_ONLY): New.
(mve_insn): Add vdupq.
* config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vdupq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vdupq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vdupq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.

13 months agoarm: [MVE intrinsics] rework vrev16q vrev32q vrev64q
Christophe Lyon [Tue, 21 Feb 2023 09:21:23 +0000 (09:21 +0000)] 
arm: [MVE intrinsics] rework vrev16q vrev32q vrev64q

Implement vrev16q, vrev32q, vrev64q using the new MVE builtins
framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q):
New.
* config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm_mve.h (vrev16q): Remove.
(vrev32q): Remove.
(vrev64q): Remove.
(vrev64q_m): Remove.
(vrev16q_m): Remove.
(vrev32q_m): Remove.
(vrev16q_x): Remove.
(vrev32q_x): Remove.
(vrev64q_x): Remove.
(vrev64q_f16): Remove.
(vrev64q_f32): Remove.
(vrev32q_f16): Remove.
(vrev16q_s8): Remove.
(vrev32q_s8): Remove.
(vrev32q_s16): Remove.
(vrev64q_s8): Remove.
(vrev64q_s16): Remove.
(vrev64q_s32): Remove.
(vrev64q_u8): Remove.
(vrev64q_u16): Remove.
(vrev64q_u32): Remove.
(vrev32q_u8): Remove.
(vrev32q_u16): Remove.
(vrev16q_u8): Remove.
(vrev64q_m_u8): Remove.
(vrev64q_m_s8): Remove.
(vrev64q_m_u16): Remove.
(vrev64q_m_s16): Remove.
(vrev64q_m_u32): Remove.
(vrev64q_m_s32): Remove.
(vrev16q_m_s8): Remove.
(vrev32q_m_f16): Remove.
(vrev16q_m_u8): Remove.
(vrev32q_m_s8): Remove.
(vrev64q_m_f16): Remove.
(vrev32q_m_u8): Remove.
(vrev32q_m_s16): Remove.
(vrev64q_m_f32): Remove.
(vrev32q_m_u16): Remove.
(vrev16q_x_s8): Remove.
(vrev16q_x_u8): Remove.
(vrev32q_x_s8): Remove.
(vrev32q_x_s16): Remove.
(vrev32q_x_u8): Remove.
(vrev32q_x_u16): Remove.
(vrev64q_x_s8): Remove.
(vrev64q_x_s16): Remove.
(vrev64q_x_s32): Remove.
(vrev64q_x_u8): Remove.
(vrev64q_x_u16): Remove.
(vrev64q_x_u32): Remove.
(vrev32q_x_f16): Remove.
(vrev64q_x_f16): Remove.
(vrev64q_x_f32): Remove.
(__arm_vrev16q_s8): Remove.
(__arm_vrev32q_s8): Remove.
(__arm_vrev32q_s16): Remove.
(__arm_vrev64q_s8): Remove.
(__arm_vrev64q_s16): Remove.
(__arm_vrev64q_s32): Remove.
(__arm_vrev64q_u8): Remove.
(__arm_vrev64q_u16): Remove.
(__arm_vrev64q_u32): Remove.
(__arm_vrev32q_u8): Remove.
(__arm_vrev32q_u16): Remove.
(__arm_vrev16q_u8): Remove.
(__arm_vrev64q_m_u8): Remove.
(__arm_vrev64q_m_s8): Remove.
(__arm_vrev64q_m_u16): Remove.
(__arm_vrev64q_m_s16): Remove.
(__arm_vrev64q_m_u32): Remove.
(__arm_vrev64q_m_s32): Remove.
(__arm_vrev16q_m_s8): Remove.
(__arm_vrev16q_m_u8): Remove.
(__arm_vrev32q_m_s8): Remove.
(__arm_vrev32q_m_u8): Remove.
(__arm_vrev32q_m_s16): Remove.
(__arm_vrev32q_m_u16): Remove.
(__arm_vrev16q_x_s8): Remove.
(__arm_vrev16q_x_u8): Remove.
(__arm_vrev32q_x_s8): Remove.
(__arm_vrev32q_x_s16): Remove.
(__arm_vrev32q_x_u8): Remove.
(__arm_vrev32q_x_u16): Remove.
(__arm_vrev64q_x_s8): Remove.
(__arm_vrev64q_x_s16): Remove.
(__arm_vrev64q_x_s32): Remove.
(__arm_vrev64q_x_u8): Remove.
(__arm_vrev64q_x_u16): Remove.
(__arm_vrev64q_x_u32): Remove.
(__arm_vrev64q_f16): Remove.
(__arm_vrev64q_f32): Remove.
(__arm_vrev32q_f16): Remove.
(__arm_vrev32q_m_f16): Remove.
(__arm_vrev64q_m_f16): Remove.
(__arm_vrev64q_m_f32): Remove.
(__arm_vrev32q_x_f16): Remove.
(__arm_vrev64q_x_f16): Remove.
(__arm_vrev64q_x_f32): Remove.
(__arm_vrev16q): Remove.
(__arm_vrev32q): Remove.
(__arm_vrev64q): Remove.
(__arm_vrev64q_m): Remove.
(__arm_vrev16q_m): Remove.
(__arm_vrev32q_m): Remove.
(__arm_vrev16q_x): Remove.
(__arm_vrev32q_x): Remove.
(__arm_vrev64q_x): Remove.

13 months agoarm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q
Christophe Lyon [Tue, 21 Feb 2023 08:46:02 +0000 (08:46 +0000)] 
arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q

Factorize vrev16q vrev32q vrev64q so that they use generic builtin
names.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
(MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
(MVE_FP_M_VREV32Q_ONLY): New iterators.
(mve_insn): Add vrev16q, vrev32q, vrev64q.
* config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this
(mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
(mve_vrev64q_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vrev32q_<supf><mode>): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev16q_<supf>v16qi): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev64q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev32q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev16q_m_<supf>v16qi): Rename into
@mve_<mve_insn>q_m_<supf><mode>.

13 months agoarm: [MVE intrinsics] rework vcmp
Christophe Lyon [Mon, 20 Feb 2023 20:32:46 +0000 (20:32 +0000)] 
arm: [MVE intrinsics] rework vcmp

Implement vcmp using the new MVE builtins framework.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-functions.h (class
unspec_based_mve_function_exact_insn_vcmp): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vcmp.
* config/arm/arm_mve.h (vcmpneq): Remove.
(vcmphiq): Remove.
(vcmpeqq): Remove.
(vcmpcsq): Remove.
(vcmpltq): Remove.
(vcmpleq): Remove.
(vcmpgtq): Remove.
(vcmpgeq): Remove.
(vcmpneq_m): Remove.
(vcmphiq_m): Remove.
(vcmpeqq_m): Remove.
(vcmpcsq_m): Remove.
(vcmpcsq_m_n): Remove.
(vcmpltq_m): Remove.
(vcmpleq_m): Remove.
(vcmpgtq_m): Remove.
(vcmpgeq_m): Remove.
(vcmpneq_s8): Remove.
(vcmpneq_s16): Remove.
(vcmpneq_s32): Remove.
(vcmpneq_u8): Remove.
(vcmpneq_u16): Remove.
(vcmpneq_u32): Remove.
(vcmpneq_n_u8): Remove.
(vcmphiq_u8): Remove.
(vcmphiq_n_u8): Remove.
(vcmpeqq_u8): Remove.
(vcmpeqq_n_u8): Remove.
(vcmpcsq_u8): Remove.
(vcmpcsq_n_u8): Remove.
(vcmpneq_n_s8): Remove.
(vcmpltq_s8): Remove.
(vcmpltq_n_s8): Remove.
(vcmpleq_s8): Remove.
(vcmpleq_n_s8): Remove.
(vcmpgtq_s8): Remove.
(vcmpgtq_n_s8): Remove.
(vcmpgeq_s8): Remove.
(vcmpgeq_n_s8): Remove.
(vcmpeqq_s8): Remove.
(vcmpeqq_n_s8): Remove.
(vcmpneq_n_u16): Remove.
(vcmphiq_u16): Remove.
(vcmphiq_n_u16): Remove.
(vcmpeqq_u16): Remove.
(vcmpeqq_n_u16): Remove.
(vcmpcsq_u16): Remove.
(vcmpcsq_n_u16): Remove.
(vcmpneq_n_s16): Remove.
(vcmpltq_s16): Remove.
(vcmpltq_n_s16): Remove.
(vcmpleq_s16): Remove.
(vcmpleq_n_s16): Remove.
(vcmpgtq_s16): Remove.
(vcmpgtq_n_s16): Remove.
(vcmpgeq_s16): Remove.
(vcmpgeq_n_s16): Remove.
(vcmpeqq_s16): Remove.
(vcmpeqq_n_s16): Remove.
(vcmpneq_n_u32): Remove.
(vcmphiq_u32): Remove.
(vcmphiq_n_u32): Remove.
(vcmpeqq_u32): Remove.
(vcmpeqq_n_u32): Remove.
(vcmpcsq_u32): Remove.
(vcmpcsq_n_u32): Remove.
(vcmpneq_n_s32): Remove.
(vcmpltq_s32): Remove.
(vcmpltq_n_s32): Remove.
(vcmpleq_s32): Remove.
(vcmpleq_n_s32): Remove.
(vcmpgtq_s32): Remove.
(vcmpgtq_n_s32): Remove.
(vcmpgeq_s32): Remove.
(vcmpgeq_n_s32): Remove.
(vcmpeqq_s32): Remove.
(vcmpeqq_n_s32): Remove.
(vcmpneq_n_f16): Remove.
(vcmpneq_f16): Remove.
(vcmpltq_n_f16): Remove.
(vcmpltq_f16): Remove.
(vcmpleq_n_f16): Remove.
(vcmpleq_f16): Remove.
(vcmpgtq_n_f16): Remove.
(vcmpgtq_f16): Remove.
(vcmpgeq_n_f16): Remove.
(vcmpgeq_f16): Remove.
(vcmpeqq_n_f16): Remove.
(vcmpeqq_f16): Remove.
(vcmpneq_n_f32): Remove.
(vcmpneq_f32): Remove.
(vcmpltq_n_f32): Remove.
(vcmpltq_f32): Remove.
(vcmpleq_n_f32): Remove.
(vcmpleq_f32): Remove.
(vcmpgtq_n_f32): Remove.
(vcmpgtq_f32): Remove.
(vcmpgeq_n_f32): Remove.
(vcmpgeq_f32): Remove.
(vcmpeqq_n_f32): Remove.
(vcmpeqq_f32): Remove.
(vcmpeqq_m_f16): Remove.
(vcmpeqq_m_f32): Remove.
(vcmpneq_m_u8): Remove.
(vcmpneq_m_n_u8): Remove.
(vcmphiq_m_u8): Remove.
(vcmphiq_m_n_u8): Remove.
(vcmpeqq_m_u8): Remove.
(vcmpeqq_m_n_u8): Remove.
(vcmpcsq_m_u8): Remove.
(vcmpcsq_m_n_u8): Remove.
(vcmpneq_m_s8): Remove.
(vcmpneq_m_n_s8): Remove.
(vcmpltq_m_s8): Remove.
(vcmpltq_m_n_s8): Remove.
(vcmpleq_m_s8): Remove.
(vcmpleq_m_n_s8): Remove.
(vcmpgtq_m_s8): Remove.
(vcmpgtq_m_n_s8): Remove.
(vcmpgeq_m_s8): Remove.
(vcmpgeq_m_n_s8): Remove.
(vcmpeqq_m_s8): Remove.
(vcmpeqq_m_n_s8): Remove.
(vcmpneq_m_u16): Remove.
(vcmpneq_m_n_u16): Remove.
(vcmphiq_m_u16): Remove.
(vcmphiq_m_n_u16): Remove.
(vcmpeqq_m_u16): Remove.
(vcmpeqq_m_n_u16): Remove.
(vcmpcsq_m_u16): Remove.
(vcmpcsq_m_n_u16): Remove.
(vcmpneq_m_s16): Remove.
(vcmpneq_m_n_s16): Remove.
(vcmpltq_m_s16): Remove.
(vcmpltq_m_n_s16): Remove.
(vcmpleq_m_s16): Remove.
(vcmpleq_m_n_s16): Remove.
(vcmpgtq_m_s16): Remove.
(vcmpgtq_m_n_s16): Remove.
(vcmpgeq_m_s16): Remove.
(vcmpgeq_m_n_s16): Remove.
(vcmpeqq_m_s16): Remove.
(vcmpeqq_m_n_s16): Remove.
(vcmpneq_m_u32): Remove.
(vcmpneq_m_n_u32): Remove.
(vcmphiq_m_u32): Remove.
(vcmphiq_m_n_u32): Remove.
(vcmpeqq_m_u32): Remove.
(vcmpeqq_m_n_u32): Remove.
(vcmpcsq_m_u32): Remove.
(vcmpcsq_m_n_u32): Remove.
(vcmpneq_m_s32): Remove.
(vcmpneq_m_n_s32): Remove.
(vcmpltq_m_s32): Remove.
(vcmpltq_m_n_s32): Remove.
(vcmpleq_m_s32): Remove.
(vcmpleq_m_n_s32): Remove.
(vcmpgtq_m_s32): Remove.
(vcmpgtq_m_n_s32): Remove.
(vcmpgeq_m_s32): Remove.
(vcmpgeq_m_n_s32): Remove.
(vcmpeqq_m_s32): Remove.
(vcmpeqq_m_n_s32): Remove.
(vcmpeqq_m_n_f16): Remove.
(vcmpgeq_m_f16): Remove.
(vcmpgeq_m_n_f16): Remove.
(vcmpgtq_m_f16): Remove.
(vcmpgtq_m_n_f16): Remove.
(vcmpleq_m_f16): Remove.
(vcmpleq_m_n_f16): Remove.
(vcmpltq_m_f16): Remove.
(vcmpltq_m_n_f16): Remove.
(vcmpneq_m_f16): Remove.
(vcmpneq_m_n_f16): Remove.
(vcmpeqq_m_n_f32): Remove.
(vcmpgeq_m_f32): Remove.
(vcmpgeq_m_n_f32): Remove.
(vcmpgtq_m_f32): Remove.
(vcmpgtq_m_n_f32): Remove.
(vcmpleq_m_f32): Remove.
(vcmpleq_m_n_f32): Remove.
(vcmpltq_m_f32): Remove.
(vcmpltq_m_n_f32): Remove.
(vcmpneq_m_f32): Remove.
(vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq_s8): Remove.
(__arm_vcmpneq_s16): Remove.
(__arm_vcmpneq_s32): Remove.
(__arm_vcmpneq_u8): Remove.
(__arm_vcmpneq_u16): Remove.
(__arm_vcmpneq_u32): Remove.
(__arm_vcmpneq_n_u8): Remove.
(__arm_vcmphiq_u8): Remove.
(__arm_vcmphiq_n_u8): Remove.
(__arm_vcmpeqq_u8): Remove.
(__arm_vcmpeqq_n_u8): Remove.
(__arm_vcmpcsq_u8): Remove.
(__arm_vcmpcsq_n_u8): Remove.
(__arm_vcmpneq_n_s8): Remove.
(__arm_vcmpltq_s8): Remove.
(__arm_vcmpltq_n_s8): Remove.
(__arm_vcmpleq_s8): Remove.
(__arm_vcmpleq_n_s8): Remove.
(__arm_vcmpgtq_s8): Remove.
(__arm_vcmpgtq_n_s8): Remove.
(__arm_vcmpgeq_s8): Remove.
(__arm_vcmpgeq_n_s8): Remove.
(__arm_vcmpeqq_s8): Remove.
(__arm_vcmpeqq_n_s8): Remove.
(__arm_vcmpneq_n_u16): Remove.
(__arm_vcmphiq_u16): Remove.
(__arm_vcmphiq_n_u16): Remove.
(__arm_vcmpeqq_u16): Remove.
(__arm_vcmpeqq_n_u16): Remove.
(__arm_vcmpcsq_u16): Remove.
(__arm_vcmpcsq_n_u16): Remove.
(__arm_vcmpneq_n_s16): Remove.
(__arm_vcmpltq_s16): Remove.
(__arm_vcmpltq_n_s16): Remove.
(__arm_vcmpleq_s16): Remove.
(__arm_vcmpleq_n_s16): Remove.
(__arm_vcmpgtq_s16): Remove.
(__arm_vcmpgtq_n_s16): Remove.
(__arm_vcmpgeq_s16): Remove.
(__arm_vcmpgeq_n_s16): Remove.
(__arm_vcmpeqq_s16): Remove.
(__arm_vcmpeqq_n_s16): Remove.
(__arm_vcmpneq_n_u32): Remove.
(__arm_vcmphiq_u32): Remove.
(__arm_vcmphiq_n_u32): Remove.
(__arm_vcmpeqq_u32): Remove.
(__arm_vcmpeqq_n_u32): Remove.
(__arm_vcmpcsq_u32): Remove.
(__arm_vcmpcsq_n_u32): Remove.
(__arm_vcmpneq_n_s32): Remove.
(__arm_vcmpltq_s32): Remove.
(__arm_vcmpltq_n_s32): Remove.
(__arm_vcmpleq_s32): Remove.
(__arm_vcmpleq_n_s32): Remove.
(__arm_vcmpgtq_s32): Remove.
(__arm_vcmpgtq_n_s32): Remove.
(__arm_vcmpgeq_s32): Remove.
(__arm_vcmpgeq_n_s32): Remove.
(__arm_vcmpeqq_s32): Remove.
(__arm_vcmpeqq_n_s32): Remove.
(__arm_vcmpneq_m_u8): Remove.
(__arm_vcmpneq_m_n_u8): Remove.
(__arm_vcmphiq_m_u8): Remove.
(__arm_vcmphiq_m_n_u8): Remove.
(__arm_vcmpeqq_m_u8): Remove.
(__arm_vcmpeqq_m_n_u8): Remove.
(__arm_vcmpcsq_m_u8): Remove.
(__arm_vcmpcsq_m_n_u8): Remove.
(__arm_vcmpneq_m_s8): Remove.
(__arm_vcmpneq_m_n_s8): Remove.
(__arm_vcmpltq_m_s8): Remove.
(__arm_vcmpltq_m_n_s8): Remove.
(__arm_vcmpleq_m_s8): Remove.
(__arm_vcmpleq_m_n_s8): Remove.
(__arm_vcmpgtq_m_s8): Remove.
(__arm_vcmpgtq_m_n_s8): Remove.
(__arm_vcmpgeq_m_s8): Remove.
(__arm_vcmpgeq_m_n_s8): Remove.
(__arm_vcmpeqq_m_s8): Remove.
(__arm_vcmpeqq_m_n_s8): Remove.
(__arm_vcmpneq_m_u16): Remove.
(__arm_vcmpneq_m_n_u16): Remove.
(__arm_vcmphiq_m_u16): Remove.
(__arm_vcmphiq_m_n_u16): Remove.
(__arm_vcmpeqq_m_u16): Remove.
(__arm_vcmpeqq_m_n_u16): Remove.
(__arm_vcmpcsq_m_u16): Remove.
(__arm_vcmpcsq_m_n_u16): Remove.
(__arm_vcmpneq_m_s16): Remove.
(__arm_vcmpneq_m_n_s16): Remove.
(__arm_vcmpltq_m_s16): Remove.
(__arm_vcmpltq_m_n_s16): Remove.
(__arm_vcmpleq_m_s16): Remove.
(__arm_vcmpleq_m_n_s16): Remove.
(__arm_vcmpgtq_m_s16): Remove.
(__arm_vcmpgtq_m_n_s16): Remove.
(__arm_vcmpgeq_m_s16): Remove.
(__arm_vcmpgeq_m_n_s16): Remove.
(__arm_vcmpeqq_m_s16): Remove.
(__arm_vcmpeqq_m_n_s16): Remove.
(__arm_vcmpneq_m_u32): Remove.
(__arm_vcmpneq_m_n_u32): Remove.
(__arm_vcmphiq_m_u32): Remove.
(__arm_vcmphiq_m_n_u32): Remove.
(__arm_vcmpeqq_m_u32): Remove.
(__arm_vcmpeqq_m_n_u32): Remove.
(__arm_vcmpcsq_m_u32): Remove.
(__arm_vcmpcsq_m_n_u32): Remove.
(__arm_vcmpneq_m_s32): Remove.
(__arm_vcmpneq_m_n_s32): Remove.
(__arm_vcmpltq_m_s32): Remove.
(__arm_vcmpltq_m_n_s32): Remove.
(__arm_vcmpleq_m_s32): Remove.
(__arm_vcmpleq_m_n_s32): Remove.
(__arm_vcmpgtq_m_s32): Remove.
(__arm_vcmpgtq_m_n_s32): Remove.
(__arm_vcmpgeq_m_s32): Remove.
(__arm_vcmpgeq_m_n_s32): Remove.
(__arm_vcmpeqq_m_s32): Remove.
(__arm_vcmpeqq_m_n_s32): Remove.
(__arm_vcmpneq_n_f16): Remove.
(__arm_vcmpneq_f16): Remove.
(__arm_vcmpltq_n_f16): Remove.
(__arm_vcmpltq_f16): Remove.
(__arm_vcmpleq_n_f16): Remove.
(__arm_vcmpleq_f16): Remove.
(__arm_vcmpgtq_n_f16): Remove.
(__arm_vcmpgtq_f16): Remove.
(__arm_vcmpgeq_n_f16): Remove.
(__arm_vcmpgeq_f16): Remove.
(__arm_vcmpeqq_n_f16): Remove.
(__arm_vcmpeqq_f16): Remove.
(__arm_vcmpneq_n_f32): Remove.
(__arm_vcmpneq_f32): Remove.
(__arm_vcmpltq_n_f32): Remove.
(__arm_vcmpltq_f32): Remove.
(__arm_vcmpleq_n_f32): Remove.
(__arm_vcmpleq_f32): Remove.
(__arm_vcmpgtq_n_f32): Remove.
(__arm_vcmpgtq_f32): Remove.
(__arm_vcmpgeq_n_f32): Remove.
(__arm_vcmpgeq_f32): Remove.
(__arm_vcmpeqq_n_f32): Remove.
(__arm_vcmpeqq_f32): Remove.
(__arm_vcmpeqq_m_f16): Remove.
(__arm_vcmpeqq_m_f32): Remove.
(__arm_vcmpeqq_m_n_f16): Remove.
(__arm_vcmpgeq_m_f16): Remove.
(__arm_vcmpgeq_m_n_f16): Remove.
(__arm_vcmpgtq_m_f16): Remove.
(__arm_vcmpgtq_m_n_f16): Remove.
(__arm_vcmpleq_m_f16): Remove.
(__arm_vcmpleq_m_n_f16): Remove.
(__arm_vcmpltq_m_f16): Remove.
(__arm_vcmpltq_m_n_f16): Remove.
(__arm_vcmpneq_m_f16): Remove.
(__arm_vcmpneq_m_n_f16): Remove.
(__arm_vcmpeqq_m_n_f32): Remove.
(__arm_vcmpgeq_m_f32): Remove.
(__arm_vcmpgeq_m_n_f32): Remove.
(__arm_vcmpgtq_m_f32): Remove.
(__arm_vcmpgtq_m_n_f32): Remove.
(__arm_vcmpleq_m_f32): Remove.
(__arm_vcmpleq_m_n_f32): Remove.
(__arm_vcmpltq_m_f32): Remove.
(__arm_vcmpltq_m_n_f32): Remove.
(__arm_vcmpneq_m_f32): Remove.
(__arm_vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq): Remove.
(__arm_vcmphiq): Remove.
(__arm_vcmpeqq): Remove.
(__arm_vcmpcsq): Remove.
(__arm_vcmpltq): Remove.
(__arm_vcmpleq): Remove.
(__arm_vcmpgtq): Remove.
(__arm_vcmpgeq): Remove.
(__arm_vcmpneq_m): Remove.
(__arm_vcmphiq_m): Remove.
(__arm_vcmpeqq_m): Remove.
(__arm_vcmpcsq_m): Remove.
(__arm_vcmpltq_m): Remove.
(__arm_vcmpleq_m): Remove.
(__arm_vcmpgtq_m): Remove.
(__arm_vcmpgeq_m): Remove.

13 months agoarm: [MVE intrinsics] add cmp shape
Christophe Lyon [Mon, 20 Feb 2023 20:30:11 +0000 (20:30 +0000)] 
arm: [MVE intrinsics] add cmp shape

This patch adds the cmp shape description.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (cmp): New.
* config/arm/arm-mve-builtins-shapes.h (cmp): New.

13 months agoarm: [MVE intrinsics] factorize vcmp
Christophe Lyon [Mon, 20 Feb 2023 20:19:35 +0000 (20:19 +0000)] 
arm: [MVE intrinsics] factorize vcmp

Factorize vcmp so that they use the same pattern.

2022-10-25  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N)
(MVE_CMP_M_N_F, mve_cmp_op1): New.
(isu): Add VCMP*
(supf): Likewise.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ...
(@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this.
(mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>)
(mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>)
(mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this.
(mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>)
(mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>)
(mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>)
(mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into
...
(@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this.
(mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>)
(mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>)
(mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>)
(mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge
into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this.
(mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>)
(mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>)
(mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.

13 months agoImplement LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [PR109128]
Joseph Myers [Thu, 11 May 2023 08:07:00 +0000 (10:07 +0200)] 
Implement LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [PR109128]

This is one part of the fix for PR109128, along with a corresponding
binutils's linker change.  Without this patch, what happens in the
linker, when an unused object in a .a file has offload data, is that
elf_link_is_defined_archive_symbol calls bfd_link_plugin_object_p,
which ends up calling the plugin's claim_file_handler, which then
records the object as one with offload data. That is, the linker never
decides to use the object in the first place, but use of this _p
interface (called as part of trying to decide whether to use the
object) results in the plugin deciding to use its offload data (and a
consequent mismatch in the offload data present at runtime).

The new hook allows the linker plugin to distinguish calls to
claim_file_handler that know the object is being used by the linker
(from ldmain.c:add_archive_element), from calls that don't know it's
being used by the linker (from elf_link_is_defined_archive_symbol); in
the latter case, the plugin should avoid recording the object as one
with offload data.

PR middle-end/109128

include/
* plugin-api.h (ld_plugin_claim_file_handler_v2)
(ld_plugin_register_claim_file_v2)
(LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New.
(struct ld_plugin_tv): Add tv_register_claim_file_v2.

lto-plugin/
* lto-plugin.c (register_claim_file_v2): New.
(claim_file_handler_v2): New.
(claim_file_handler): Wrap claim_file_handler_v2.
(onload): Handle LDPT_REGISTER_CLAIM_FILE_HOOK_V2.

13 months agoTestsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture...
Thomas Schwinge [Wed, 10 May 2023 07:17:47 +0000 (09:17 +0200)] 
Testsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture-init'

Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1
"Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'"
made 'torture-init' non-idempotent re 'LTO_TORTURE_OPTIONS', in order to catch
certain classes of errors.  Now, most of all '*.exp' files have 'torture-init'
followed by 'set-torture-options' before 'gcc-dg-runtest' etc., and therefore
don't run into the latter's
"Some callers set torture options themselves; don't override those." code.
Some '*.exp' files however do 'torture-init' but not 'set-torture-options', and
therefore we can't any longer conditionalize the implicit 'torture-init' by
'![torture-options-exist]'.

gcc/testsuite/
* lib/torture-options.exp (torture-init-done): Add.
* lib/gcc-dg.exp (gcc-dg-runtest): Use it to conditionalize
implicit 'torture-init'.
* lib/gfortran-dg.exp (gfortran-dg-runtest): Likewise.
* lib/obj-c++-dg.exp (obj-c++-dg-runtest): Likewise.
* lib/objc-dg.exp (objc-dg-runtest): Likewise.

13 months agoTestsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS...
Thomas Schwinge [Tue, 9 May 2023 08:35:27 +0000 (10:35 +0200)] 
Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage

Recent commit d6654a4be3ba44c0d57be7c8a51d76d9721345e1
"Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS'"
made it a requirement that 'LTO_TORTURE_OPTIONS' usage be within
'torture-init'/'torture-finish', and missed a few cases that didn't have that.

gcc/testsuite/
* gcc.target/arm/acle/acle.exp: Add missing
'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS'
usage.
* gcc.target/arm/cmse/cmse.exp: Likewise.
* gcc.target/arm/pure-code/pure-code.exp: Likewise.

13 months agomatch.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y)
Roger Sayle [Thu, 11 May 2023 07:15:21 +0000 (08:15 +0100)] 
match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y)

This patch teaches match.pd to simplify popcount(X&Y)+popcount(X|Y) as
popcount(X)+popcount(Y), and the related simplifications that
popcount(X)+popcount(Y)-popcount(X&Y) is popcount(X|Y).  As surprising
as it might seem, this idiom is common in cheminformatics codes
(for Tanimoto coefficient calculations).

2023-05-11  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* match.pd <popcount optimizations>: Simplify popcount(X|Y) +
popcount(X&Y) as popcount(X)+popcount(Y).  Likewise, simplify
popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and
vice versa.

gcc/testsuite/ChangeLog
* gcc.dg/fold-popcount-8.c: New test case.
* gcc.dg/fold-popcount-9.c: Likewise.
* gcc.dg/fold-popcount-10.c: Likewise.

13 months agomatch.pd: Simplify popcount/parity of bswap/rotate.
Roger Sayle [Thu, 11 May 2023 07:10:04 +0000 (08:10 +0100)] 
match.pd: Simplify popcount/parity of bswap/rotate.

This is the latest iteration of my patch from August 2020
https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552391.html
incorperating feedback and suggestions from reviewers.

This patch to match.pd optimizes away bit permutation operations,
specifically bswap and rotate, in calls to popcount and parity.

2023-05-11  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* match.pd <popcount optimizations>: Simplify popcount(bswap(x))
as popcount(x).  Simplify popcount(rotate(x,y)) as popcount(x).
<parity optimizations>:  Simplify parity(bswap(x)) as parity(x).
Simplify parity(rotate(x,y)) as parity(x).

gcc/testsuite/ChangeLog
* gcc.dg/fold-parity-6.c: New test.
* gcc.dg/fold-parity-7.c: Likewise.
* gcc.dg/fold-popcount-6.c: Likewise.
* gcc.dg/fold-popcount-7.c: Likewise.

13 months agoRISC-V: Support const series vector for RVV auto-vectorization
Juzhe-Zhong [Wed, 10 May 2023 04:00:35 +0000 (12:00 +0800)] 
RISC-V: Support const series vector for RVV auto-vectorization

This patch is the prerequiste patch for more RVV auto-vectorization
support.

Since when we enable a very simple binary operations, we will end
up with such following ICE:

during RTL pass: expand
add_run-1.c: In function 'main':
add_run-1.c:28:1: internal compiler error: Segmentation fault
0x1618ea3 crash_signal
../../../riscv-gcc/gcc/toplev.cc:314
0xe76cd9 single_set(rtx_insn const*)
../../../riscv-gcc/gcc/rtl.h:3602
0x1080f8a emit_move_insn(rtx_def*, rtx_def*)
../../../riscv-gcc/gcc/expr.cc:4342
0x170c458 insert_value_copy_on_edge
../../../riscv-gcc/gcc/tree-outof-ssa.cc:352
0x170d58e eliminate_phi
../../../riscv-gcc/gcc/tree-outof-ssa.cc:785
0x170df17 expand_phi_nodes(ssaexpand*)
../../../riscv-gcc/gcc/tree-outof-ssa.cc:1024
0xef27e2 execute
../../../riscv-gcc/gcc/cfgexpand.cc:6818

This is because LoopVectorizer assume target is able to handle
series const vector when we enable binary operations.
Then it will be easily causing ICE like that.

gcc/ChangeLog:

* config/riscv/autovec.md (@vec_series<mode>): New pattern
* config/riscv/riscv-protos.h (expand_vec_series): New function.
* config/riscv/riscv-v.cc (emit_binop): Ditto.
(emit_index_op): Ditto.
(expand_vec_series): Ditto.
(expand_const_vector): Add series vector handling.
* config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/series-1.c: New test.
* gcc.target/riscv/rvv/autovec/series_run-1.c: New test.

13 months agoMAINTAINERS: Add myself to write after approval
Ju-Zhe Zhong [Thu, 11 May 2023 00:58:03 +0000 (08:58 +0800)] 
MAINTAINERS: Add myself to write after approval

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
ChangeLog:

* MAINTAINERS: Add myself.

13 months agoDaily bump.
GCC Administrator [Thu, 11 May 2023 00:16:33 +0000 (00:16 +0000)] 
Daily bump.

13 months agoc++: wrong std::is_convertible with cv-qual fn [PR109680]
Marek Polacek [Tue, 2 May 2023 21:36:00 +0000 (17:36 -0400)] 
c++: wrong std::is_convertible with cv-qual fn [PR109680]

This PR points out that std::is_convertible has given the wrong answer
in

  static_assert (!std::is_convertible_v <int () const, int (*) ()>, "");

since r13-2822 implemented __is_{,nothrow_}convertible.

std::is_convertible uses the imaginary

  To test() { return std::declval<From>(); }

to do its job.  Here, From is 'int () const'.  std::declval is defined as:

  template<class T>
  typename std::add_rvalue_reference<T>::type declval() noexcept;

std::add_rvalue_reference is defined as "If T is a function type that
has no cv- or ref- qualifier or an object type, provides a member typedef
type which is T&&, otherwise type is T."

In our case, T is cv-qualified, so the result is T, so we end up with

  int () const declval() noexcept;

which is invalid.  In other words, this is pretty much like:

  using T = int () const;
  T fn1(); // bad, fn returning a fn
  T& fn2(); // bad, cannot declare reference to qualified function type
  T* fn3(); // bad, cannot declare pointer to qualified function type

  using U = int ();
  U fn4(); // bad, fn returning a fn
  U& fn5(); // OK
  U* fn6(); // OK

I think is_convertible_helper needs to simulate std::declval better.
To that end, I'm introducing build_trait_object, to be used where
a declval is needed.

PR c++/109680

gcc/cp/ChangeLog:

* method.cc (build_trait_object): New.
(assignable_expr): Use it.
(ref_xes_from_temporary): Likewise.
(is_convertible_helper): Likewise.  Check FUNC_OR_METHOD_TYPE_P.

gcc/testsuite/ChangeLog:

* g++.dg/ext/is_convertible6.C: New test.

13 months agoUse [(const_int 0)] idiom consistently in i386.md
Roger Sayle [Wed, 10 May 2023 21:10:49 +0000 (22:10 +0100)] 
Use [(const_int 0)] idiom consistently in i386.md

This cleans up the use of [(clobber (const_int 0))] in the i386 backend.

2023-05-10  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
* config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred
[(const_int 0)] idiom, instead of [(clobber (const_int 0))].
(*concat<mode><dwi>3_2): Likewise.
(*concat<mode><dwi>3_3): Likewise.
(*concat<mode><dwi>3_4): Likewise.
(*concat<mode><dwi>3_5): Likewise.
(*concat<mode><dwi>3_6): Likewise.
(*concat<mode><dwi>3_7): Likewise.

13 months agoc++: adjust conversion diagnostics
Jason Merrill [Thu, 23 Mar 2023 14:41:29 +0000 (10:41 -0400)] 
c++: adjust conversion diagnostics

While looking at PR109247 I made this change to improve diagnostics.  I
don't think I'm going ahead with that patch, but this still seems like a
worthy cleanup.

gcc/cp/ChangeLog:

* call.cc (convert_like_internal): Share ck_ref_bind handling
between all bad conversions.

13 months agoi386: Add missing vector extend patterns [PR92658]
Uros Bizjak [Wed, 10 May 2023 20:40:53 +0000 (22:40 +0200)] 
i386: Add missing vector extend patterns [PR92658]

Add missing insn pattern for v2qi -> v2si vector extend and named
expanders to activate generation of vector extends to 8-byte and 4-byte
vectors.

gcc/ChangeLog:

PR target/92658
* config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern.
(<insn>v4qiv4hi2): New expander.
(<insn>v2hiv2si2): Ditto.
(<insn>v2qiv2si2): Ditto.
(<insn>v2qiv2hi2): Ditto.

gcc/testsuite/ChangeLog:

PR target/92658
* gcc.target/i386/pr92658-sse4-4b.c: New test.
* gcc.target/i386/pr92658-sse4-8b.c: New test.

13 months agoFortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTION
Bernhard Reutner-Fischer [Tue, 9 May 2023 15:35:20 +0000 (17:35 +0200)] 
Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTION

gcc/fortran/ChangeLog:

* dump-parse-tree.cc (gfc_debug_expr): Remove forward declaration.
(debug): Add DEBUG_FUNCTION.
(show_code_node): Remove erroneous whitespace.

13 months agoFortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]
Bernhard Reutner-Fischer [Tue, 9 May 2023 15:21:16 +0000 (17:21 +0200)] 
Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624]

gcc/fortran/ChangeLog:

PR fortran/109624
* dump-parse-tree.cc (debug): New function for gfc_namespace.
(gfc_debug_code): Delete forward declaration.
(show_attr): Make sure to print balanced braces.

13 months agoAdd another new testcase
Andrew Pinski [Wed, 10 May 2023 17:56:15 +0000 (17:56 +0000)] 
Add another new testcase

While working on improving min/max detection, this
code (which is reduced from worse_state in ipa-pure-const.cc)
was being miscompiled. Since there was no testcase in the
testsuite yet for this, this patch adds one.

Committed as obvious after testing the testcase via:
make check-gcc RUNTESTFLAGS="execute.exp=20230510-1.c"

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/20230510-1.c: New test.

13 months agolibstdc++: [_Hashtable] Implement several small methods implicitly inline
François Dumont [Wed, 3 May 2023 04:45:47 +0000 (06:45 +0200)] 
libstdc++: [_Hashtable] Implement several small methods implicitly inline

Make implementation of 3 simple _Hashtable methods implicitly inline.

Avoid usage of const_iterator abstraction within _Hashtable implementation.

Replace several usages of __node_type* with expected __node_ptr.

libstdc++-v3/ChangeLog:

* include/bits/hashtable_policy.h
(_NodeBuilder<>::_S_build): Use __node_ptr.
(_ReuseOrAllocNode<>): Use __node_ptr in place of __node_type*.
(_AllocNode<>): Likewise.
(_Equality<>::_M_equal): Remove const_iterator usages. Only preserved
to call std::is_permutation in the non-unique key implementation.
* include/bits/hashtable.h (_Hashtable<>::_M_update_begin()): Capture
_M_begin() once.
(_Hashtable<>::_M_bucket_begin(size_type)): Implement implicitly inline.
(_Hashtable<>::_M_insert_bucket_begin): Likewise.
(_Hashtable<>::_M_remove_bucket_begin): Likewise.
(_Hashtable<>::_M_compute_hash_code): Use __node_ptr rather than
const_iterator.
(_Hashtable<>::find): Likewise.
(_Hashtable<>::_M_emplace): Likewise.
(_Hashtable<>::_M_insert_unique): Likewise.

13 months agoMAINTAINERS: Add myself to write after approval
Pan Li [Wed, 10 May 2023 15:41:08 +0000 (23:41 +0800)] 
MAINTAINERS: Add myself to write after approval

Signed-off-by: Pan Li <pan2.li@intel.com>
ChangeLog:

* MAINTAINERS: Add myself.

13 months agoc++: be stricter about constinit [CWG2543]
Jason Merrill [Mon, 6 Feb 2023 23:08:17 +0000 (15:08 -0800)] 
c++: be stricter about constinit [CWG2543]

DR 2543 clarifies that constinit variables should follow the language, and
diagnose non-constant initializers (according to [expr.const]) even if they
can actually initialize the variables statically.

DR 2543

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_outermost_constant_expr): Preserve
TARGET_EXPR flags.
(potential_constant_expression_1): Check TARGET_EXPR_ELIDING_P.
* typeck2.cc (store_init_value): Diagnose constinit sooner.

gcc/testsuite/ChangeLog:

* g++.dg/DRs/dr2543.C: New test.

13 months agoc++: always check consteval address
Jason Merrill [Tue, 9 May 2023 22:48:11 +0000 (18:48 -0400)] 
c++: always check consteval address

The restriction on the "permitted result of a constant expression" to not
refer to an immediate function applies regardless of context.  The previous
code tried to only check in cases where we wouldn't get the check in
cp_fold_r, but with the next patch I would need to add another case and it
shouldn't be a problem to always check.

We also shouldn't talk about immediate evaluation when we aren't dealing
with one.

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_outermost_constant_expr): Always check
for address of immediate fn.
(maybe_constant_init_1): Evaluate PTRMEM_CST.

gcc/testsuite/ChangeLog:

* g++.dg/DRs/dr2478.C: Handle -fimplicit-constexpr.
* g++.dg/cpp23/consteval-if12.C: Adjust diagnostics.
* g++.dg/cpp2a/consteval20.C: Likewise.
* g++.dg/cpp2a/consteval24.C: Likewise.
* g++.dg/cpp2a/srcloc20.C: Likewise.

13 months agoAvoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI
Richard Biener [Wed, 10 May 2023 13:36:12 +0000 (15:36 +0200)] 
Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI

The following forces the g++.dg/torture/pr106922.C testcase to use
the C++11 libstdc++ ABI and checks whether that worked.

gcc/testsuite/
* g++.dg/torture/pr106922.C: Force _GLIBCXX_USE_CXX11_ABI to 1.

13 months agoFix a couple constraints on the H8 in preparation for LRA conversion
Jeff Law [Wed, 10 May 2023 11:25:12 +0000 (05:25 -0600)] 
Fix a couple constraints on the H8 in preparation for LRA conversion

So this is the 2nd patch on the way to LRA for the H8.

LRA is more sensitive to getting define_constraint vs define_memory_constraint
vs define_special_memory_constraint correct.  than reload.

The H8 port has the "Q" constraint, which is used to indicate memory addresses
that can be used under certain circumstances in various ALU operations.  So it
should be a memory constraint.  Ideally it'd would be a simple memory
constraint, but it's used in contexts where MEMs are valid only for certain
parts in the H8 family.  So it really needs to be a special_memory_constraint.

The "Zz" constraint accepts memory, but the forms are limited and can not be
reloaded into a register.   It seems to be working, but I wouldn't be totally
surprised if this got stressed in the right way if it broke.

Anyway, this patch fixes "Q" and "Zz" to be special memory constraints.

Regression tested with gdbsim and pushed to the trunk.

gcc
* config/h8300/constraints.md (Q): Make this a special memory
constraint.
(Zz): Similarly.

13 months agoipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches
Jakub Jelinek [Wed, 10 May 2023 11:20:39 +0000 (13:20 +0200)] 
ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches

The PR contains a testcase where the Fortran FE creates FUNCTION_TYPE
which doesn't really match the passed in arguments (FUNCTION_TYPE has
5 arguments, call has 6).  Now, I think that is a Fortran FE bug that
should be fixed there, but I think with function pointers one can
create something similar (of course invalid) in C/C++ too,so IMHO IPA
should be also more careful.
The ipa_get_callee_param_type function can return NULL if something goes
wrong and it does e.g. if asked for 7th argument type on a function
with just 5 arguments and similar.  But, if a function isn't varargs,
when asked for 6th argument type on a function with just 5 arguments
it actually returns void_type_node because the argument list is in that
case terminated with void_list_node.

The following patch makes sure we don't treat void_list_node as something
holding another argument.

2023-05-10  Jakub Jelinek  <jakub@redhat.com>

PR fortran/109788
* ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t)
if t is void_list_node.

13 months agoaarch64: Simplify sqmovun expander
Kyrylo Tkachov [Wed, 10 May 2023 11:04:47 +0000 (12:04 +0100)] 
aarch64: Simplify sqmovun expander

This patch is a no-op as it removes the explicit vec-concat-zero patterns in favour of vczle/vczbe.
This allows us to delete the explicit expander too. Tests are added to ensure the optimisation required
still triggers.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete.
(aarch64_sqmovun<mode>_insn_be): Delete.
(aarch64_sqmovun<mode><vczle><vczbe>): New define_insn.
(aarch64_sqmovun<mode>): Delete expander.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/pr99195_4.c: Add tests for sqmovun.

13 months ago[PATCH] aarch64: PR target/99195 annotate simple permutation patterns for vec-concat...
Kyrylo Tkachov [Wed, 10 May 2023 11:00:17 +0000 (12:00 +0100)] 
[PATCH] aarch64: PR target/99195 annotate simple permutation patterns for vec-concat-zero

Another straightforward patch annotating patterns for the zip1, zip2, uzp1, uzp2, rev* instructions, plus tests.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>):
Rename to...
(aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This.
(aarch64_rev<REVERSE:rev_op><mode>): Rename to...
(aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add tests for zip and rev
intrinsics.

13 months agoaarch64: PR target/99195 annotate simple saturating add/sub patterns for vec-concat...
Kyrylo Tkachov [Wed, 10 May 2023 10:50:01 +0000 (11:50 +0100)] 
aarch64: PR target/99195 annotate simple saturating add/sub patterns for vec-concat-zero

Moving onto the saturating instructions, this one goes through the simple add/sub ones.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>):
Rename to...
(aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This.
(aarch64_<sur>qadd<mode>): Rename to...
(aarch64_<sur>qadd<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_1.c: Add testing for qadd, qsub.
* gcc.target/aarch64/simd/pr99195_6.c: New test.

13 months agoaarch64: Simplify QSHRN expanders and patterns
Kyrylo Tkachov [Wed, 10 May 2023 09:44:30 +0000 (10:44 +0100)] 
aarch64: Simplify QSHRN expanders and patterns

This patch deletes the explicit BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN patterns for the QSHRN instructions in favour
of annotating a single one with <vczle><vczbe>. This allows simplification of the expander too.
Tests are added to ensure that we still optimise away the concat-with-zero use case.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/pr99195_5.c: New test.

13 months agoaarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zero
Kyrylo Tkachov [Wed, 10 May 2023 09:40:06 +0000 (10:40 +0100)] 
aarch64: PR target/99195 annotate simple narrowing patterns for vec-concat-zero

This patch cleans up some almost-duplicate patterns for the XTN, SQXTN, UQXTN instructions.
Using the <vczle><vczbe> attributes we can remove the BYTES_BIG_ENDIAN and !BYTES_BIG_ENDIAN cases,
as well as the intrinsic expanders that select between the two.
Tests are also added. Thankfully the diffstat comes out negative \O/.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete.
(aarch64_xtn<mode>_insn_be): Likewise.
(trunc<mode><Vnarrowq>2): Rename to...
(trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
(aarch64_xtn<mode>): Move under the above.  Just emit the truncate RTL.
(aarch64_<su>qmovn<mode>): Likewise.
(aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
(aarch64_<su>qmovn<mode>_insn_le): Delete.
(aarch64_<su>qmovn<mode>_insn_be): Likewise.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_4.c: Add tests for vmovn, vqmovn.

13 months agoc++: Reject attributes without arguments used as pack expansion [PR109756]
Jakub Jelinek [Wed, 10 May 2023 09:37:04 +0000 (11:37 +0200)] 
c++: Reject attributes without arguments used as pack expansion [PR109756]

The following testcase shows we silently accept (and ignore) attributes without
arguments used as pack expansions.  This is because we call
make_pack_expansion and that starts with
  if (!arg || arg == error_mark_node)
    return arg;
Now, an attribute without arguments like [[noreturn...]] is IMHO always
invalid, in this case for 2 reasons; one is that as it has no arguments,
no pack can be present and second is that the standard says that
attributes need to specially permit uses of parameter pack and doesn't
explicitly permit it for any of the standard attributes (except for alignas?
which has different syntax).
If an attribute has some arguments but doesn't contain packs in those
arguments, make_pack_expansion will already diagnose it.

The patch also changes cp_parser_std_attribute, such that for attributes unknown
to the compiler (or perhaps registered just for -Wno-attributes=) we differentiate
between the attribute having no arguments (in that case we want to diagnose them
when followed by ellipsis even if they are unknown, as they can't contain a pack
in that case) and the case where they do have arguments but we've just skipped over
those arguments because we don't know how to parse them (except that they are
a balanced token sequence) - in that case we really don't know if they contain
packs or not.

2023-05-10  Jakub Jelinek  <jakub@redhat.com>

PR c++/109756
* parser.cc (cp_parser_std_attribute): For unknown attributes with
arguments set TREE_VALUE (attribute) to error_mark_node after skipping
the balanced tokens.
(cp_parser_std_attribute_list): If ... is used after attribute without
arguments, diagnose it and return error_mark_node.  If
TREE_VALUE (attribute) is error_mark_node, don't call
make_pack_expansion nor return early error_mark_node.

* g++.dg/cpp0x/gen-attrs-78.C: New test.

13 months agoRISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P...
Li Xu [Wed, 10 May 2023 04:02:13 +0000 (04:02 +0000)] 
RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0.

This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.

Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
    int16_t maxVal = __riscv_vmv_x_s_i16m1_i16 (__riscv_vle16_v_i16m1 (base, vl));
    return maxVal;
}

Before this patch:
bug.c:15:1: internal compiler error: Segmentation fault
   15 | }
      | ^
0x145d723 crash_signal
../.././riscv-gcc/gcc/toplev.cc:314
0x22929dd const_csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:44
0x2292a21 csr_operand(rtx_def*, machine_mode)
../.././riscv-gcc/gcc/config/riscv/predicates.md:46
0x23dfbb0 recog_356
../.././riscv-gcc/gcc/config/riscv/iterators.md:72
0x23efecd recog(rtx_def*, rtx_insn*, int*)
../.././riscv-gcc/gcc/config/riscv/iterators.md:89
0xdddc15 recog_memoized(rtx_insn*)
../.././riscv-gcc/gcc/recog.h:273

After this patch:
vsetivli zero,0,e16,m1,ta,ma
vmv.x.s a5,v1

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/scalar_move-10.c: New test.
* gcc.target/riscv/rvv/base/scalar_move-11.c: New test.

13 months agoRISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
Juzhe-Zhong [Tue, 9 May 2023 12:05:50 +0000 (20:05 +0800)] 
RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT

This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.

They let movmisalign<mode> to handle scalable vector of SVE.
For RVV, we should follow the same implementation of ARM SVE.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
incorrect codes.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.

13 months agoRISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]
Juzhe-Zhong [Tue, 9 May 2023 02:19:34 +0000 (10:19 +0800)] 
RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773]

This patch is fix dead loop in vsetvl intrinsic avl checking.

vsetvli->get_def () has vsetvli->get_def () has vsetvli.....
Then it will keep looping in the vsetvli avl checking which is a dead loop.

PR target/109773

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function.
(source_equal_p): Fix dead loop in vsetvl avl checking.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109773-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109773-2.c: New test.

13 months agoNew testcase
Andrew Pinski [Wed, 10 May 2023 05:02:48 +0000 (05:02 +0000)] 
New testcase

While I was writting a match.pd patch, I can across GCC was being miscompiled
but no testcase was failing. So this adds that testcase.

Committed after testing on x86_64 with
make check-gcc RUNTESTFLAGS="execute.exp=20230509-1.c"

gcc/testsuite/ChangeLog:

* gcc.c-torture/execute/20230509-1.c: New test.

13 months agoCRIS: Fix ccmode typo in cris_postdbr_cmpelim
Hans-Peter Nilsson [Fri, 28 Apr 2023 22:12:39 +0000 (00:12 +0200)] 
CRIS: Fix ccmode typo in cris_postdbr_cmpelim

Typo spotted while doing CCmode improvements, as a missed
optimization.  It's almost visible from the patch context;
there's not much done in terms of "mode-adjustment" when
replacing (reg:CC CRIS_CC0_REGNUM) with a copy!
This bug affects functions in the newlib printf-formatting
functions (nothing else in libgcc or newlib libc), with the
performance impact on coremark scores being less than 1e-6
(3/5078992 cycles, 6/48543 bytes).

* config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode
of modeadjusted_dccr.

13 months agoDaily bump.
GCC Administrator [Wed, 10 May 2023 00:17:49 +0000 (00:17 +0000)] 
Daily bump.

13 months agoUpdate cpplib ru.po
Joseph Myers [Tue, 9 May 2023 20:47:59 +0000 (20:47 +0000)] 
Update cpplib ru.po

* ru.po: Update.

13 months agoUpdate gcc hr.po
Joseph Myers [Tue, 9 May 2023 20:23:31 +0000 (20:23 +0000)] 
Update gcc hr.po

* hr.po: Update.

13 months agolibstdc++: Fix <chrono> pretty printers and add tests
Jonathan Wakely [Tue, 9 May 2023 17:18:01 +0000 (18:18 +0100)] 
libstdc++: Fix <chrono> pretty printers and add tests

This fixes a couple of errors in the printers for chrono types, and adds
tests to ensure they keep working.

libstdc++-v3/ChangeLog:

* python/libstdcxx/v6/printers.py (StdChronoDurationPrinter):
Print floating-point durations correctly.
(StdChronoTimePointPrinter): Support printing only the value,
not the type name. Uncomment handling for known clocks.
(StdChronoZonedTimePrinter): Remove type names from output.
(StdChronoCalendarPrinter): Fix hh_mm_ss member access.
(StdChronoTimeZonePrinter): Add equals sign to output.
* testsuite/libstdc++-prettyprinters/chrono.cc: New test.

13 months agoc++: error-recovery ICE with unstable satisfaction [PR109752]
Patrick Palka [Tue, 9 May 2023 19:07:00 +0000 (15:07 -0400)] 
c++: error-recovery ICE with unstable satisfaction [PR109752]

After diagnosing and recovering from unstable satisfaction, it's
possible to evaluate an atom for the first time noisily rather than
quietly.  The satisfaction cache tries to handle this situation
gracefully, but apparently not gracefully enough: we inserted an empty
slot into the cache, and left it empty, which later makes
hash_table::check_complete_insertion unhappy.  This patch fixes this by
removing the empty slot in this case.

PR c++/109752

gcc/cp/ChangeLog:

* constraint.cc (satisfaction_cache::satisfaction_cache): In the
unexpected case of evaluating an atom for the first time noisily,
remove the cache slot that we inserted.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-pr109752.C: New test.

13 months agoc++: noexcept-spec from nested class confusion [PR109761]
Patrick Palka [Tue, 9 May 2023 19:06:34 +0000 (15:06 -0400)] 
c++: noexcept-spec from nested class confusion [PR109761]

When late processing a noexcept-spec from a nested class after completion
of the outer class (since it's a complete-class context), we pass the wrong
class context to noexcept_override_late_checks -- the outer class type
instead of the nested class type -- which leads to bogus errors in the
below test.

This patch fixes this by making noexcept_override_late_checks obtain the
class context directly via DECL_CONTEXT instead of via an additional
parameter.

PR c++/109761

gcc/cp/ChangeLog:

* parser.cc (cp_parser_class_specifier): Don't pass a class
context to noexcept_override_late_checks.
(noexcept_override_late_checks): Remove 'type' parameter
and use DECL_CONTEXT of 'fndecl' instead.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/noexcept78.C: New test.

13 months agoarm: [MVE intrinsics] rework vmaxaq vminaq
Christophe Lyon [Mon, 13 Feb 2023 21:49:21 +0000 (21:49 +0000)] 
arm: [MVE intrinsics] rework vmaxaq vminaq

Implement vmaxaq and vminaq using the new MVE builtins framework.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxaq and
vminaq.
* config/arm/arm_mve.h (vminaq): Remove.
(vmaxaq): Remove.
(vminaq_m): Remove.
(vmaxaq_m): Remove.
(vminaq_s8): Remove.
(vmaxaq_s8): Remove.
(vminaq_s16): Remove.
(vmaxaq_s16): Remove.
(vminaq_s32): Remove.
(vmaxaq_s32): Remove.
(vminaq_m_s8): Remove.
(vmaxaq_m_s8): Remove.
(vminaq_m_s16): Remove.
(vmaxaq_m_s16): Remove.
(vminaq_m_s32): Remove.
(vmaxaq_m_s32): Remove.
(__arm_vminaq_s8): Remove.
(__arm_vmaxaq_s8): Remove.
(__arm_vminaq_s16): Remove.
(__arm_vmaxaq_s16): Remove.
(__arm_vminaq_s32): Remove.
(__arm_vmaxaq_s32): Remove.
(__arm_vminaq_m_s8): Remove.
(__arm_vmaxaq_m_s8): Remove.
(__arm_vminaq_m_s16): Remove.
(__arm_vmaxaq_m_s16): Remove.
(__arm_vminaq_m_s32): Remove.
(__arm_vmaxaq_m_s32): Remove.
(__arm_vminaq): Remove.
(__arm_vmaxaq): Remove.
(__arm_vminaq_m): Remove.
(__arm_vmaxaq_m): Remove.

13 months agoarm: [MVE intrinsics] factorize vmaxaq vminaq
Christophe Lyon [Mon, 13 Feb 2023 21:49:02 +0000 (21:49 +0000)] 
arm: [MVE intrinsics] factorize vmaxaq vminaq

Factorize vmaxaq vminaq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
New.
(mve_insn): Add vmaxa, vmina.
(supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
* config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.

13 months agoarm: [MVE intrinsics] add binary_maxamina shape
Christophe Lyon [Mon, 13 Feb 2023 21:46:30 +0000 (21:46 +0000)] 
arm: [MVE intrinsics] add binary_maxamina shape

This patch adds the binary_maxamina shape description.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New.
* config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.

13 months agoarm: [MVE intrinsics] rework vmaxnmaq vminnmaq
Christophe Lyon [Mon, 13 Feb 2023 21:32:11 +0000 (21:32 +0000)] 
arm: [MVE intrinsics] rework vmaxnmaq vminnmaq

Implement vmaxnmaq and vminnmaq using the new MVE builtins framework.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxnmaq and
vminnmaq.
* config/arm/arm_mve.h (vminnmaq): Remove.
(vmaxnmaq): Remove.
(vmaxnmaq_m): Remove.
(vminnmaq_m): Remove.
(vminnmaq_f16): Remove.
(vmaxnmaq_f16): Remove.
(vminnmaq_f32): Remove.
(vmaxnmaq_f32): Remove.
(vmaxnmaq_m_f16): Remove.
(vminnmaq_m_f16): Remove.
(vmaxnmaq_m_f32): Remove.
(vminnmaq_m_f32): Remove.
(__arm_vminnmaq_f16): Remove.
(__arm_vmaxnmaq_f16): Remove.
(__arm_vminnmaq_f32): Remove.
(__arm_vmaxnmaq_f32): Remove.
(__arm_vmaxnmaq_m_f16): Remove.
(__arm_vminnmaq_m_f16): Remove.
(__arm_vmaxnmaq_m_f32): Remove.
(__arm_vminnmaq_m_f32): Remove.
(__arm_vminnmaq): Remove.
(__arm_vmaxnmaq): Remove.
(__arm_vmaxnmaq_m): Remove.
(__arm_vminnmaq_m): Remove.

13 months agoarm: [MVE intrinsics] factorize vmaxnmaq vminnmaq
Christophe Lyon [Mon, 13 Feb 2023 21:12:25 +0000 (21:12 +0000)] 
arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq

Factorize vmaxnmaq and vminnmaq so that they use the same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ)
(MVE_VMAXNMA_VMINNMAQ_M): New.
(mve_insn): Add vmaxnma, vminnma.
* config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>):
Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.