Simon Marchi [Mon, 21 Dec 2015 17:51:54 +0000 (12:51 -0500)]
Remove HP-UX references fom testsuite
This patch removes all special cases for HP-UX, for which support has
been removed earlier, that I found in the testsuite. Note that the hppa
architecture != HP-UX, since other OSes can run on hppa, so I tried to
leave everything that is not HP-UX specific.
Two complete tests were completely HP-UX specific, so I removed them.
I ran the testsuite on Linux x86-64, native and native-gdbserver, and
noticed no regressions.
Simon Marchi [Mon, 21 Dec 2015 16:23:43 +0000 (11:23 -0500)]
Remove references to HP CC/aCC compiler from testsuite
The HP CC/aCC compiler is exclusive to HP-UX, for which support has been
explicitly removed. Therefore, It does not make sense to keep tests
for these compilers' quirks.
Nick Clifton [Mon, 21 Dec 2015 12:00:04 +0000 (12:00 +0000)]
Fix building pdfs of assembler documentation.
PR gas/19386
* doc/as.texinfo (Strings): Prepend a space to index entries that
start with a backslash. This works around a problem in the pdf
generator.
H.J. Lu [Fri, 18 Dec 2015 22:03:43 +0000 (14:03 -0800)]
Process 64-bit imm/disp only for 64-bit BFD
We only need to store 32-bit immediate in 64-bit and optimize 64-bit
displacement to 32-bit only for 64-bit BFD.
* config/tc-i386.c (optimize_imm): Store 32-bit immediate in
64-bit only for 64-bit BFD
(optimize_disp): Optimize 64-bit displacement to 32-bit only
for 64-bit BFD.
Simon Marchi [Fri, 18 Dec 2015 18:39:26 +0000 (13:39 -0500)]
Add documentation to gdb_compile
This patch adds some documentation to gdb_compile. It describes the
various options that can influence compilation. Most of them are
handled by DejaGnu, but are not really documented anywhere, so I think
it's good to have a quick reference. Not all possible options are
described, that would add way to much noise. I chose those that I think
are relevant in the context of writing a test case.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Enable conditional breakpoints for targets that support software single step in GDBServer
This patch enables support for conditional breakpoints if the target supports
software single step.
This was disabled before as the implementations of software single step were too
simple as discussed in
https://sourceware.org/ml/gdb-patches/2015-04/msg01110.html.
Since these issues are now fixed support can be added back.
New tests passing :
PASS: gdb.base/cond-eval-mode.exp: set breakpoint condition-evaluation
target and related...
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Support software single step on ARM in GDBServer
This patch teaches GDBServer how to software single step on ARM
linux by sharing code with GDB.
The arm_get_next_pcs function in GDB is now shared with GDBServer. So
that GDBServer can use the function to return the possible addresses of
the next PC.
A proper shared context was also needed so that we could share the code,
this context is described in the arm_get_next_pcs structure.
Testing :
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Append arm-get-next-pcs.o,
arm-linux.o.
(ALLDEPFILES): Append arm-get-next-pcs.c, arm-linux.c
(arm-linux.o): New rule.
(arm-get-next-pcs.o): New rule.
* arch/arm-get-next-pcs.c: New file.
* arch/arm-get-next-pcs.h: New file.
* arch/arm-linux.h: New file.
* arch/arm-linux.c: New file.
* arm.c: Include common-regcache.c.
(thumb_advance_itstate): Moved from arm-tdep.c.
(arm_instruction_changes_pc): Likewise.
(thumb_instruction_changes_pc): Likewise.
(thumb2_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
* arm.h (submask): Move macro from arm-tdep.h
(bit): Likewise.
(bits): Likewise.
(sbits): Likewise.
(BranchDest): Likewise.
(thumb_advance_itstate): Moved declaration from arm-tdep.h
(arm_instruction_changes_pc): Likewise.
(thumb_instruction_changes_pc): Likewise.
(thumb2_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
* arm-linux-tdep.c: Include arch/arm.h, arch/arm-get-next-pcs.h
arch/arm-linux.h.
(arm_linux_get_next_pcs_ops): New struct.
(ARM_SIGCONTEXT_R0, ARM_UCONTEXT_SIGCONTEXT,
ARM_OLD_RT_SIGFRAME_SIGINFO, ARM_OLD_RT_SIGFRAME_UCONTEXT,
ARM_NEW_RT_SIGFRAME_UCONTEXT, ARM_NEW_SIGFRAME_MAGIC): Move stack
layout defines to arch/arm-linux.h.
(arm_linux_sigreturn_next_pc_offset): Move to arch/arm-linux.c.
(arm_linux_software_single_step): Adjust for arm_get_next_pcs
implementation.
* arm-tdep.c: Include arch/arm-get-next-pcs.h.
(arm_get_next_pcs_ops): New struct.
(submask): Move macro to arm.h.
(bit): Likewise.
(bits): Likewise.
(sbits): Likewise.
(BranchDest): Likewise.
(thumb_instruction_changes_pc): Move to arm.c
(thumb2_instruction_changes_pc): Likewise.
(arm_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
(thumb_advance_itstate): Likewise.
(thumb_get_next_pc_raw): Move to arm-get-next-pcs.c.
(arm_get_next_pc_raw): Likewise.
(arm_get_next_pc): Likewise.
(thumb_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence): Likewise.
(arm_get_next_pcs_read_memory_unsigned_integer): New function.
(arm_get_next_pcs_addr_bits_remove): Likewise.
(arm_get_next_pcs_syscall_next_pc): Likewise.
(arm_get_next_pcs_is_thumb): Likewise.
(arm_software_single_step): Adjust for arm_get_next_pcs
implementation.
* arm-tdep.h: (arm_get_next_pc): Remove declaration.
(arm_get_next_pcs_read_memory_unsigned_integer):
New declaration.
(arm_get_next_pcs_addr_bits_remove): Likewise.
(arm_get_next_pcs_syscall_next_pc): Likewise.
(arm_get_next_pcs_is_thumb): Likewise.
(arm_deal_with_atomic_sequence: Remove declaration.
* common/gdb_vecs.h: Add CORE_ADDR vector definition.
* configure.tgt (aarch64*-*-linux): Add arm-get-next-pcs.o,
arm-linux.o.
(arm*-wince-pe): Add arm-get-next-pcs.o.
(arm*-*-linux*): Add arm-get-next-pcs.o, arm-linux.o,
arm-get-next-pcs.o
(arm*-*-netbsd*,arm*-*-knetbsd*-gnu): Add arm-get-next-pcs.o.
(arm*-*-openbsd*): Likewise.
(arm*-*-symbianelf*): Likewise.
(arm*-*-*): Likewise.
* symtab.h: Move CORE_ADDR vector definition to gdb_vecs.h.
gdb/gdbserver/ChangeLog:
* Makefile.in (SFILES): Append arch/arm-linux.c,
arch/arm-get-next-pcs.c.
(arm-linux.o): New rule.
(arm-get-next-pcs.o): New rule.
* configure.srv (arm*-*-linux*): Add arm-get-next-pcs.o,
arm-linux.o.
* linux-aarch32-low.c (arm_abi_breakpoint): Remove macro. Moved
to linux-aarch32-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): Make non-static.
* linux-aarch32-low.h (arm_abi_breakpoint): New macro. Moved
from linux-aarch32-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): New declaration.
* linux-arm-low.c: Include arch/arm-linux.h
aarch/arm-get-next-pcs.h, sys/syscall.h.
(get_next_pcs_ops): New struct.
(get_next_pcs_addr_bits_remove): New function.
(get_next_pcs_is_thumb): New function.
(get_next_pcs_read_memory_unsigned_integer): Likewise.
(arm_sigreturn_next_pc): Likewise.
(get_next_pcs_syscall_next_pc): Likewise.
(arm_gdbserver_get_next_pcs): Likewise.
(struct linux_target_ops) <arm_gdbserver_get_next_pcs>:
Initialize.
* linux-low.h: Move CORE_ADDR vector definition to gdb_vecs.h.
* server.h: Include gdb_vecs.h.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Share regcache function regcache_raw_read_unsigned
This patch is in preparation for software single step support on ARM in
GDBServer. It adds a new shared function regcache_raw_read_unsigned and
regcache_raw_get_unsigned so that GDB and GDBServer can use the same call
to fetch a raw register into an integer.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* Makefile.in (SFILES): Append common/common-regcache.c.
(COMMON_OBS): Append common/common-regcache.o.
(common-regcache.o): New rule.
* common/common-regcache.h (register_status) New enum.
(regcache_raw_read_unsigned): New declaration.
* common/common-regcache.c: New file.
* regcache.h (enum register_status): Move to common-regcache.h.
(regcache_raw_read_unsigned): Likewise.
(regcache_raw_get_unsigned): Likewise.
gdb/gdbserver/ChangeLog:
* Makefile.in (SFILES): Append common/common-regcache.c.
(OBS): Append common-regcache.o.
(common-regcache.o): New rule.
* regcache.c (init_register_cache): Initialize cache to
REG_UNAVAILABLE.
(regcache_raw_read_unsigned): New function.
* regcache.h (REG_UNAVAILABLE, REG_VALID): Replaced by shared
register_status enum.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Refactor arm_software_single_step to use regcache
This patch is in preparation for software single step support on ARM in
GDBServer. It refactors arm_*_software_single_step and sub-functions to
use regcache instead of frame to access registers so that the code can be
shared more easily between GDB and GDBServer.
Note also that since the intention is at some point to get rid of frame
completely in that function, memory reads have also been replaced by
read_memory_unsigned_integer rather than get_frame_memory_unsigned.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* arm-linux-tdep.c (arm_linux_sigreturn_next_pc_offset): New function.
(arm_linux_sigreturn_next_pc): Likewise.
(arm_linux_syscall_next_pc): Use regcache instead of frame.
(arm_linux_software_single_step): Likewise.
* arm-tdep.c (arm_is_thumb): New function.
(shifted_reg_va): Use regcache instead of frame.
(thumb_get_next_pc_raw): Likewise.
(arm_get_next_pc_raw): Likewise.
(arm_get_next_pc): Likewise.
(thumb_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence): Likewise.
(arm_software_single_step): Likewise.
* arm-tdep.h (struct gdbarch_tdep): Use regcache for syscall_next_pc.
(arm_get_next_pc): Use regcache.
(arm_deal_with_atomic_sequence): Likewise.
(arm_is_thumb): New declaration.
* regcache.c (regcache_raw_get_unsigned): New function.
* regcache.h (regcache_raw_get_unsigned): New function declaration.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:58 +0000 (11:33 -0500)]
Replace breakpoint_reinsert_addr by get_next_pcs operation in GDBServer
This patch in preparation for software single step support on ARM. It refactors
breakpoint_reinsert_addr into get_next_pcs so that multiple location can be
returned.
When software single stepping there can be multiple possible next addresses
because we're stepping over a conditional branch instruction, for example.
The operation get_next_pcs handles that by returning a vector of all the
possible next addresses.
Software breakpoints are installed at each location returned.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gold/
PR gold/18780
* arm.cc (Target_arm::do_make_data_plt): Choose PLT generator based
on value of --long-plt flag.
(Output_data_plt_arm_standard::do_get_plt_entry_size): Moved to
Output_data_plt_arm_short.
(Output_data_plt_arm_standard::do_fill_plt_entry): Likewise.
(Output_data_plt_arm_standard::plt_entry): Likewise.
(Output_data_plt_arm_standard::do_fill_first_plt_entry): Fix
variable reference.
(Output_data_plt_arm_short): New class.
(Output_data_plt_arm_short::do_fill_plt_entry): Error out on too large
PLT offsets instead of asserting.
(Output_data_plt_arm_long): New class.
* options.h (General_options): Define --long-plt flag.
Pedro Alves [Thu, 17 Dec 2015 14:20:52 +0000 (14:20 +0000)]
Fix PR threads/19354: "info threads" error with multiple inferiors
Note: this applies on top of:
[PATCH] Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTL
https://sourceware.org/ml/gdb-patches/2015-12/msg00214.html
We try to avoid using libthread_db.so to list threads in the inferior
when debugging live processes, but the code that decides whether to
use it decides incorrectly if you have more than one inferior, and the
current inferior doesn't have execution yet. The result is visible
as:
(gdb) add-inferior
Added inferior 2
(gdb) inferior 2
[Switching to inferior 2 [<null>] (<noexec>)]
(gdb) info inferiors
Num Description Executable
1 process 15397 /home/pedro/gdb/tests/threads
* 2 <null>
(gdb) info threads
Cannot find new threads: generic error
(gdb)
Fix this by checking whether each inferior has execution rather than
just the current inferior.
By moving the core updating to linux-nat.c's update_thread_list
implementation, this also ends up fixing the
lwp-last-seen-running-on-core updating in the case we're debugging a
program that uses raw clone rather than pthreads, as linux-thread-db.c
isn't pushed in the target stack in that scenario.
Tested on x86_64 Fedora 20.
gdb/ChangeLog:
2015-12-17 Pedro Alves <palves@redhat.com>
PR threads/19354
* linux-nat.c (linux_nat_update_thread_list): Update process cores
each lwp was last seen running on here.
* linux-thread-db.c (update_thread_core): Delete.
(thread_db_update_thread_list_td_ta_thr_iter): Rename to ...
(thread_db_update_thread_list): ... this. Skip inferiors with
execution. Also call the target beneath.
(thread_db_update_thread_list): Delete.
gdb/testsuite/ChangeLog:
2015-12-17 Pedro Alves <palves@redhat.com>
PR threads/19354
* gdb.multi/info-threads.exp: New file.
Pedro Alves [Thu, 17 Dec 2015 14:20:51 +0000 (14:20 +0000)]
Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTL
Since we now rely on PTRACE_EVENT_CLONE being available (added in
Linux 2.5.46), we're relying on NPTL.
This commit removes the support for older LinuxThreads, as well as the
workarounds for vendor 2.4 kernels with NPTL backported.
- Rely on tkill being available.
- Assume gdb doesn't get cancel signals.
- Remove code that checks the LinuxThreads restart and cancel signals
in the inferior.
- Assume that __WALL is available.
- Assume that non-leader threads report WIFEXITED.
- Thus, no longer need to send signal 0 to check whether threads are
still alive.
- Update comments throughout.
Tested on x86_64 Fedora 20, native and gdbserver.
gdb/ChangeLog:
* configure.ac: Remove tkill checks.
* configure, config.in: Regenerate.
* linux-nat.c: Remove HAVE_TKILL_SYSCALL check. Update top level
comments.
(linux_nat_post_attach_wait): Remove 'cloned' parameter. Use
__WALL.
(attach_proc_task_lwp_callback): Don't set the cloned flag.
(linux_nat_attach): Adjust.
(kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back
to 'kill'.
(linux_handle_extended_wait): Use __WALL. Don't set the cloned
flag.
(wait_lwp): Use __WALL. Update comments.
(running_callback, stop_and_resume_callback): Delete.
(linux_nat_filter_event): Don't stop and resume all lwps. Don't
check if the event LWP has previously exited.
(check_zombie_leaders): Update comments.
(linux_nat_wait_1): Use __WALL.
(kill_wait_callback): Don't handle clone processes separately.
Use __WALL instead.
(linux_thread_alive): Delete.
(linux_nat_thread_alive): Return true as long as the LWP is in the
LWP list.
(linux_nat_update_thread_list): Assume the kernel supports
PTRACE_EVENT_CLONE.
(get_signo): Delete.
(lin_thread_get_thread_signals): Remove LinuxThreads references.
No longer check __pthread_sig_restart / __pthread_sig_cancel in
the inferior.
* linux-nat.h (struct lwp_info) <cloned>: Delete field.
* linux-thread-db.c: Update comments.
(_initialize_thread_db): Remove LinuxThreads references.
* nat/linux-waitpid.c (my_waitpid): No longer emulate __WALL.
Pass down flags unmodified.
* linux-waitpid.h (my_waitpid): Update documentation.
gdb/gdbserver/ChangeLog:
* linux-low.c (linux_kill_one_lwp): Remove references to
LinuxThreads.
(kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back
to 'kill'.
(linux_init_signals): Delete.
(initialize_low): Adjust.
* thread-db.c (thread_db_init): Remove LinuxThreads reference.
Yao Qi [Thu, 17 Dec 2015 13:07:54 +0000 (13:07 +0000)]
Fix one heap buffer overflow in aarch64_push_dummy_call
Hi,
AddressSanitizer reports an error like this,
(gdb) PASS: gdb.base/call-ar-st.exp: continue to tbreak9
print print_long_arg_list(a, b, c, d, e, f, *struct1, *struct2, *struct3, *struct4, *flags, *flags_combo, *three_char, *five_char, *int_char_combo, *d1, *d2, *d3, *f1, *f2, *f3)
=================================================================
==6236==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200008eb50 at pc 0x89e432 bp 0x7fffa3df9080 sp 0x7fffa3df9078
READ of size 5 at 0x60200008eb50 thread T0
#0 0x89e431 in memory_xfer_partial gdb/target.c:1264
#1 0x89e6c7 in target_xfer_partial gdb/target.c:1320
#2 0x89f267 in target_write_partial gdb/target.c:1595^M
#3 0x8a014b in target_write_with_progress gdb/target.c:1889^M
#4 0x8a0262 in target_write gdb/target.c:1914^M
#5 0x89ee59 in target_write_memory gdb/target.c:1492^M
#6 0x9a1c74 in write_memory gdb/corefile.c:393^M
#7 0x467ea5 in aarch64_push_dummy_call gdb/aarch64-tdep.c:1388
The problem is that an instance of stack_item_t is created to adjust
stack for alignment, the item.len is correct, but item.data is buf,
which is wrong, because item.len can be greater than the length of
buf. This patch sets item.data to NULL, and only update sp (no
inferior memory writes on stack for this item).
gdb:
2015-12-17 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (struct stack_item_t): Update comments.
(pass_on_stack): Set item.data to NULL.
(aarch64_push_dummy_call): Call write_memory if si->data
isn't NULL.
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.
In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.
This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.
* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
TAG_ARCH_profile for armv8-a.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
bfd/
* bfd-in2.h: Regenerate.
* reloc.c: Add new relocations.
* libbfd.h (bfd_reloc_code_real_names): Add new relocations
display names.
* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
relocations.
(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
(elf32_arm_final_link_relocate): Implement new relocations
resolution.
gas/
* doc/c-arm.texi: Add documentation about new directives
* config/tc-arm.c (group_reloc_table): Add mapping between gas
syntax and new relocations.
(do_t_add_sub): Keep new relocations for add operand.
(do_t_mov_cmp): Keep new relocations for mov operand.
(insns): Use 'shifter operand with possible group relocation'
operand parse code for movs operand.
(md_apply_fix): Implement mov and add encoding when new
relocations on them.
(tc_gen_reloc): Add new relocations.
(arm_fix_adjustable): Since offset has a limited range ([0:255])
we disable adjust_reloc_syms() for new relocations.
gas/testsuite/
* gas/arm/adds-thumb1-reloc-local.d: New
* gas/arm/adds-thumb1-reloc-local.s: New
* gas/arm/movs-thumb1-reloc-local.d: New
* gas/arm/movs-thumb1-reloc-local.s: New
include/
* elf/arm.h: Add new arm relocations.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
tests.
* ld-arm/thumb1-adds.d: New
* ld-arm/thumb1-adds.s: New
* ld-arm/thumb1-movs.d: New
* ld-arm/thumb1-movs.s: New
We have code in configure.ac that tries to detect whether the compiler
supports each warning and suppress it if not, but that doesn't work
with "-Wno-" options, because gcc doesn't error out for
-Wno-unknown-warning unless other diagnostics are being produced.
See https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html.
Handle this by checking whether -Wfoo works when we actually want
-Wno-foo.
gdb/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* configure.ac (compiler warning flags): When testing a
-Wno-foo option, check whether -Wfoo works instead.
* configure: Regenerate.
gdb/gdbserver/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* configure.ac (compiler warning flags): When testing a
-Wno-foo option, check whether -Wfoo works instead.
* configure: Regenerate.
gdb/btrace.h: In function ‘size_t VEC_btrace_insn_s_embedded_size(int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_alloc(int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_copy(VEC_btrace_insn_s*)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_merge(VEC_btrace_insn_s*, VEC_btrace_insn_s*)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘int VEC_btrace_insn_s_reserve(VEC_btrace_insn_s**, int, const char*, unsigned int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* common/vec.h (vec_offset): New macro.
(DEF_VEC_ALLOC_FUNC_I, DEF_VEC_ALLOC_FUNC_O): Use it instead of
offsetof.
Mickael Guene [Wed, 16 Dec 2015 09:09:05 +0000 (10:09 +0100)]
[ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
movs r3, #:upper8_15:#foo
lsls r3, #8
adds r3, #:upper0_7:#foo
lsls r3, #8
adds r3, #:lower8_15:#foo
lsls r3, #8
adds r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
4: 2300 movs r3, #0
4: R_ARM_THM_ALU_ABS_G3_NC foo
6: 021b lsls r3, r3, #8
8: 3300 adds r3, #0
8: R_ARM_THM_ALU_ABS_G2_NC foo
a: 021b lsls r3, r3, #8
c: 3300 adds r3, #0
c: R_ARM_THM_ALU_ABS_G1_NC foo
e: 021b lsls r3, r3, #8
10: 3300 adds r3, #0
10: R_ARM_THM_ALU_ABS_G0_NC foo
Jan Beulich [Tue, 15 Dec 2015 13:31:25 +0000 (14:31 +0100)]
bfd: don't produce corrupt COFF symbol table due to long ELF file name symbols
The re-writing logic in _bfd_coff_final_link() overwrote the ".file"
part of the symbol table entry, due to not coping with the auxiliary
entry generated in all cases.
Note that while I would have wanted to add a test case,
(a) I didn't spot any one testing the base functionality here, and
(b) I wasn't able to figure out proper conditionals to use in e.g.
ld-elf/elf.exp to check for the necessary PE/PE+ support (which
varies by target).
Nick Clifton [Tue, 15 Dec 2015 11:01:03 +0000 (11:01 +0000)]
Add support for the MRS instruction to the AArch64 simulator.
* aarch64/simulator.c (system_get): New function. Provides read
access to the dczid system register.
(do_mrs): New function - implements the MRS instruction.
(dexSystem): Call do_mrs for the MRS instruction. Halt on
unimplemented system instructions.
Don Breazeal [Mon, 14 Dec 2015 19:18:06 +0000 (11:18 -0800)]
Target remote mode fork and exec event documentation
This patch implements documentation updates for target remote mode fork and
exec events. A summary of the rationale for the changes made here:
* Connecting to a remote target -- explain that the two protocols exist.
* Connecting in target remote mode -- explain invoking gdbserver for target
remote mode, and move remote-specific text from original "Connecting to a
remote target" section.
* Connecting in target extended-remote mode -- promote this section from
"Using the gdbserver Program | Running gdbserver | Multi-Process Mode for
gdbserver". Put it next to the target remote mode section.
* Host and target files -- collect paragraphs dealing with how to locate
symbol files from original sections "Connecting to a remote target" and
"Using the gdbserver program | Connecting to gdbserver".
* Steps for connecting to a remote target -- used to be "Using the
gdbserver program | Connecting to gdbserver"
* Remote connection commands -- used to be the bulk of "Connecting to a
remote target". Added "target extended-remote" commands and information.
gdb/ChangeLog:
* NEWS: Announce fork and exec event support for target remote.
gdb/doc/ChangeLog:
* gdb.texinfo (Forks): Correct Linux kernel version where
fork and exec events are supported, add notes about support
of these events in target remote mode.
(Connecting): Reorganize and clarify distinctions between
target remote, extended-remote, and multiprocess.
Reorganize related text from separate sections into new
sections.
(Server): Note effects of target extended-remote mode.
Delete section on Multi-Process Mode for gdbserver.
Move some text to "Connecting" node.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec event support
This patch implements support for fork and exec events with target remote
mode Linux targets. For such targets with Linux kernels 2.5.46 and later,
this enables follow-fork-mode, detach-on-fork and fork and exec
catchpoints.
The changes required to implement this included:
* Don't exit from gdbserver if there are still active inferiors.
* Allow changing the active process in remote mode.
* Enable fork and exec events in remote mode.
* Print "Ending remote debugging" only when disconnecting.
* Combine remote_kill and extended_remote_kill into a single function
that can handle the multiple inferior case for target remote. Also,
the same thing for remote_mourn and extended_remote_mourn.
* Enable process-style ptids in target remote.
* Remove restriction on multiprocess mode in target remote.
gdb/gdbserver/ChangeLog:
* server.c (process_serial_event): Don't exit from gdbserver
in remote mode if there are still active inferiors.
gdb/ChangeLog:
* inferior.c (number_of_live_inferiors): New function.
(have_live_inferiors): Use number_of_live_inferiors in place
of duplicate code.
* inferior.h (number_of_live_inferiors): Declare new function.
* remote.c (set_general_process): Remove restriction on target
remote mode.
(remote_query_supported): Likewise.
(remote_detach_1): Exit in target remote mode only when there
is just one live inferior left.
(remote_disconnect): Unpush the target directly instead of
calling remote_mourn.
(remote_kill): Rewrite function to handle both target remote
and extended-remote. Call remote_kill_k.
(remote_kill_k): New function.
(extended_remote_kill): Delete function.
(remote_mourn, extended_remote_mourn): Combine functions into
one, remote_mourn, and enable extended functionality for target
remote.
(remote_pid_to_str): Enable "process" style ptid string for
target remote.
(remote_supports_multi_process): Remove restriction on target
remote mode.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec test updates
This patch updates tests for fork and exec events in target remote mode.
In the majority of cases this was a simple matter of removing some code
that disabled the test for target remote. In a few cases the test needed
to be disabled; in those cases the gdb_protocol was checked instead of
using the [is_remote target] etc.
In a couple of cases we needed to use clean_restart, since target remote
doesn't support the run command, and in one case we had to modify an expect
expression to allow for a "multiprocess-style" ptid.
Tested with the patch that implemented target remote mode fork and exec
event support.
gdb/testsuite/ChangeLog:
* gdb.base/execl-update-breakpoints.exp (main): Enable for target
remote.
* gdb.base/foll-exec-mode.exp (main): Disable for target remote.
* gdb.base/foll-exec.exp (main): Enable for target remote.
* gdb.base/foll-fork.exp (main): Likewise.
* gdb.base/foll-vfork.exp (main): Likewise.
* gdb.base/multi-forks.exp (main): Likewise, and use clean_restart.
(proc continue_to_exit_bp_loc): Use clean_restart.
* gdb.base/pie-execl.exp (main): Disable for target remote.
* gdb.base/watch-vfork.exp (main): Enable for target remote.
* gdb.mi/mi-nsthrexec.exp (main): Likewise.
* gdb.threads/execl.exp (main): Likewise.
* gdb.threads/fork-child-threads.exp (main): Likewise.
* gdb.threads/fork-plus-threads.exp (main): Disable for target
remote.
* gdb.threads/fork-thread-pending.exp (main): Enable for target
remote.
* gdb.threads/linux-dp.exp (check_philosopher_stack): Allow
pid.tid style ptids, instead of just tid.
* gdb.threads/thread-execl.exp (main): Enable for target remote.
* gdb.threads/watchpoint-fork.exp (main): Likewise.
* gdb.trace/report.exp (use_collected_data): Allow pid.tid style
ptids, instead of just tid.
Matthew Wahab [Mon, 14 Dec 2015 17:46:21 +0000 (17:46 +0000)]
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
Matthew Wahab [Mon, 14 Dec 2015 17:40:03 +0000 (17:40 +0000)]
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.
The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.
Matthew Wahab [Mon, 14 Dec 2015 17:35:47 +0000 (17:35 +0000)]
[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Mon, 14 Dec 2015 17:27:52 +0000 (17:27 +0000)]
[AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.
The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.
include/opcode/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
Matthew Wahab [Mon, 14 Dec 2015 17:25:35 +0000 (17:25 +0000)]
[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.
The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.
The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.
This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
qualifier from per-type base and offet.
Matthew Wahab [Mon, 14 Dec 2015 17:22:36 +0000 (17:22 +0000)]
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Mon, 14 Dec 2015 17:16:50 +0000 (17:16 +0000)]
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.
The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.
Matthew Wahab [Mon, 14 Dec 2015 17:07:51 +0000 (17:07 +0000)]
[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <Hd>, <Hs>, <V>.h[<idx>]
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
fmls, fmul and fmulx to the scalar indexed element group.
Matthew Wahab [Mon, 14 Dec 2015 17:01:56 +0000 (17:01 +0000)]
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.
Matthew Wahab [Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)]
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
Matthew Wahab [Mon, 14 Dec 2015 16:54:38 +0000 (16:54 +0000)]
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
Matthew Wahab [Mon, 14 Dec 2015 16:49:34 +0000 (16:49 +0000)]
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Matthew Wahab [Mon, 14 Dec 2015 16:44:02 +0000 (16:44 +0000)]
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
Matthew Wahab [Mon, 14 Dec 2015 16:34:47 +0000 (16:34 +0000)]
[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.
The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
Immediate.
This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
Andrew Burgess [Mon, 16 Nov 2015 09:39:43 +0000 (09:39 +0000)]
gdb: Add an error when 'list -' reaches the start of a file.
When a a user uses 'list +' to list forward through a source file they
eventually reach the end of the source file. Subsequent uses of 'list
+' result in an error message like this, that let the user know they are
at the end of the source file:
Line number XXX out of range; FILENAME has YYY lines.
Compare this to the current behaviour of 'list -' which lists backwards
through a source file. When the user reaches the beginning of the
source file, subsequent uses of 'list -' result in the command silently
returning. This can be confusing if the previous uses of 'list -' have
scrolled off the users display, the user receives no reminder that the
have already seen the start of the file.
After this commit a use of 'list -' when the user has already seen the
start of a file will receive the following error:
Already at the start of FILENAME.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Add an error when trying to use
'-' to scan read off the start of the source file.
gdb/testsuite/ChangeLog:
* gdb.base/list.exp (test_list_forward): Add end of file error
test.
(test_repeat_list_command): Add end of file error test.
(test_list_backwards): Add beginning of file error test.
Andrew Burgess [Mon, 16 Nov 2015 09:33:32 +0000 (09:33 +0000)]
gdb: 'list' command, tweak handling of +/- arguments.
There is an inconsistency with the handling of the special +/- arguments
to the list command.
For the very first time that list is used (after the inferior has
changed locations) then only the first character of the argument string
is checked, so 'list +BLAH' will operate as 'list +' and 'list -----FOO'
will operate as 'list -'. This compares to each subsequent use of list,
where the whole argument string is checked, so 'list +BLAH' will try to
list lines of code around the function '+BLAH'.
This commit unifies the behaviour so that the whole argument string is
checked, in order to list the next 10, or previous 10 lines from a file
only 'list +' and 'list -' are now valid.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Check that the argument string is
a single character, either '+' or '-'.
gdb/testsuite/ChangeLog:
* gdb.base/list.exp (test_list_invalid_args): New function,
defined, and called.
Andrew Burgess [Mon, 16 Nov 2015 09:30:35 +0000 (09:30 +0000)]
gdb: Small code restructure for list_command.
Move handling of special +/- arguments to the list_command function
inside a single if block, this helps group all related functionality
together. There should be no user visible changes after this commit.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Move all handling of +/-
arguments into a single if block.
Cary Coutant [Fri, 11 Dec 2015 22:01:22 +0000 (14:01 -0800)]
Make output views accessible to Target during do_relocate().
gold/
* object.cc (Sized_relobj_file::Sized_relobj_file): Initialize
output_views_.
* object.h (Object::get_output_view): New function.
(Object::do_get_output_view): New function.
(Sized_relobj_file::do_get_output_view): New function.
(Sized_relobj_file::output_views_): New data member.
* reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to
output views in class object.
(Sized_relobj_file::do_get_output_view): New function.
Yao Qi [Fri, 11 Dec 2015 16:21:09 +0000 (16:21 +0000)]
Remove gdb.base/coremaker2.c
I happen to find that coremaker2.c isn't used in the testsuite (if I
don't miss anything). I don't believe it until I see this ChangeLog
entry,
1999-11-18 Fred Fish <fnf@cygnus.com>
* gdb.base/coremaker2.c: Add sample program for generating
cores that is more self contained than coremaker.c. Eventually
I'll add more code to this and tie it into the testsuite.
Yao Qi [Fri, 11 Dec 2015 11:19:52 +0000 (11:19 +0000)]
Use arm_eabi_breakpoint on aarch32
Nowdays, GDBserver chooses arm breakpoint instructions by checking
macro __ARM_EABI__. When aarch64 GDBserver debugs arm program,
arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined
in aarch64 compiler. This causes GDBserver chooses the wrong
breakpoint instruction for arm program. This patch fixes it.
gdb/gdbserver:
2015-12-11 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint
arm breakpoint.
Matthew Wahab [Fri, 11 Dec 2015 10:22:40 +0000 (10:22 +0000)]
[AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.
A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: Enable the statistical profiling
extension. Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 11 Dec 2015 10:11:27 +0000 (10:11 +0000)]
[AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 11 Dec 2015 09:56:07 +0000 (09:56 +0000)]
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
Matthew Wahab [Fri, 11 Dec 2015 09:52:11 +0000 (09:52 +0000)]
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
pmscr_el2.
(aarch64_sys_reg_supported_p): Add architecture feature tests for
the new registers.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
system registers.
* gas/aarch64/sysreg-2.d: Enable the statistical profiling
extension and update the expected output.
Matthew Wahab [Fri, 11 Dec 2015 09:30:26 +0000 (09:30 +0000)]
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.
The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.
This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Antoine Tremblay [Thu, 10 Dec 2015 19:43:48 +0000 (14:43 -0500)]
Fix regression revealed by corethreads.exp
This patch fixes a regression introduced by:
https://sourceware.org/ml/gdb-patches/2015-12/msg00192.html
We can't use thread_from_lwp with core files. As mentioned in a comment,
td_ta_map_lwp2thr uses ps_get_thread_area, but we can't use that
currently on core targets, as it uses ptrace directly.
Use directly record_thread instead.
This fixes :
PASS -> FAIL: gdb.threads/corethreads.exp: thread0 found
PASS -> FAIL: gdb.threads/corethreads.exp: thread1 found
gdb/ChangeLog:
* linux-thread-db.c (find_new_threads_callback): Use record_thread.