aarch64: Use canonicalize_comparison in ccmp expansion [PR117346]

While testing the patch for PR 85605 on aarch64, it was noticed that
imm_choice_comparison.c test failed. This was because canonicalize_comparison
was not being called in the ccmp case. This can be noticed without the patch
for PR 85605 as evidence of the new testcase.

Bootstrapped and tested on aarch64-linux-gnu.

PR target/117346

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_gen_ccmp_first): Call
canonicalize_comparison before figuring out the cmp_mode/cc_mode.
(aarch64_gen_ccmp_next): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/imm_choice_comparison-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

Simplify switch bit test clustering algorithm

The current switch bit test clustering enumerates all possible case
clusters combinations to find ones that fit the bit test constrains
best.  This causes performance problems with very large switches.

For bit test clustering which happens naturally in word sized chunks
I don't think such an expensive algorithm is really needed.

This patch implements a simple greedy algorithm that walks
the sorted list and examines word sized windows and tries
to cluster them.

Surprisingly the new algorithm gives consistly better clusters
for the examples I tried.

For example from the gcc bootstrap:

old: 0-15 16-31 96-175
new: 0-31 96-175

I'm not fully sure why that is, probably some bug in the old
algorithm? This shows even up in the test suite where if-to-switch-6
now can generate a switch, as well as a case in switch-1.c

I don't have a proof that the new algorithm is always as good or better,
but so far at least I don't see any counter examples.

It also fixes the excessive compile time in PR117091,
however this was already fixed by an earlier patch
that doesn't run clustering when no targets have multiple
values.

gcc/ChangeLog:

PR middle-end/117091
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests):
Change clustering algorithm to simple greedy.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/if-to-switch-6.c: Allow condition chain.
* gcc.dg/tree-ssa/switch-1.c: Allow more bit tests.
* gcc.dg/pr21643.c: Use -fno-bit-tests
* gcc.target/aarch64/pr99988.c: Use -fno-bit-tests

Only do switch bit test clustering when multiple labels point to same bb

The bit cluster code generation strategy is only beneficial when
multiple case labels point to the same code. Do a quick check if
that is the case before trying to cluster.

This fixes the switch part of PR117091 where all case labels are unique
however it doesn't address the performance problems for non unique
cases.

gcc/ChangeLog:

PR middle-end/117091
* gimple-if-to-switch.cc (if_chain::is_beneficial): Update
find_bit_test call.
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests):
Get max_c argument and bail out early if all case labels are
unique.
(switch_decision_tree::compute_cases_per_edge): Record number of
targets per label and return.
(switch_decision_tree::analyze_switch_statement): ... pass to
find_bit_tests.
* tree-switch-conversion.h: Update prototypes.

Disable -fbit-tests and -fjump-tables at -O0

gcc/ChangeLog:

* common.opt: Enable -fbit-tests and -fjump-tables only at -O1.
* opts.cc (default_options_table): Dito.

Fix miscompilation of function containing __builtin_unreachable

This is a wrong-code generation on the SPARC for a function containing
a call to __builtin_unreachable caused by the delay slot scheduling pass,
and more specifically the find_end_label function which has these lines:

  /* Otherwise, see if there is a label at the end of the function. If there
     is, it must be that RETURN insns aren't needed, so that is our return
     label and we don't have to do anything else.  */

The comment was correct 20 years ago but no longer is nowadays in the
presence of RTL epilogues and calls to __builtin_unreachable, so the
patch just removes the associated two lines of code:

  else if (LABEL_P (insn))
    *plabel = as_a <rtx_code_label *> (insn);

and otherwise contains just adjustments to the commentary.

gcc/
PR rtl-optimization/117327
* reorg.cc (find_end_label): Do not return a dangling label at the
end of the function and adjust commentary.

gcc/testsuite/
* gcc.c-torture/execute/20241029-1.c: New test.

aarch64: Remove unnecessary casts to rtx_code [PR117349]

In aarch64_gen_ccmp_first/aarch64_gen_ccmp_next, the casts
were no longer needed after r14-3412-gbf64392d66f291 which
changed the type of the arguments to rtx_code.

In aarch64_rtx_costs, they were no longer needed since
r12-4828-g1d5c43db79b7ea which changed the type of code
to rtx_code.

Pushed as obvious after a build/test for aarch64-linux-gnu.

gcc/ChangeLog:

PR target/117349
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Remove
unnecessary casts to rtx_code.
(aarch64_gen_ccmp_first): Likewise.
(aarch64_gen_ccmp_next): Likewise.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

c-family: Handle RAW_DATA_CST in complete_array_type [PR117313]

The following testcase ICEs, because
add_flexible_array_elts_to_size -> complete_array_type
is done only after braced_lists_to_strings which optimizes
RAW_DATA_CST surrounded by INTEGER_CST into a larger RAW_DATA_CST
covering even the boundaries, while I thought it is done before
that.
So, RAW_DATA_CST now can be the last constructor_elt in a CONSTRUCTOR
and so we need the function to take it into account (handle it as
RAW_DATA_CST standing for RAW_DATA_LENGTH consecutive elements).

The function wants to support both CONSTRUCTORs without indexes and with
them (for non-RAW_DATA_CST elts it was just adding 1 for the current
index).  So, if the RAW_DATA_CST elt has ce->index, we need to add
RAW_DATA_LENGTH (ce->value) - 1, while if it doesn't (and it isn't cnt == 0
case where curindex is 0), add that plus 1, i.e. RAW_DATA_LENGTH (ce->value).

2024-10-29  Jakub Jelinek  <jakub@redhat.com>

PR c/117313
gcc/c-family/
* c-common.cc (complete_array_type): For RAW_DATA_CST elements
advance curindex by RAW_DATA_LENGTH or one less than that if
ce->index is non-NULL.  Handle even the first element if
it is RAW_DATA_CST.  Formatting fix.
gcc/testsuite/
* c-c++-common/init-6.c: New test.

c++: printing AGGR_INIT_EXPR args

PR30854 was about wrongly dumping the dummy object argument to a
constructor; r126582 in 4.3 fixed that by skipping the first argument.  But
not all functions called by AGGR_INIT_EXPR are constructors, as observed in
PR116634; we shouldn't skip for non-member functions.  And let's combine the
printing code for CALL_EXPR and AGGR_INIT_EXPR.

This doesn't make us accept the ill-formed 116634 testcase again with a
pedwarn, just fixes the diagnostic issue.

PR c++/30854
PR c++/116634

gcc/cp/ChangeLog:

* error.cc (dump_aggr_init_expr_args): Remove.
(dump_call_expr_args): Handle AGGR_INIT_EXPR.
(dump_expr): Combine AGGR_INIT_EXPR and CALL_EXPR cases.

gcc/testsuite/ChangeLog:

* g++.dg/coroutines/coro-bad-alloc-02-no-op-new-nt.C: Adjust
diagnostic.
* g++.dg/diagnostic/aggr-init1.C: New test.

[RISC-V] RISC-V: Add implication for M extension.

That M implies Zmmul.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: M implies Zmmul.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-15.c: Add _zmmul1p0 to arch string.
* gcc.target/riscv/attribute-16.c: Ditto.
* gcc.target/riscv/attribute-17.c: Ditto.
* gcc.target/riscv/attribute-18.c: Ditto.
* gcc.target/riscv/attribute-19.c: Ditto.
* gcc.target/riscv/pr110696.c: Ditto.
* gcc.target/riscv/target-attr-01.c: Ditto.
* gcc.target/riscv/target-attr-02.c: Ditto.
* gcc.target/riscv/target-attr-03.c: Ditto.
* gcc.target/riscv/target-attr-04.c: Ditto.
* gcc.target/riscv/target-attr-08.c: Ditto.
* gcc.target/riscv/target-attr-11.c: Ditto.
* gcc.target/riscv/target-attr-14.c: Ditto.
* gcc.target/riscv/target-attr-15.c: Ditto.
* gcc.target/riscv/target-attr-16.c: Ditto.
* gcc.target/riscv/rvv/base/pr114352-1.c: Likewise.
* gcc.target/riscv/rvv/base/pr114352-3.c: Likewise.
* gcc.dg/pr90838.c: Fix search string for rv64.

Co-Authored-By: Jeff Law <jlaw@ventanamicro.com>

testcase: Add testcase for tree-optimization/117341

Even though PR 117341 was a duplicate of PR 116768, another
testcase this time C++ does not hurt to have.
The testcase is a self-contained and does not use directly libstdc++
except for operator new (it does not even call delete).

Tested on x86_64-linux-gnu with it working.

PR tree-optimization/117341

gcc/testsuite/ChangeLog:

* g++.dg/torture/pr117341-1.C: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

[PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-32.c: New test.
* gcc.target/riscv/cmo-64.c: New test.

[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions

gcc/ChangeLog:

* config.gcc: Add riscv_cmo.h.
* config/riscv/riscv_cmo.h: New file.

RISC-V: Add testcases for form 1 of MASK_LEN_STRIDED_LOAD{STORE}

Form 1:
  void __attribute__((noinline))                                        \
  vec_strided_load_store_##T##_form_1 (T *restrict out, T *restrict in, \
       long stride, size_t size)        \
  {                                                                     \
    for (size_t i = 0; i < size; i++)                                   \
      out[i * stride] = in[i * stride];                                 \
  }

The below test suites are passed for this patch:
* The riscv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add strided folder.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-f64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-run-1-u8.c: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st.h: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st_data.h: New test.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st_run.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>

RISC-V: Implement the MASK_LEN_STRIDED_LOAD{STORE}

This patch would like to implment the MASK_LEN_STRIDED_LOAD{STORE} in
the RISC-V backend by leveraging the vector strided load/store insn.

For example:
void foo (int * __restrict a, int * __restrict b, int stride, int n)
{
    for (int i = 0; i < n; i++)
      a[i*stride] = b[i*stride] + 100;
}

Before this patch:
  38   │     vsetvli a5,a3,e32,m1,ta,ma
  39   │     vluxei64.v  v1,(a1),v4
  40   │     mul a4,a2,a5
  41   │     sub a3,a3,a5
  42   │     vadd.vv v1,v1,v2
  43   │     vsuxei64.v  v1,(a0),v4
  44   │     add a1,a1,a4
  45   │     add a0,a0,a4

After this patch:
  33   │     vsetvli a5,a3,e32,m1,ta,ma
  34   │     vlse32.v    v1,0(a1),a2
  35   │     mul a4,a2,a5
  36   │     sub a3,a3,a5
  37   │     vadd.vv v1,v1,v2
  38   │     vsse32.v    v1,0(a0),a2
  39   │     add a1,a1,a4
  40   │     add a0,a0,a4

The below test suites are passed for this patch:
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/autovec.md (mask_len_strided_load_<mode>): Add
new pattern for MASK_LEN_STRIDED_LOAD.
(mask_len_strided_store_<mode>): Ditto but for store.
* config/riscv/riscv-protos.h (expand_strided_load): Add new
func decl to expand strided load.
(expand_strided_store): Ditto but for store.
* config/riscv/riscv-v.cc (expand_strided_load): Add new
func impl to expand strided load.
(expand_strided_store): Ditto but for store.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>

RISC-V: Adjust the gather-scatter testcases due to middle-end change

After we have MASK_LEN_STRIDED_LOAD{STORE} in the middle-end, the
strided case need to be adjust for IR check.

The below test suites are passed for this patch:
* The riscv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c:
Adjust IR for MASK_LEN_LOAD check.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c:
Ditto but for store.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c:
Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Vect: Introduce MASK_LEN_STRIDED_LOAD{STORE} to loop vectorizer

This patch would like to allow generation of MASK_LEN_STRIDED_LOAD{STORE} IR
for invariant stride memory access.  For example as below

void foo (int * __restrict a, int * __restrict b, int stride, int n)
{
    for (int i = 0; i < n; i++)
      a[i*stride] = b[i*stride] + 100;
}

Before this patch:
  66   │   _73 = .SELECT_VL (ivtmp_71, POLY_INT_CST [4, 4]);
  67   │   _52 = _54 * _73;
  68   │   vect__5.16_61 = .MASK_LEN_GATHER_LOAD (vectp_b.14_59, _58, 4, { 0, ... }, { -1, ... }, _73, 0);
  69   │   vect__7.17_63 = vect__5.16_61 + { 100, ... };
  70   │   .MASK_LEN_SCATTER_STORE (vectp_a.18_67, _58, 4, vect__7.17_63, { -1, ... }, _73, 0);
  71   │   vectp_b.14_60 = vectp_b.14_59 + _52;
  72   │   vectp_a.18_68 = vectp_a.18_67 + _52;
  73   │   ivtmp_72 = ivtmp_71 - _73;

After this patch:
  60   │   _70 = .SELECT_VL (ivtmp_68, POLY_INT_CST [4, 4]);
  61   │   _52 = _54 * _70;
  62   │   vect__5.16_58 = .MASK_LEN_STRIDED_LOAD (vectp_b.14_56, _55, { 0, ... }, { -1, ... }, _70, 0);
  63   │   vect__7.17_60 = vect__5.16_58 + { 100, ... };
  64   │   .MASK_LEN_STRIDED_STORE (vectp_a.18_64, _55, vect__7.17_60, { -1, ... }, _70, 0);
  65   │   vectp_b.14_57 = vectp_b.14_56 + _52;
  66   │   vectp_a.18_65 = vectp_a.18_64 + _52;
  67   │   ivtmp_69 = ivtmp_68 - _70;

The below test suites are passed for this patch:
* The x86 bootstrap test.
* The x86 fully regression test.
* The riscv fully regression test.

gcc/ChangeLog:

* tree-vect-stmts.cc (vect_get_strided_load_store_ops): Handle
MASK_LEN_STRIDED_LOAD{STORE} after supported check.
(vectorizable_store): Generate MASK_LEN_STRIDED_LOAD when the offset
of gater is not vector type.
(vectorizable_load): Ditto but for store.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Internal-fn: Introduce new IFN MASK_LEN_STRIDED_LOAD{STORE}

This patch would like to introduce new IFN for strided load and store.

LOAD:  v = MASK_LEN_STRIDED_LOAD (ptr, stride, mask, len, bias)
STORE: MASK_LEN_STRIED_STORE (ptr, stride, v, mask, len, bias)

The IFN target below code example similar as below

void foo (int * a, int * b, int stride, int n)
{
  for (int i = 0; i < n; i++)
    a[i * stride] = b[i * stride];
}

The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

* internal-fn.cc (strided_load_direct): Add new define direct
for strided load.
(strided_store_direct): Ditto but for store.
(expand_strided_load_optab_fn): Add new func to expand the IFN
MASK_LEN_STRIDED_LOAD in middle-end.
(expand_strided_store_optab_fn): Ditto but for store.
(direct_strided_load_optab_supported_p): Add define for stride
load optab supported.
(direct_strided_store_optab_supported_p): Ditto but for store.
(internal_fn_len_index): Add strided load/store len index.
(internal_fn_mask_index): Ditto but for mask.
(internal_fn_stored_value_index): Add strided store value index.
* internal-fn.def (MASK_LEN_STRIDED_LOAD): Add new IFN for
strided load.
(MASK_LEN_STRIDED_STORE): Ditto but for store.
* optabs.def (mask_len_strided_load_optab): Add strided load optab.
(mask_len_strided_store_optab): Add strided store optab.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Remove dead vect_recog_mixed_size_cond_pattern

vect_recog_mixed_size_cond_pattern only applies to COMPARISON_CLASS_P
rhs1 COND_EXPRs which no longer appear - the following removes it.
Its testcases still pass, I believe the situation is mitigated by
bool pattern handling of the compare use in COND_EXPRs.

* tree-vect-patterns.cc (type_conversion_p): Remove.
(vect_recog_mixed_size_cond_pattern): Likewise.
(vect_vect_recog_func_ptrs): Remove vect_recog_mixed_size_cond_pattern
entry.

Remove dead code in vectorizer pattern recog

The following removes the code path in vect_recog_mask_conversion_pattern
dealing with comparisons in COND_EXPRs.  That can no longer happen.

* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Remove COMPARISON_CLASS_P rhs1 of COND_EXPR case and assert
it doesn't happen.

libstdc++: Fix complexity of drop_view::begin() const [PR112641]

Views are required to have a amortized O(1) begin(), but our drop_view's
const begin overload is O(n) for non-common ranges with a non-sized
sentinel.  This patch reimplements it so that it's O(1) always.  See
also LWG 4009.

PR libstdc++/112641

libstdc++-v3/ChangeLog:

* include/std/ranges (drop_view::begin): Reimplement const
overload so that it's O(1) always.
* testsuite/std/ranges/adaptors/drop.cc (test10): New test.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>

jit: fix leak of pending_assemble_externals_set [PR117275]

My recent r15-4580-g779c0390e3b57d fix for resetting state in
varasm.cc introduced some noise to "make selftest-valgrind" and,
presumably, a memory leak in libgccjit:

==2462086== 160 (56 direct, 104 indirect) bytes in 1 blocks are definitely lost in loss record 248 of 352
==2462086==    at 0x5270E7D: operator new(unsigned long) (vg_replace_malloc.c:342)
==2462086==    by 0x1D1EB89: init_varasm_once() (varasm.cc:6806)
==2462086==    by 0x181C845: backend_init() (toplev.cc:1826)
==2462086==    by 0x181D41A: do_compile() (toplev.cc:2193)
==2462086==    by 0x181D99C: toplev::main(int, char**) (toplev.cc:2371)
==2462086==    by 0x378391D: main (main.cc:39)

Fixed thusly.

gcc/ChangeLog:
PR jit/117275
* varasm.cc (process_pending_assemble_externals): Reset
pending_assemble_externals_set to nullptr after deleting it.
(varasm_cc_finalize): Delete pending_assemble_externals_set.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

tree-optimization/117343 - decide_masked_load_lanes and stale graph

It turns out decide_masked_load_lanes accesses a stale SLP graph
so the following re-builds it instead.

PR tree-optimization/117343
* tree-vect-slp.cc (vect_optimize_slp_pass::build_vertices):
Support re-building the SLP graph.
(vect_optimize_slp_pass::run): Re-build the SLP graph before
decide_masked_load_lanes.

tree-optimization/117333 - ICE with NULL access size DR

dr_may_alias_p ICEs when TYPE_SIZE of DR->ref is NULL but this is
valid IL when the access size of an aggregate copy can be infered
from the RHS.

PR tree-optimization/117333
* tree-data-ref.cc (dr_may_alias_p): Guard against NULL
access size.

* gcc.dg/torture/pr117333.c: New testcase.

libstdc++: Use if consteval rather than if (std::__is_constant_evaluated()) for {,b}float16_t nextafter [PR117321]

The nextafter_c++23.cc testcase fails to link at -O0.
The problem is that eventhough std::__is_constant_evaluated() has
always_inline attribute, that at -O0 just means that we inline the
call, but its result is still assigned to a temporary which is tested
later, nothing at -O0 propagates that false into the if and optimizes
away the if body.  And the __builtin_nextafterf16{,b} calls are meant
to be used solely for constant evaluation, the C libraries don't
define nextafterf16 these days.

As __STDCPP_FLOAT16_T__ and __STDCPP_BFLOAT16_T__ are predefined right
now only by GCC, not by clang which doesn't implement the extended floating
point types paper, and as they are predefined in C++23 and later modes only,
I think we can just use if consteval which is folded already during the FE
and the body isn't included even at -O0.  I've added a feature test for
that just in case clang implements those and implements those in some weird
way.  Note, if (__builtin_is_constant_evaluted()) would work correctly too,
that is also folded to false at gimplification time and the corresponding
if block not emitted at all.  But for -O0 it can't be wrapped into a helper
inline function.

2024-10-29  Jakub Jelinek  <jakub@redhat.com>

PR libstdc++/117321
* include/c_global/cmath (nextafter(_Float16, _Float16)): Use
if consteval rather than if (std::__is_constant_evaluated()) around
the __builtin_nextafterf16 call.
(nextafter(__gnu_cxx::__bfloat16_t, __gnu_cxx::__bfloat16_t)): Use
if consteval rather than if (std::__is_constant_evaluated()) around
the __builtin_nextafterf16b call.
* testsuite/26_numerics/headers/cmath/117321.cc: New test.

ada: Fix static_assert with one argument

Single argument static_assert is C++17 only and breaks the build using
older GCC (prerequisite is C++14).

gcc/ada

* types.h: fix static_assert.

arm: [MVE intrinsics] Rework MVE vld/vst intrinsics

Implement the mve vld and vst intrinsics using the MVE builtins framework.

The main part of the patch is to reimplement to vstr/vldr patterns
such that we now have much fewer of them:
- non-truncating stores
- predicated non-truncating stores
- truncating stores
- predicated truncating stores
- non-extending loads
- predicated non-extending loads
- extending loads
- predicated extending loads

This enables us to update the implementation of vld1/vst1 and use the
new vldr/vstr builtins.

The patch also adds support for the predicated vld1/vst1 versions.

gcc.target/arm/pr112337.c needs an update, to call the intrinsic
instead of the builtin, which this patch deletes.

2024-09-11  Alfie Richards  <Alfie.Richards@arm.com>
    Christophe Lyon  <christophe.lyon@arm.com>

gcc/

* config/arm/arm-mve-builtins-base.cc (vld1q_impl): Add support
for predicated version.
(vst1q_impl): Likewise.
(vstrq_impl): New class.
(vldrq_impl): New class.
(vldrbq): New.
(vldrhq): New.
(vldrwq): New.
(vstrbq): New.
(vstrhq): New.
(vstrwq): New.
* config/arm/arm-mve-builtins-base.def (vld1q): Add predicated
version.
(vldrbq): New.
(vldrhq): New.
(vldrwq): New.
(vst1q): Add predicated version.
(vstrbq): New.
(vstrhq): New.
(vstrwq): New.
(vrev32q): Update types to float_16.
* config/arm/arm-mve-builtins-base.h (vldrbq): New.
(vldrhq): New.
(vldrwq): New.
(vstrbq): New.
(vstrhq): New.
(vstrwq): New.
* config/arm/arm-mve-builtins-functions.h (memory_vector_mode):
Remove conversion of floating point vectors to integer.
* config/arm/arm-mve-builtins.cc (TYPES_float16): Change to...
(TYPES_float_16): ...this.
(TYPES_float_32): New.
(float16): Change to...
(float_16): ...this.
(float_32): New.
(preds_z_or_none): New.
(function_resolver::check_gp_argument): Add support for _z
predicate.
* config/arm/arm_mve.h (vstrbq): Remove.
(vstrbq_p): Likewise.
(vstrhq): Likewise.
(vstrhq_p): Likewise.
(vstrwq): Likewise.
(vstrwq_p): Likewise.
(vst1q_p): Likewise.
(vld1q_z): Likewise.
(vldrbq_s8): Likewise.
(vldrbq_u8): Likewise.
(vldrbq_s16): Likewise.
(vldrbq_u16): Likewise.
(vldrbq_s32): Likewise.
(vldrbq_u32): Likewise.
(vstrbq_s8): Likewise.
(vstrbq_s32): Likewise.
(vstrbq_s16): Likewise.
(vstrbq_u8): Likewise.
(vstrbq_u32): Likewise.
(vstrbq_u16): Likewise.
(vstrbq_p_s8): Likewise.
(vstrbq_p_s32): Likewise.
(vstrbq_p_s16): Likewise.
(vstrbq_p_u8): Likewise.
(vstrbq_p_u32): Likewise.
(vstrbq_p_u16): Likewise.
(vldrbq_z_s16): Likewise.
(vldrbq_z_u8): Likewise.
(vldrbq_z_s8): Likewise.
(vldrbq_z_s32): Likewise.
(vldrbq_z_u16): Likewise.
(vldrbq_z_u32): Likewise.
(vldrhq_s32): Likewise.
(vldrhq_s16): Likewise.
(vldrhq_u32): Likewise.
(vldrhq_u16): Likewise.
(vldrhq_z_s32): Likewise.
(vldrhq_z_s16): Likewise.
(vldrhq_z_u32): Likewise.
(vldrhq_z_u16): Likewise.
(vldrwq_s32): Likewise.
(vldrwq_u32): Likewise.
(vldrwq_z_s32): Likewise.
(vldrwq_z_u32): Likewise.
(vldrhq_f16): Likewise.
(vldrhq_z_f16): Likewise.
(vldrwq_f32): Likewise.
(vldrwq_z_f32): Likewise.
(vstrhq_f16): Likewise.
(vstrhq_s32): Likewise.
(vstrhq_s16): Likewise.
(vstrhq_u32): Likewise.
(vstrhq_u16): Likewise.
(vstrhq_p_f16): Likewise.
(vstrhq_p_s32): Likewise.
(vstrhq_p_s16): Likewise.
(vstrhq_p_u32): Likewise.
(vstrhq_p_u16): Likewise.
(vstrwq_f32): Likewise.
(vstrwq_s32): Likewise.
(vstrwq_u32): Likewise.
(vstrwq_p_f32): Likewise.
(vstrwq_p_s32): Likewise.
(vstrwq_p_u32): Likewise.
(vst1q_p_u8): Likewise.
(vst1q_p_s8): Likewise.
(vld1q_z_u8): Likewise.
(vld1q_z_s8): Likewise.
(vst1q_p_u16): Likewise.
(vst1q_p_s16): Likewise.
(vld1q_z_u16): Likewise.
(vld1q_z_s16): Likewise.
(vst1q_p_u32): Likewise.
(vst1q_p_s32): Likewise.
(vld1q_z_u32): Likewise.
(vld1q_z_s32): Likewise.
(vld1q_z_f16): Likewise.
(vst1q_p_f16): Likewise.
(vld1q_z_f32): Likewise.
(vst1q_p_f32): Likewise.
(__arm_vstrbq_s8): Likewise.
(__arm_vstrbq_s32): Likewise.
(__arm_vstrbq_s16): Likewise.
(__arm_vstrbq_u8): Likewise.
(__arm_vstrbq_u32): Likewise.
(__arm_vstrbq_u16): Likewise.
(__arm_vldrbq_s8): Likewise.
(__arm_vldrbq_u8): Likewise.
(__arm_vldrbq_s16): Likewise.
(__arm_vldrbq_u16): Likewise.
(__arm_vldrbq_s32): Likewise.
(__arm_vldrbq_u32): Likewise.
(__arm_vstrbq_p_s8): Likewise.
(__arm_vstrbq_p_s32): Likewise.
(__arm_vstrbq_p_s16): Likewise.
(__arm_vstrbq_p_u8): Likewise.
(__arm_vstrbq_p_u32): Likewise.
(__arm_vstrbq_p_u16): Likewise.
(__arm_vldrbq_z_s8): Likewise.
(__arm_vldrbq_z_s32): Likewise.
(__arm_vldrbq_z_s16): Likewise.
(__arm_vldrbq_z_u8): Likewise.
(__arm_vldrbq_z_u32): Likewise.
(__arm_vldrbq_z_u16): Likewise.
(__arm_vldrhq_s32): Likewise.
(__arm_vldrhq_s16): Likewise.
(__arm_vldrhq_u32): Likewise.
(__arm_vldrhq_u16): Likewise.
(__arm_vldrhq_z_s32): Likewise.
(__arm_vldrhq_z_s16): Likewise.
(__arm_vldrhq_z_u32): Likewise.
(__arm_vldrhq_z_u16): Likewise.
(__arm_vldrwq_s32): Likewise.
(__arm_vldrwq_u32): Likewise.
(__arm_vldrwq_z_s32): Likewise.
(__arm_vldrwq_z_u32): Likewise.
(__arm_vstrhq_s32): Likewise.
(__arm_vstrhq_s16): Likewise.
(__arm_vstrhq_u32): Likewise.
(__arm_vstrhq_u16): Likewise.
(__arm_vstrhq_p_s32): Likewise.
(__arm_vstrhq_p_s16): Likewise.
(__arm_vstrhq_p_u32): Likewise.
(__arm_vstrhq_p_u16): Likewise.
(__arm_vstrwq_s32): Likewise.
(__arm_vstrwq_u32): Likewise.
(__arm_vstrwq_p_s32): Likewise.
(__arm_vstrwq_p_u32): Likewise.
(__arm_vst1q_p_u8): Likewise.
(__arm_vst1q_p_s8): Likewise.
(__arm_vld1q_z_u8): Likewise.
(__arm_vld1q_z_s8): Likewise.
(__arm_vst1q_p_u16): Likewise.
(__arm_vst1q_p_s16): Likewise.
(__arm_vld1q_z_u16): Likewise.
(__arm_vld1q_z_s16): Likewise.
(__arm_vst1q_p_u32): Likewise.
(__arm_vst1q_p_s32): Likewise.
(__arm_vld1q_z_u32): Likewise.
(__arm_vld1q_z_s32): Likewise.
(__arm_vldrwq_f32): Likewise.
(__arm_vldrwq_z_f32): Likewise.
(__arm_vldrhq_z_f16): Likewise.
(__arm_vldrhq_f16): Likewise.
(__arm_vstrwq_p_f32): Likewise.
(__arm_vstrwq_f32): Likewise.
(__arm_vstrhq_f16): Likewise.
(__arm_vstrhq_p_f16): Likewise.
(__arm_vld1q_z_f16): Likewise.
(__arm_vst1q_p_f16): Likewise.
(__arm_vld1q_z_f32): Likewise.
(__arm_vst2q_f32): Likewise.
(__arm_vst1q_p_f32): Likewise.
(__arm_vstrbq): Likewise.
(__arm_vstrbq_p): Likewise.
(__arm_vstrhq): Likewise.
(__arm_vstrhq_p): Likewise.
(__arm_vstrwq): Likewise.
(__arm_vstrwq_p): Likewise.
(__arm_vst1q_p): Likewise.
(__arm_vld1q_z): Likewise.
* config/arm/arm_mve_builtins.def:
(vstrbq_s): Delete.
(vstrbq_u): Likewise.
(vldrbq_s): Likewise.
(vldrbq_u): Likewise.
(vstrbq_p_s): Likewise.
(vstrbq_p_u): Likewise.
(vldrbq_z_s): Likewise.
(vldrbq_z_u): Likewise.
(vld1q_u): Likewise.
(vld1q_s): Likewise.
(vldrhq_z_u): Likewise.
(vldrhq_u): Likewise.
(vldrhq_z_s): Likewise.
(vldrhq_s): Likewise.
(vld1q_f): Likewise.
(vldrhq_f): Likewise.
(vldrhq_z_f): Likewise.
(vldrwq_f): Likewise.
(vldrwq_s): Likewise.
(vldrwq_u): Likewise.
(vldrwq_z_f): Likewise.
(vldrwq_z_s): Likewise.
(vldrwq_z_u): Likewise.
(vst1q_u): Likewise.
(vst1q_s): Likewise.
(vstrhq_p_u): Likewise.
(vstrhq_u): Likewise.
(vstrhq_p_s): Likewise.
(vstrhq_s): Likewise.
(vst1q_f): Likewise.
(vstrhq_f): Likewise.
(vstrhq_p_f): Likewise.
(vstrwq_f): Likewise.
(vstrwq_s): Likewise.
(vstrwq_u): Likewise.
(vstrwq_p_f): Likewise.
(vstrwq_p_s): Likewise.
(vstrwq_p_u): Likewise.
* config/arm/iterators.md (MVE_w_narrow_TYPE): New iterator.
(MVE_w_narrow_type): New iterator.
(MVE_wide_n_TYPE): New attribute.
(MVE_wide_n_type): New attribute.
(MVE_wide_n_sz_elem): New attribute.
(MVE_wide_n_VPRED): New attribute.
(MVE_elem_ch): New attribute.
(supf): Remove VSTRBQ_S, VSTRBQ_U, VLDRBQ_S, VLDRBQ_U, VLD1Q_S,
VLD1Q_U, VLDRHQ_S, VLDRHQ_U, VLDRWQ_S, VLDRWQ_U, VST1Q_S, VST1Q_U,
VSTRHQ_S, VSTRHQ_U, VSTRWQ_S, VSTRWQ_U.
(VSTRBQ, VLDRBQ, VLD1Q, VLDRHQ, VLDRWQ, VST1Q, VSTRHQ, VSTRWQ):
Delete.
* config/arm/mve.md (mve_vstrbq_<supf><mode>): Remove.
(mve_vldrbq_<supf><mode>): Likewise.
(mve_vstrbq_p_<supf><mode>): Likewise.
(mve_vldrbq_z_<supf><mode>): Likewise.
(mve_vldrhq_fv8hf): Likewise.
(mve_vldrhq_<supf><mode>): Likewise.
(mve_vldrhq_z_fv8hf): Likewise.
(mve_vldrhq_z_<supf><mode>): Likewise.
(mve_vldrwq_fv4sf): Likewise.
(mve_vldrwq_<supf>v4si): Likewise.
(mve_vldrwq_z_fv4sf): Likewise.
(mve_vldrwq_z_<supf>v4si): Likewise.
(@mve_vld1q_f<mode>): Likewise.
(@mve_vld1q_<supf><mode>): Likewise.
(mve_vstrhq_fv8hf): Likewise.
(mve_vstrhq_p_fv8hf): Likewise.
(mve_vstrhq_p_<supf><mode>): Likewise.
(mve_vstrhq_<supf><mode>): Likewise.
(mve_vstrwq_fv4sf): Likewise.
(mve_vstrwq_p_fv4sf): Likewise.
(mve_vstrwq_p_<supf>v4si): Likewise.
(mve_vstrwq_<supf>v4si): Likewise.
(@mve_vst1q_f<mode>): Likewise.
(@mve_vst1q_<supf><mode>): Likewise.
(@mve_vstrq_<mode>): New.
(@mve_vstrq_p_<mode>): New.
(@mve_vstrq_truncate_<mode>): New.
(@mve_vstrq_p_truncate_<mode>): New.
(@mve_vldrq_<mode>): New.
(@mve_vldrq_z_<mode>): New.
(@mve_vldrq_extend_<mode><US>): New.
(@mve_vldrq_z_extend_<mode><US>): New.
* config/arm/unspecs.md:
(VSTRBQ_S): Remove.
(VSTRBQ_U): Likewise.
(VLDRBQ_S): Likewise.
(VLDRBQ_U): Likewise.
(VLD1Q_F): Likewise.
(VLD1Q_S): Likewise.
(VLD1Q_U): Likewise.
(VLDRHQ_F): Likewise.
(VLDRHQ_U): Likewise.
(VLDRHQ_S): Likewise.
(VLDRWQ_F): Likewise.
(VLDRWQ_S): Likewise.
(VLDRWQ_U): Likewise.
(VSTRHQ_F): Likewise.
(VST1Q_S): Likewise.
(VST1Q_U): Likewise.
(VSTRHQ_U): Likewise.
(VSTRWQ_S): Likewise.
(VSTRWQ_U): Likewise.
(VSTRWQ_F): Likewise.
(VST1Q_F): Likewise.
(VLDRQ): New.
(VLDRQ_Z): Likewise.
(VLDRQ_EXT): Likewise.
(VLDRQ_EXT_Z): Likewise.
(VSTRQ): Likewise.
(VSTRQ_P): Likewise.
(VSTRQ_TRUNC): Likewise.
(VSTRQ_TRUNC_P): Likewise.

gcc/testsuite/
* gcc.target/arm/pr112337.c: Call intrinsic instead of builtin.

arm: [MVE intrinsics] Add support for predicated contiguous loads and stores

This patch extends
function_expander::use_contiguous_load_insn and
function_expander::use_contiguous_store_insn functions to
support predicated versions.

2024-09-11  Alfie Richards  <Alfie.Richards@arm.com>
    Christophe Lyon  <christophe.lyon@arm.com>

gcc/

* config/arm/arm-mve-builtins.cc
(function_expander::use_contiguous_load_insn): Add support for
PRED_z.
(function_expander::use_contiguous_store_insn): Add support for
PRED_p.

arm: [MVE intrinsics] Add load_extending and store_truncating function bases

This patch adds the load_extending and store_truncating function bases
for MVE intrinsics.

The constructors have parameters describing the memory element
type/width which is part of the function base name (e.g. "h" in
vldrhq).

2024-09-11  Alfie Richards <Alfie.Richards@arm.com>

gcc/

* config/arm/arm-mve-builtins-functions.h
(load_extending): New class.
(store_truncating): New class.
* config/arm/arm-protos.h (arm_mve_data_mode): New helper function.
* config/arm/arm.cc (arm_mve_data_mode): New helper function.

arm: [MVE intrinsics] Add load_ext intrinsic shape

This patch adds the extending load shape.
It also adds/fixes comments for the load and store shapes.

2024-09-11  Alfie Richards <Alfie.Richards@arm.com>
    Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc:
(load_ext): New.
* config/arm/arm-mve-builtins-shapes.h:
(load_ext): New.

arm: [MVE intrinsics] fix vst tests

The tests for vst* instrinsics use functions which return a void
expression which can generate a warning. This hasn't come up previously
as the inlining presumably prevents the warning.

This change removed the uneccessary and incorrect returns.

2024-09-11  Alfie Richards <Alfie.Richards@arm.com>

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/vst1q_p_f16.c: Remove `return`.
* gcc.target/arm/mve/intrinsics/vst1q_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst2q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst4q_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_s8.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_p_u8.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrbq_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_offset_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_p_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrdq_scatter_shifted_offset_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_f16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u16.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_scatter_shifted_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrhq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.

c: Add __builtin_stdc_rotate_{left,right} builtins [PR117030]

I believe the new C2Y <stdbit.h> type-generic functions
stdc_rotate_{left,right} have the same problems the other stdc_*
type-generic functions had.  If we want to support arbitrary
unsigned _BitInt(N), don't want to use statement expressions
(so that one can actually use them in static variable initializers),
don't want to evaluate the arguments multiple times and don't want
to expand the arguments multiple times during preprocessing to avoid the
old tgmath preprocessing bloat, we need a built-in for those.

The following patch adds those.  And as we need to support rotations by 0
and tree-ssa-forwprop.cc is only able to pattern recognize with BIT_AND_EXPR
for that case (i.e. for power of two widths), the patch just constructs
LROTATE_EXPR/RROTATE_EXPR right away.  Negative second arguments are
considered UB, while positive ones are modulo precision.

2024-10-29  Jakub Jelinek  <jakub@redhat.com>

PR c/117030
gcc/
* doc/extend.texi (__builtin_stdc_rotate_left,
__builtin_stdc_rotate_right): Document.
gcc/c-family/
* c-common.cc (c_common_reswords): Add __builtin_stdc_rotate_left
and __builtin_stdc_rotate_right.
* c-ubsan.cc (ubsan_instrument_shift): For {L,R}ROTATE_EXPR
just check if op1 is negative.
gcc/c/
* c-parser.cc: Include asan.h and c-family/c-ubsan.h.
(c_parser_postfix_expression): Handle __builtin_stdc_rotate_left
and __builtin_stdc_rotate_right.
* c-fold.cc (c_fully_fold_internal): Handle LROTATE_EXPR and
RROTATE_EXPR.
gcc/testsuite/
* gcc.dg/builtin-stdc-rotate-1.c: New test.
* gcc.dg/builtin-stdc-rotate-2.c: New test.
* gcc.dg/ubsan/builtin-stdc-rotate-1.c: New test.
* gcc.dg/ubsan/builtin-stdc-rotate-2.c: New test.

Daily bump.

testsuite: drop the "test-" prefix from sarif-output python scripts

Drop the "text-" prefix from the various gcc.dg/sarif-output/test-*.py
scripts so that the scripts are close to the .c files they are used by
when the files are sorted by name.

gcc/testsuite/ChangeLog:
* gcc.dg/sarif-output/test-bad-pragma.py: Rename to...
* gcc.dg/sarif-output/bad-pragma.py: ...this.
* gcc.dg/sarif-output/bad-pragma.c: Update for script renaming.
* gcc.dg/sarif-output/test-include-chain-1.py: Rename to...
* gcc.dg/sarif-output/include-chain-1.py: ...this.
* gcc.dg/sarif-output/include-chain-1.c: Update for script renaming.
* gcc.dg/sarif-output/test-include-chain-2.py: Rename to...
* gcc.dg/sarif-output/include-chain-2.py: ...this.
* gcc.dg/sarif-output/include-chain-2.c: Update for script renaming.
* gcc.dg/sarif-output/test-missing-semicolon.py: Rename to...
* gcc.dg/sarif-output/missing-semicolon.py: ...this.
* gcc.dg/sarif-output/missing-semicolon.c: Update for script renaming.
* gcc.dg/sarif-output/test-no-diagnostics.py: Rename to...
* gcc.dg/sarif-output/no-diagnostics.py: ...this.
* gcc.dg/sarif-output/no-diagnostics.c: Update for script renaming.
* gcc.dg/sarif-output/test-werror.py: Rename to...
* gcc.dg/sarif-output/werror.py: ...this.
* gcc.dg/sarif-output/werror.c: Update for script renaming.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

testcase: Add testcase for PR 117330 [PR117330]

This testcase was causing an ICE during vectorization
due to r15-4695-gd17e672ce82e69 but was fixed with
r15-4713-g0942bb85fc5573.

Pushed as obvious after a quick test on x86_64-linux-gnu to
make sure the testcase passes.

PR tree-optimization/117330

gcc/testsuite/ChangeLog:

* gcc.dg/torture/pr117330-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

testsuite: Require atomic operations for pr47333_0

Since the test uses __sync_fetch_and_add, add a requirement for
target to support atomic operations on int and long types.

This fixes a spurious test failure on pru-unknown-elf, which lacks
atomic ops. The test still passes on x86_64-linux-gnu.

gcc/testsuite/ChangeLog:

* g++.dg/lto/pr47333_0.C: Require target that supports atomic
operations on int and long types.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>

gcc: fix 'statements' comment typo

gcc/ChangeLog:

* opts-common.cc (prune_options): Fix typo.

testsuite: add testcase for fixed PR107467

PR107467 ended up being fixed by the fix for PR115110, but let's
add the testcase on top.

gcc/testsuite/ChangeLog:
PR tree-optimization/107467
PR middle-end/115110

* g++.dg/lto/pr107467_0.C: New test.

Fix bitwise_or logic for prange.

Set non-zero only if at least one of the two operands does not contain zero.

* range-op-ptr.cc (operator_bitwise_or::fold_range): Fix logic
for setting nonzero.

aarch64: Use implementation namespace for vxarq_u64 immediate argument

Looks like this immediate variable was missed out when I last fixed the
namespace issues in arm_neon.h.  Fixed in the obvious manner.

Bootstrapped and tested on aarch64-none-linux-gnu.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/arm_neon.h (vxarq_u64): Rename imm6 to __imm6.

libstdc++: Fix tests for std::vector range operations

The commit I pushed was not the one I'd tested, so it had older versions
of the tests, with bugs that I'd already fixed locally. This commit has
the fixed tests that I'd intended to push in the first place.

libstdc++-v3/ChangeLog:

* testsuite/23_containers/vector/bool/cons/from_range.cc: Use
dg-do run instead of compile.
(test_ranges): Use do_test instead of do_test_a for rvalue
range.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/bool/modifiers/assign/assign_range.cc:
Use dg-do run instead of compile.
(do_test): Use same test logic for vector<bool> as for primary
template.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/bool/modifiers/insert/append_range.cc:
Use dg-do run instead of compile.
(test_ranges): Use do_test instead of do_test_a for rvalue
range.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/bool/modifiers/insert/insert_range.cc:
Use dg-do run instead of compile.
(do_test): Fix incorrect function arguments to match intended
results.
(test_ranges): Use do_test instead of do_test_a for rvalue
range.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/cons/from_range.cc: Use dg-do
run instead of compile.
(test_ranges): Fix ill-formed call to do_test.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/modifiers/append_range.cc:
Use dg-do run instead of compile.
(test_constexpr): Likewise.
* testsuite/23_containers/vector/modifiers/assign/assign_range.cc:
Use dg-do run instead of compile.
(do_test): Do not reuse input ranges.
(test_constexpr): Call function template instead of just
instantiating it.
* testsuite/23_containers/vector/modifiers/insert/insert_range.cc:
Use dg-do run instead of compile.
(do_test): Fix incorrect function arguments to match intended
results.
(test_constexpr): Call function template instead of just
instantiating it.

build: update bootstrap req to C++14

We moved to a bootstrap requirement of C++11 in GCC 11, 8 years after
support was stable in GCC 4.8.

It is now 8 years since C++14 was the default mode in GCC 6 (and 9 years
since support was complete in GCC 5), and we have a few bits of optional
C++14 code in the compiler, so it seems a good time to update the bootstrap
requirement again.

The big benefit of the change is the greater constexpr power, but C++14 also
added variable templates, generic lambdas, lambda init-capture, binary
literals, and numeric literal digit separators.

C++14 was feature-complete in GCC 5, and became the default in GCC 6.  5.4.0
bootstraps trunk correctly; trunk stage1 built with 5.3.0 breaks in
eh_data_format_name due to PR69995.

gcc/ChangeLog:

* doc/install.texi (Prerequisites): Update to C++14.

ChangeLog:

* configure.ac: Update requirement to C++14.
* configure: Regenerate.

[target/117316] Fix initializer for riscv code alignment handling

The construct used for initializing the code alignments in a recent change is
causing bootstrap problems on riscv64 as seen in the referenced bugzilla.

This patch adjusts the initializer by pushing the NULL down into each uarch
clause.  Bootstrapped on riscv64, regression test in flight, but given
bootstrap is broken it seemed advisable to move this forward now.

I'm so much looking forward to the day when we have performant hardware for
bootstrap testing...  Sigh.

Anyway, bootstrapped and installing on the trunk.

PR target/117316
gcc/
* config/riscv/riscv.cc (riscv_tune_param): Drop initializer.
(*_tune_info): Add initializers for code alignments.

tree-optimization/117307 - STMT_VINFO_SLP_VECT_ONLY mis-computation

STMT_VINFO_SLP_VECT_ONLY isn't properly computed as union of all
group members and when the group is later split due to duplicates
not all sub-groups inherit the flag.

PR tree-optimization/117307
* tree-vect-data-refs.cc (vect_analyze_data_ref_accesses):
Properly compute STMT_VINFO_SLP_VECT_ONLY.  Set it on all
parts of a split group.

* gcc.dg/vect/pr117307.c: New testcase.

tree-core.h (omp_clause_code): Comments regarding range checks for OMP_CLAUSE_...

gcc/ChangeLog:

* tree-core.h (enum omp_clause_code): Add comments to cross ref to
OMP_CLAUSE_DECL etc. and mark the ranges used in the range checks.

vec-lowering: Fix ABSU lowering [PR111285]

ABSU_EXPR lowering incorrectly used the resulting type
for the new expression but in the case of ABSU the resulting
type is an unsigned type and with ABSU is folded away. The fix
is to use a signed type for the expression instead.

Bootstrapped and tested on x86_64-linux-gnu.

PR middle-end/111285

gcc/ChangeLog:

* tree-vect-generic.cc (do_unop): Use a signed type for the
operand if the operation was ABSU_EXPR.

gcc/testsuite/ChangeLog:

* g++.dg/torture/vect-absu-1.C: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

phiopt: Move check for maybe_undef_p slightly earlier

This moves the check for maybe_undef_p in match_simplify_replacement
slightly earlier before figuring out the true/false arg using arg0/arg1
instead.
In most cases this is no difference in compile time; just in the case
there is an undef in the args there would be a slight compile time
improvement as there is no reason to figure out which arg corresponds
to the true/false side of the conditional.

Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

* tree-ssa-phiopt.cc (match_simplify_replacement): Move
check for maybe_undef_p earlier.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

Remove code in vectorizer pattern recog relying on vec_cond{u,eq,}

With the intent to rely on vec_cond_mask and vec_cmp patterns
comparisons do not need rewriting into COND_EXPRs that eventually
combine to vec_cond{u,eq,}.

* tree-vect-patterns.cc (check_bool_pattern): For comparisons
we do nothing if we can expand them or we can't replace them
with a ? -1 : 0 condition - but the latter would require
expanding the comparison which we proved we can't.  So do
nothing, aka not think vec_cond{u,eq,} will save us.

RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

This patch fixes following ICE:

test.c: In function 'func':
test.c:37:24: internal compiler error: Segmentation fault
   37 |     vfloat16mf2_t vc = __riscv_vlmul_trunc_v_f16m1_f16mf2(vb);
      |                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The root cause is that vlmul_trunc has a null return value.
gimple_call <__riscv_vlmul_trunc_v_f16m1_f16mf2, NULL, vb_13>
                                                 ^^^

Passed the rv64gcv_zvfh regression test.

Singed-off-by: Li Xu <xuli1@eswincomputing.com>
PR target/117286

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Do not expand NULL return.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr117286.c: New test.

gcc.target/i386/pr53533-[13].c: Adjust assembly scan

Before

1089d083117 Simplify (B * v + C) * D -> BD* v + CD when B,C,D are all INTEGER_CST.

the loop was

.L2:
movl (%rdi,%rdx), %eax
addl $12345, %eax
imull $-1564285888, %eax, %eax
leal -333519936(%rax), %eax
movl %eax, (%rsi,%rdx)
addq $4, %rdx
cmpq $1024, %rdx
jne .L2

There were 1 addl and 1 leal. 1 addq was to update the loop counter.  The
optimized loop is

.L2:
imull $-1564285888, (%rdi,%rax), %edx
subl $1269844480, %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $1024, %rax
jne .L2

1 addl is changed to subl and leal is removed. Adjust assembly scan to
check for 1 subl and 1 addl/addq as well as lea removal.

* gcc.target/i386/pr53533-1.c: Adjust assembly scan.
* gcc.target/i386/pr53533-3.c: Likewise.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

Daily bump.

libstdc++: Add P1206R7 from_range members to std::vector [PR111055]

This is another piece of P1206R7, adding new members to std::vector and
std::vector<bool>.

The __uninitialized_copy_a extension needs to be enhanced to support
passing non-common ranges (i.e. a sentinel that is a different type from
the iterator) and move-only input iterators.

libstdc++-v3/ChangeLog:

PR libstdc++/111055
* include/bits/ranges_base.h (__container_compatible_range): New
concept.
* include/bits/stl_bvector.h (vector(from_range, R&&, const Alloc&))
(assign_range, insert_range, append_range): Define.
* include/bits/stl_uninitialized.h (__do_uninit_copy): Support
non-common ranges.
(__uninitialized_copy_a): Likewise.
* include/bits/stl_vector.h (_Vector_base::_M_append_range_to):
New function.
(_Vector_base::_M_append_range): Likewise.
(vector(from_range, R&&, const Alloc&), assign_range): Define.
(append_range): Define.
(insert_range): Declare.
* include/debug/vector (vector(from_range, R&&, const Alloc&))
(assign_range, insert_range, append_range): Define.
* include/bits/vector.tcc (insert_range): Define.
* testsuite/util/testsuite_iterators.h (input_iterator_wrapper_rval):
New class template.
* testsuite/23_containers/vector/bool/cons/from_range.cc: New test.
* testsuite/23_containers/vector/bool/modifiers/assign/assign_range.cc:
New test.
* testsuite/23_containers/vector/bool/modifiers/insert/append_range.cc:
New test.
* testsuite/23_containers/vector/bool/modifiers/insert/insert_range.cc:
New test.
* testsuite/23_containers/vector/cons/from_range.cc: New test.
* testsuite/23_containers/vector/modifiers/append_range.cc: New test.
* testsuite/23_containers/vector/modifiers/assign/assign_range.cc:
New test.
* testsuite/23_containers/vector/modifiers/insert/insert_range.cc:
New test.

Reviewed-by: Patrick Palka <ppalka@redhat.com>

libstdc++: Fix std::vector<bool>::emplace to forward parameter

If the parameter is not lvalue-convertible to bool then the current code
will fail to compile. The parameter should be forwarded to restore the
original value category.

libstdc++-v3/ChangeLog:

* include/bits/stl_bvector.h (emplace_back, emplace): Forward
parameter pack to preserve value category.
* testsuite/23_containers/vector/bool/emplace_rvalue.cc: New
test.

arm: Support -mfdpic for more targets

Targets that are not arm*-*-uclinuxfdpiceabi can use -S -mfdpic, but -c
-mfdpic does not pass --fdpic to gas.  This is an unnecessary
restriction.  Just define the ASM_SPEC in bpabi.h.

Additionally, use armelf[b]_linux_fdpiceabi emulations for -mfdpic in
linux-eabi.h.  This will allow a future musl fdpic port to use the
desired BFD emulation.

gcc/ChangeLog:

* config/arm/bpabi.h (TARGET_FDPIC_ASM_SPEC): Transform -mfdpic.
* config/arm/linux-eabi.h (TARGET_FDPIC_LINKER_EMULATION): Define.
(SUBTARGET_EXTRA_LINK_SPEC): Use TARGET_FDPIC_LINKER_EMULATION
if -mfdpic.

xtensa: Define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P target hook

In commit bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0 ("gcc: xtensa: reorder
movsi_internal patterns for better code generation during LRA"),  the
instruction order in "movsi_internal" MD definition was changed to make LRA
use load/store instructions with larger memory address displacements, but as
a side effect, it now uses the larger displacements (ie., the larger
instructions) even outside of reload operations.

The underlying problem is that LRA assumes by default that there is only one
maximal legitimate displacement for the same address structure, meaning that
it has no choice but to use the first load/store instruction it finds.

To fix this, define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook to always
return true.

gcc/ChangeLog:

* config/xtensa/xtensa.cc (TARGET_DIFFERENT_ADDR_DISPLACEMENT_P):
Add new target hook to always return true.
* config/xtensa/xtensa.md (movsi_internal):
Revert the previous changes.

genmatch: Add selftests to genmatch for diag_vfprintf

The following patch adds selftests to genmatch to verify the new printing
routine there.
So that I can rely on HAVE_DECL_FMEMOPEN (host test), the tests are done
solely in stage2+ where we link the host libcpp etc. to genmatch.
The tests have been adjusted from pretty-print.cc (test_pp_format),
and I've added to that function two new tests because I've noticed nothing
was testing the %M$.*N$s etc. format specifiers.

2024-10-27  Jakub Jelinek  <jakub@redhat.com>

* configure.ac (gcc_AC_CHECK_DECLS): Add fmemopen.
* configure: Regenerate.
* config.in: Regenerate.
* Makefile.in (build/genmatch.o): Add -DGENMATCH_SELFTESTS to
BUILD_CPPFLAGS for stage2+ genmatch.
* genmatch.cc (test_diag_vfprintf, genmatch_diag_selftests): New
functions.
(main): Call genmatch_diag_selftests.
* pretty-print.cc (test_pp_format): Add two tests, one for %M$.*N$s
and one for %M$.Ns.

c-family: -Wleading-whitespace= argument spelling

On Thu, Oct 24, 2024 at 03:33:25PM -0400, Eric Gallager wrote:
> On Thu, Oct 24, 2024 at 4:17 AM Jakub Jelinek <jakub@redhat.com> wrote:
> > I've tried to build stage3 with
> > -Wleading-whitespace=blanks -Wtrailing-whitespace=blank -Wno-error=leading-whitespace=blanks -Wno-error=trailing-whitespace=blank
>
> So wait, it's "blanks" (plural) when it's leading, but "blank"
> (singular) when it's trailing? That inconsistency bothers me...

I've mentioned it already in
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/664664.html
Citing that here:
    Not sure about the kinds for the option, given -Wleading-whitespace=
    uses plural and this option singular and -Wleading-whitespace= spaces
    means literally just ' ' characters, while space in
    -Wtrailing-whitespace= was ' ', '\t', '\v' and '\f'; so category;
    perhaps just use any and blanks?
Other preferences?

Here is a patch to do the blank->blanks and space->any changes.

2024-10-27  Jakub Jelinek  <jakub@redhat.com>

gcc/
* doc/invoke.texi (Wtrailing-whitespace=): Change
blank argument to blanks and space argument to any.
gcc/c-family/
* c.opt (warn_trailing_whitespace_kind): Change blank
to blanks and space to any.
gcc/testsuite/
* c-c++-common/cpp/Wtrailing-whitespace-2.c: Use
-Wtrailing-whitespace=blanks rather than -Wtrailing-whitespace=blank.
* c-c++-common/cpp/Wtrailing-whitespace-3.c: Use
-Wtrailing-whitespace=any rather than -Wtrailing-whitespace=space.
* c-c++-common/cpp/Wtrailing-whitespace-7.c: Use
-Wtrailing-whitespace=blanks rather than -Wtrailing-whitespace=blank.
* c-c++-common/cpp/Wtrailing-whitespace-8.c: Use
-Wtrailing-whitespace=any rather than -Wtrailing-whitespace=space.

testsuite: Fix up gcc.dg/vec-perm-lower.c test

On Tue, Oct 15, 2024 at 12:45:35PM +0000, Tamar Christina wrote:
> I'll write a gimple one and commit with this then.

The new test FAILs on i686-linux, with the usual

FAIL: gcc.dg/vec-perm-lower.c (test for excess errors)
Excess errors:
.../gcc/testsuite/gcc.dg/vec-perm-lower.c:9:1: warning: SSE vector return without SSE enabled changes the ABI [-Wpsabi]
.../gcc/testsuite/gcc.dg/vec-perm-lower.c:8:1: warning: MMX vector argument without MMX enabled changes the ABI [-Wpsabi]

The following patch fixes that.
Tested on x86_64-linux with
make check-gcc RUNTESTFLAGS='--target_board=unix/\{-m32,-m32/-mno-sse/-mno-mmx,-m64\} dg.exp=vec-perm-lower.c'
which previously FAILed, now PASSes, ok for trunk?

2024-10-27  Jakub Jelinek  <jakub@redhat.com>

* gcc.dg/vec-perm-lower.c: Add -Wno-psabi to dg-options.

Fortran: Fix regressions with intent(out) class[PR115070, PR115348].

2024-10-27  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/115070
PR fortran/115348
* trans-expr.cc (gfc_trans_class_init_assign): If all the
components of the default initializer are null for a scalar,
build an empty statement to prevent prior declarations from
disappearing.

gcc/testsuite/
PR fortran/115070
* gfortran.dg/pr115070.f90: New test.

PR fortran/115348
* gfortran.dg/pr115348.f90: New test.

testsuite: Sanitize pacbti test cases for Cortex-M

Some of the test cases were scanning for "bti", but it would,
incorrectly, match the ".arch_extenssion pacbti".

gcc/testsuite/ChangeLog:

* gcc.target/arm/bti-1.c: Check for asm instructions starting
with a tab.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/pac-1.c: Likewise.
* gcc.target/arm/pac-2.c: Likewise.
* gcc.target/arm/pac-3.c: Likewise.
* gcc.target/arm/pac-4.c: Likewise.
* gcc.target/arm/pac-6.c: Likewise.
* gcc.target/arm/pac-7.c: Likewise.
* gcc.target/arm/pac-8.c: Likewise.
* gcc.target/arm/pac-9.c: Likewise.
* gcc.target/arm/pac-10.c: Likewise.
* gcc.target/arm/pac-11.c: Likewise.
* gcc.target/arm/pac-15.c: Likewise.
* gcc.target/arm/pac-sibcall.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Co-authored-by: Yvan ROUX <yvan.roux@foss.st.com>

Daily bump.

doc, fortran: Add a missing menu item.

The changes in r15-4697-g4727bfb37701 omit a menu entry which causes a
bootstrap fail when Frotran is included for at least makeinfo 6.7.
Fixed thus.

gcc/fortran/ChangeLog:

* intrinsic.texi: Add menu item for UINT.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>

tree: Mark PAREN_EXPR and VEC_DUPLICATE_EXPR as non-trapping [PR117234]

While looking to fix a possible trapping issue in PHI-OPT's factor,
I noticed that some tree codes could be marked as trapping even
though they don't have a possibility to trap. In the case of PAREN_EXPR,
it is basically a nop except when it comes to association across it so
it can't trap.
In the case of VEC_DUPLICATE_EXPR, it is similar to a CONSTRUCTOR, so it
can't trap.

This fixes those 2 issues and adds 4 testcases, 2 which are specific to aarch64
since the only way to get a VEC_DUPLICATE_EXPR is to use intrinsics currently.

Build and tested for aarch64-linux-gnu.

PR tree-optimization/117234

gcc/ChangeLog:

* tree-eh.cc (operation_could_trap_helper_p): Treat
PAREN_EXPR and VEC_DUPLICATE_EXPR like constructing
expressions.

gcc/testsuite/ChangeLog:

* g++.dg/eh/noncall-fp-1.C: New test.
* g++.target/aarch64/sve/noncall-eh-fp-1.C: New test.
* gcc.dg/tree-ssa/trapping-1.c: New test.
* gcc.target/aarch64/sve/trapping-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

Add UNSIGNED for intrinsics.

gcc/fortran/ChangeLog:

* gfortran.texi: Correct reference to make clear that UNSIGNED
will not be part of F202Y.
Other clarifications.
Extend table of intrinsics, add links.
* intrinsic.texi: Add descriptions for UNSIGNED arguments.
* invoke.texi: Add anchor for -funsigned.

Fix old glitch in the GNAT Reference Manual

gcc/ada
PR ada/62122
* doc/gnat_rm/implementation_defined_attributes.rst
(Unrestricted_Access): Remove null exclusion.
* gnat_rm.texi: Regenerate.

Assert finished vectorizer pattern COND_EXPR transition

The following places a few strathegic asserts so we do not end up
with COND_EXPRs with a comparison as the first operand during
vectorization.

* tree-vect-slp.cc (vect_get_operand_map): Mark
COMPARISON_CLASS_P COND_EXPR condition path unreachable.
* tree-vect-stmts.cc (vect_is_simple_use): Likewise.
(vectorizable_condition): Assert the COND_EXPR condition isn't
COMPARISON_CLASS_P.

Finish vectorizer pattern proper COND_EXPR transition

This fixes up vect_recog_ctz_ffs_pattern.

* tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Create
a separate pattern stmt for the comparison in the generated
COND_EXPR.

Finish vectorizer pattern proper COND_EXPR transition

The following tries to finish building proper GIMPLE COND_EXPRs
in vectorizer pattern recognition.

* tree-vect-patterns.cc (vect_recog_divmod_pattern): Build
separate comparion pattern for the condition of a COND_EXPR
pattern.

testsuite: fixup tbaa test again

Test was broken until r15-4684-g2d1d6be00257c5 which made it actually
run and r15-4685-g091e45b4e97d1e which applied fixes other than the
trivial rename.

But more is needed: this gets the test working properly in terms of scanning
the dump and handling the interaction w/ LTO with not producing an executable
(did try ltrans scan but that didn't work either).

Unfortunately, the test seems to fail for me on godbolt even going back to
GCC 7.1 or thereabouts, hence XFAIL. However, if I revert r9-3870-g2a98b4bfc3d952,
I do get an ICE in fld_incomplete_type_of -- because we do far more checking
with LTO now on (in)complete types. And reverting it on releases/gcc-9 actually
makes it give 0.

In summary: fix the test fully so it really does run and we get a check
for ICEing at least, and mark the dg-final scan as XFAIL so Honza can
comment on that.

gcc/testsuite/ChangeLog:
PR testsuite/117299

* gcc.dg/lto/tbaa_0.c: Move to...
* gcc.dg/tbaa.c: ...here.

Daily bump.

libbacktrace: recognize new Mach-O DWARF sections

Patch from Pavel Safonov.

These sections are used on macOS Sequoia.

Fixes https://github.com/ianlancetaylor/libbacktrace/issues/136

* macho.c (dwarf_section_names): Add __debug_addr and
__debug_line_str.

simplify-rtx: Handle `a != 0 ? -a : 0` [PR58195]

The gimple (and generic) levels have this optmization since r12-2041-g7d6979197274a662da7bdc5.
It seems like a good idea to add a similar one to rtl just in case it is not caught at the
gimple level.

Note the loop case in csel-neg-1.c is not handled at the gimple level (even with phiopt turned back on),
this is because of casts to avoid signed integer overflow; a patch to fix this at the gimple level will be
submitted seperately.

Changes since v1:
* v2: Use `CONST0_RTX (mode)` instead of const0_rtx. Add csel-neg-2.c for float testcase which now passes.

Build and tested for aarch64-linux-gnu.

PR rtl-optimization/58195

gcc/ChangeLog:

* simplify-rtx.cc (simplify_context::simplify_ternary_operation): Handle
`a != 0 ? -a : 0` and `a == 0 ? 0 : -a`.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/csel-neg-1.c: New test.
* gcc.target/aarch64/csel-neg-2.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

testsuite: lto: fix pr47333 test

This failure was hidden until we started to run the test by fixing
the filename earlier: ignore -Wtemplate-body using a pragma like
e.g. g++.dg/lto/20101010-1_0.C does because lto.exp doesn't support
dg-additional-options.

gcc/testsuite/ChangeLog:
PR lto/47333

* g++.dg/lto/pr47333_0.C: Ignore -Wtemplate-body.

testsuite: lto: fix pr62026 test

This failure was hidden until we started to run the test by fixing
the filename earlier: pass -Wno-return-type.

gcc/testsuite/ChangeLog:
PR lto/62026

* g++.dg/lto/pr62026_0.C: Pass -Wno-return-type.

testsuite: lto: fix pr95677 test

These failures were hidden until we started to run the test by fixing
the filename earlier: use dg-lto directives.

gcc/testsuite/ChangeLog:
PR c++/95677

* g++.dg/lto/pr95677_0.C: Use dg-lto-*.

testsuite: lto: fix tbaa_0 test

These failures were hidden until we started to run the test by fixing
the filename earlier: use dg-lto directives, pass -std=gnu89 for
implicit-int, and use -flto-partition=none like c-c++-common/hwasan/builtin-special-handling.c.

gcc/testsuite/ChangeLog:

* gcc.dg/lto/tbaa_0.c: Use dg-lto directives, pass -std=gnu89, and
use -flto-partition=none.

testsuite: lto: rename tbaa-1 test

This was being ignored previously. Rename it per README.

gcc/testsuite/ChangeLog:

* gcc.dg/lto/tbaa-1.c: Move to...
* gcc.dg/lto/tbaa_0.c: ...here.

testsuite: lto: rename pr47333 test

This was being ignored previously. Rename it per README.

gcc/testsuite/ChangeLog:
PR target/47333

* g++.dg/lto/pr47333.C: Move to...
* g++.dg/lto/pr47333_0.C: ...here.

testsuite: lto: rename pr62026 test

This was being ignored previously. Rename it per README.

gcc/testsuite/ChangeLog:
PR lto/62026

* g++.dg/lto/pr62026.C: Move to...
* g++.dg/lto/pr62026_0.C: ...here.

testsuite: lto: rename pr95677 test

This was being ignored previously. Rename it per README.

gcc/testsuite/ChangeLog:
PR c++/95677

* g++.dg/lto/pr95677.C: Move to...
* g++.dg/lto/pr95677_0.C: ...here.

toplevel: Error out if using --disable-libstdcxx with bootstrap [PR105474]

Bootstrapping and using --disable-libstdcxx will cause a build failure deep in compiling
stage2 so instead error out early in the toplevel configure so it is more user friendly.

Bootstrapped and tested on x86_64-linux-gnu.
Also made sure --disable-libstdcxx without --disable-bootstrap failed.

PR bootstrap/105474

ChangeLog:

* configure: Regenerate.
* configure.ac: Error out if libstdc++ is not enabled
with bootstrapping.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

aarch64: Support multiple variants including up to 3

On some of the Qualcomm's SoC that includes oryon-1 core, the variant
will be different on the cores due to big.little config. Though
the difference between big and little is not significant enough
to have seperate cost/scheduling models for them and the feature set
is the same across all variants.

Also on some SoCs, there are 3 variants of the core, big.middle.little
so this increases the support there for up to 3 cores and 3 variants
in the original parsing loop but it does not change the support for max
of 2 different cores.

After this patch and the patch that adds oryon-1, -mcpu=native works
on the SoCs I am working with.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

* config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Support
3 cores and 3 variants. If there is one core but multiple variant,
then treat the variant as being all.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cpunative/info_25: New file.
* gcc.target/aarch64/cpunative/info_26: New file.
* gcc.target/aarch64/cpunative/native_cpu_25.c: New test.
* gcc.target/aarch64/cpunative/native_cpu_26.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

AArch64: Add more accurate constraint [PR117292]

As shown in the PR, reload may only check the constraint in some cases and
and not check the predicate is still valid for the resulting instruction.
To fix the issue, add a new constraint which matches the predicate exactly.

gcc/ChangeLog:
PR target/117292
* config/aarch64/aarch64-simd.md (xor<mode>3<vczle><vczbe>): Use
'De' constraint.
* config/aarch64/constraints.md (De): Add new constraint.

gcc/testsuite/ChangeLog:
PR target/117292
* gcc.target/aarch64/sve/single_5.c: Remove xfails.
* gcc.target/aarch64/pr117292.c: New test.

Fortran: Fix ICE with structure constructor in data statement [PR79685]

2024-10-25  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/79685
* decl.cc (match_data_constant): Find the symtree instead of
the symbol so the use renamed symbols are found. Pass this and
the derived type to gfc_match_structure_constructor.
* match.h: Update prototype of gfc_match_structure_contructor.
* primary.cc (gfc_match_structure_constructor): Remove call to
gfc_get_ha_sym_tree and use caller supplied symtree instead.

gcc/testsuite/
PR fortran/79685
* gfortran.dg/use_rename_13.f90: New test.

testsuite: add testcase for fixed PR115933

gcc/testsuite/ChangeLog:
PR rtl-optimization/115933

* gcc.dg/pr115933.c: New test.

aarch64: Add mfloat vreinterpret intrinsics

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.cc (MODE_d_mf8): New.
(MODE_q_mf8): New.
(QUAL_mf8): New.
(VREINTERPRET_BUILTINS1): Add mf8 entry.
(VREINTERPRET_BUILTINS): Ditto.
(VREINTERPRETQ_BUILTINS1): Ditto.
(VREINTERPRETQ_BUILTINS): Ditto.
(aarch64_lookup_simd_type_in_table): Match modal_float bit

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/advsimd-intrinsics/mf8-reinterpret.c: New test.

aarch64: Add support for mfloat8x{8|16}_t types

gcc/ChangeLog:

* config/aarch64/aarch64-builtins.cc
(aarch64_init_simd_builtin_types): Initialise FP8 simd types.
* config/aarch64/aarch64-builtins.h
(enum aarch64_type_qualifiers): Add qualifier_modal_float bit.
* config/aarch64/aarch64-simd-builtin-types.def:
Add Mfloat8x{8|16}_t types.
* config/aarch64/arm_neon.h: Add mfloat8x{8|16}_t typedefs.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/movv16qi_2.c: Test mfloat as well.
* gcc.target/aarch64/movv16qi_3.c: Ditto.
* gcc.target/aarch64/movv2x16qi_1.c: Ditto.
* gcc.target/aarch64/movv3x16qi_1.c: Ditto.
* gcc.target/aarch64/movv4x16qi_1.c: Ditto.
* gcc.target/aarch64/movv8qi_2.c: Ditto.
* gcc.target/aarch64/movv8qi_3.c: Ditto.
* gcc.target/aarch64/mfloat-init-1.c: New test.

match.pd: Add std::pow folding optimizations.

This patch adds the following two simplifications in match.pd for
POW_ALL and POWI:
- pow (1.0/x, y) to pow (x, -y), avoiding the division
- pow (0.0, x) to 0.0, avoiding the call to pow.
The patterns are guarded by flag_unsafe_math_optimizations,
!flag_trapping_math, and !HONOR_INFINITIES.
The POW_ALL patterns are also gated under !flag_errno_math.
The second pattern is also guarded by !HONOR_NANS and
!HONOR_SIGNED_ZEROS.

Tests were added to confirm the application of the transform for
builtins pow, powf, powl, powi, powif, powil, and powf16.

The patch was bootstrapped and regtested on aarch64-linux-gnu and
x86_64-linux-gnu, no regression.
OK for mainline?

Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>
gcc/
* match.pd: Fold pow (1.0/x, y) -> pow (x, -y) and
pow (0.0, x) -> 0.0.

gcc/testsuite/
* gcc.dg/tree-ssa/pow_fold_1.c: New test.

Match: Simplify branch form 3 of unsigned SAT_ADD into branchless

There are sorts of forms for the unsigned SAT_ADD.  Some of them are
complicated while others are cheap.  This patch would like to simplify
the complicated form into the cheap ones.  For example as below:

From the form 3 (branch):
  SAT_U_ADD = (X + Y) >= x ? (X + Y) : -1.

To (branchless):
  SAT_U_ADD = (X + Y) | - ((X + Y) < X).

  #define T uint8_t

  T sat_add_u_1 (T x, T y)
  {
    return (T)(x + y) >= x ? (x + y) : -1;
  }

Before this patch:
   1   │ uint8_t sat_add_u_1 (uint8_t x, uint8_t y)
   2   │ {
   3   │   uint8_t D.2809;
   4   │
   5   │   _1 = x + y;
   6   │   if (x <= _1) goto <D.2810>; else goto <D.2811>;
   7   │   <D.2810>:
   8   │   D.2809 = x + y;
   9   │   goto <D.2812>;
  10   │   <D.2811>:
  11   │   D.2809 = 255;
  12   │   <D.2812>:
  13   │   return D.2809;
  14   │ }

After this patch:
   1   │ uint8_t sat_add_u_1 (uint8_t x, uint8_t y)
   2   │ {
   3   │   uint8_t D.2809;
   4   │
   5   │   _1 = x + y;
   6   │   _2 = x + y;
   7   │   _3 = x > _2;
   8   │   _4 = (unsigned char) _3;
   9   │   _5 = -_4;
  10   │   D.2809 = _1 | _5;
  11   │   return D.2809;
  12   │ }

The simplify doesn't need to check if target support the SAT_ADD, it
is somehow the optimization in gimple level.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Remove unsigned branch form 3 for SAT_ADD, and
add simplify to branchless instead.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/sat_u_add-simplify-1-u16.c: New test.
* gcc.dg/tree-ssa/sat_u_add-simplify-1-u32.c: New test.
* gcc.dg/tree-ssa/sat_u_add-simplify-1-u64.c: New test.
* gcc.dg/tree-ssa/sat_u_add-simplify-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

Assorted --disable-checking fixes [PR117249]

We have currently 3 different definitions of gcc_assert macro, one used most
of the time (unless --disable-checking) which evaluates the condition at
runtime and also checks it at runtime, then one for --disable-checking GCC 4.5+
which looks like
((void)(UNLIKELY (!(EXPR)) ? __builtin_unreachable (), 0 : 0))
and a fallback one
((void)(0 && (EXPR)))
Now, the last one actually doesn't evaluate any of the side-effects in the
argument, just quiets up unused var/parameter warnings.
I've tried to replace the middle definition with
({ [[assume (EXPR)]]; (void) 0; })
for compilers which support assume attribute and statement expressions
(surprisingly quite a few spots use gcc_assert inside of comma expressions),
but ran into PR117287, so for now such a change isn't being proposed.

The following patch attempts to move important side-effects from gcc_assert
arguments.

Bootstrapped/regtested on x86_64-linux and i686-linux with normal
--enable-checking=yes,rtl,extra, plus additionally I've attempted to do
x86_64-linux bootstrap with --disable-checking and gcc_assert changed to the
((void)(0 && (EXPR)))
version when --disable-checking.  That version ran into spurious middle-end
warnings
../../gcc/../include/libiberty.h:733:36: error: argument to ‘alloca’ is too large [-Werror=alloca-larger-than=]
../../gcc/tree-ssa-reassoc.cc:5659:20: note: in expansion of macro ‘XALLOCAVEC’
  int op_num = ops.length ();
  int op_normal_num = op_num;
  gcc_assert (op_num > 0);
  int stmt_num = op_num - 1;
  gimple **stmts = XALLOCAVEC (gimple *, stmt_num);
where we have gcc_assert exactly to work-around middle-end warnings.
Guess I'd need to also disable -Werror for this experiment, which actually
isn't a problem with unmodified system.h, because even for
--disable-checking we use the __builtin_unreachable at least in
stage2/stage3 and so the warnings aren't emitted, and even if it used
[[assume ()]]; it would work too because in stage2/stage3 we could again
rely on assume and statement expression support.

2024-10-25  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/117249
* tree-ssa-structalias.cc (insert_vi_for_tree): Move put calls out of
gcc_assert.
* lto-cgraph.cc (lto_symtab_encoder_delete_node): Likewise.
* gimple-ssa-strength-reduction.cc (get_alternative_base,
add_cand_for_stmt): Likewise.
* tree-eh.cc (add_stmt_to_eh_lp_fn): Likewise.
* except.cc (duplicate_eh_regions_1): Likewise.
* tree-ssa-reassoc.cc (insert_operand_rank): Likewise.
* config/nvptx/nvptx.cc (nvptx_expand_call): Use == rather than = in
gcc_assert.
* opts-common.cc (jobserver_info::disconnect): Call close outside of
gcc_assert and only check result in it.
(jobserver_info::return_token): Call write outside of gcc_assert and
only check result in it.
* genautomata.cc (output_default_latencies): Move j++ side-effect
outside of gcc_assert.
* tree-ssa-loop-ivopts.cc (get_alias_ptr_type_for_ptr_address): Use
== rather than = in gcc_assert.
* cgraph.cc (symbol_table::create_edge): Move ++edges_max_uid
side-effect outside of gcc_assert.

lto: Handle RAW_DATA_CST in compare_tree_sccs_1 [PR117201]

I've missed I need to add RAW_DATA_CST support in compare_tree_sccs_1,
because without that it considers all RAW_DATA_CSTs to be equivalent,
regardless of their length or content.

2024-10-24  Jakub Jelinek  <jakub@redhat.com>

PR lto/117201
PR lto/117288
* lto-common.cc (compare_tree_sccs_1): Handle RAW_DATA_CST.

* gcc.dg/lto/pr117201_0.c: New test.
* gcc.dg/lto/pr117288_0.c: New test.

Default expand_vec_cond_expr_p code to ERROR_MARK

As we want to transition to only vcond_mask expanders the following
makes it possible to easier distinguish queries that rely on
vcond queries for expand_vec_cond_expr_p from those of vcond_mask
by for the latter having the comparison code defaulted to ERROR_MARK.

* optabs-tree.h (expand_vec_cond_expr_p): Default the
comparison code to ERROR_MARK.
* match.pd: Remove unneded expand_vec_cond_expr_p args.
* tree-vect-generic.cc (expand_vector_condition): Likewise.
* tree-vect-loop.cc (vect_reduction_update_partial_vector_usage):
Likewise.
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Likewise.
(scan_store_can_perm_p): Likewise.
(vectorizable_condition): Likewise.

testsuite: Generalise tree-ssa/shifts-3.c regexp

My recent gcc.dg/tree-ssa/shifts-3.c test failed on arm-linux-gnu
because it used widen_mult_expr to do a multiplication on chars.
This patch generalises the regexp in the same way as for f3.

gcc/testsuite/
* gcc.dg/tree-ssa/shifts-3.c: Accept widen_mult for f2 too.

Add regression test

gcc/testsuite
PR ada/116551
* gnat.dg/specs/vfa3.ads: New test.

libstdc++: Disable parts of new test that depend on constexpr std::string

The compile-time assertions don't work with -D_GLIBCXX_USE_CXX11_ABI=0.

libstdc++-v3/ChangeLog:

* testsuite/21_strings/basic_string/operators/char/op_plus_string_view.cc:
Check __cpp_lib_constexpr_string.

libstdc++: implement concatenation of strings and string_views

This adds support for P2591R5, merged for C++26.

libstdc++-v3/ChangeLog:

* include/bits/basic_string.h: Implement the four operator+
overloads between basic_string and (types convertible to)
basic_string_view.
* include/bits/version.def: Bump the feature-testing macro.
* include/bits/version.h: Regenerate.
* testsuite/21_strings/basic_string/operators/char/op_plus_fspath_neg.cc: New test.
* testsuite/21_strings/basic_string/operators/char/op_plus_string_view.cc: New test.
* testsuite/21_strings/basic_string/operators/char/op_plus_string_view_compat.cc:
New test.

Signed-off-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>

Restrict :c to commutative ops as intended

genmatch was supposed to restrict :c to verifiable commutative
operations while leaving :C to the "I know what I'm doing" case.
The following enforces this, cleaning up parsing and amending
the commutative_op helper.  There's one pattern that needs adjustment,
the pattern optimizing fmax (x, NaN) or fmax (NaN, x) to x since
fmax isn't commutative.

* genmatch.cc (commutative_op): Add paramter to indicate whether
all compares should be considered commutative.  Handle
hypot, add_overflow and mul_overflow.
(parser::parse_expr): Simplify 'c' handling by using
commutative_op and error out when the operation is not.
* match.pd ((minmax:c @0 NaN@1) -> @0): Use :C, we know
what we are doing.

tree-optimization/117277 - remove CLOBBERs before SLP code generation

We have to remove CLOBBERs before SLP is code generated since for
store-lanes we are inserting our own CLOBBERs that we want to survive.
So the following refactors vect_transform_loop to remove unwanted
stmts first.

This resolves the gcc.target/aarch64/sve/store_lane_spill_1.c FAIL.

PR tree-optimization/117277
* tree-vect-loop.cc (vect_transform_loop): Remove CLOBBERs
and prefetches before doing any code generation.

tree-optimization/116575 - SLP masked load-lanes discovery

The following implements masked load-lane discovery for SLP.  The
challenge here is that a masked load has a full-width mask with
group-size number of elements when this becomes a masked load-lanes
instruction one mask element gates all group members.  We already
have some discovery hints in place, namely STMT_VINFO_SLP_VECT_ONLY
to guard non-uniform masks, but we need to choose a way for SLP
discovery to handle possible masked load-lanes SLP trees.

I have this time chosen to handle load-lanes discovery where we
have performed permute optimization already and conveniently got
the graph with predecessor edges built.  This is because unlike
non-masked loads masked loads with a load_permutation are never
produced by SLP discovery (because load permutation handling doesn't
handle un-permuting the mask) and thus the load-permutation lowering
which handles non-masked load-lanes discovery doesn't trigger.

With this SLP discovery for a possible masked load-lanes, thus
a masked load with uniform mask, produces a splat of a single-lane
sub-graph as the mask SLP operand.  This is a representation that
shouldn't pessimize the mask load case and allows the masked load-lanes
transform to simply elide this splat.

This fixes the aarch64-sve.exp mask_struct_load*.c testcases with
--param vect-force-slp=1

PR tree-optimization/116575
* tree-vect-slp.cc (vect_get_and_check_slp_defs): Handle
gaps, aka NULL scalar stmt.
(vect_build_slp_tree_2): Allow gaps in the middle of a
grouped mask load.  When the mask of a grouped mask load
is uniform do single-lane discovery for the mask and
insert a splat VEC_PERM_EXPR node.
(vect_optimize_slp_pass::decide_masked_load_lanes): New
function.
(vect_optimize_slp_pass::run): Call it.

Relax vect_check_scalar_mask check

When the mask is not a constant or external def there's no need to
check the scalar type, in particular with SLP and the mask being
a VEC_PERM_EXPR there isn't a scalar operand ready to check
(not one vect_is_simple_use will get you).  We later check the
vector type and reject non-mask types there.

* tree-vect-stmts.cc (vect_check_scalar_mask): Only check
the scalar type for constant or extern defs.

ada: Change scope of XUB type

An earlier patch in the "nameless" series caused a regression with
-fgnat-encodings=all.  Previously, all artificial types were emitted
in the CU scope in the DWARF, but with the patch, an "XUB" type is
emitted in the function scope.  This causes gdb lookups to erroneously
find the XUB type rather than the type that gdb expects to find.

Note that I don't know why the earlier code worked, because decl.cc
clearly sets the XUB type's context to be the current function.

This patch changes the type's context so that it is nested in a type
that is conveniently available.

gcc/ada/ChangeLog:

* gcc-interface/decl.cc (gnat_to_gnu_entity): Use gnu_fat_type as the type
context for a XUB type.