Jernej Skrabec [Sun, 9 Mar 2025 06:12:41 +0000 (07:12 +0100)]
sunxi: mmc: Improve reset procedure
Cards should always be reset and threshold set. This fixes eMMC on H616.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
[Andre: use macro-defined offsets to fix build on older SoCs] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
It turns out that checking just one write is not enough. Due to
unexplained reasons scan procedure detected double the size. By making
16 dword writes and comparisons that never happens.
New procedure is also inverted. Instead of writing two different values
to base address and some offset and then reading both and comparing
values, simplify this by writing pattern at the base address and then
search for this pattern at some offset.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Ryan Walklin <ryan@testtoast.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Sun, 9 Mar 2025 06:31:42 +0000 (07:31 +0100)]
sunxi: h616: dram: Rework size detection
Since there is quite a few possible DRAM configurations in terms of bus
width, rank and rows and columns count, size detection algorithm must be
very careful not to test combination which would be bigger than H616 is
actually capable of handling.
Ideally, we should always detect memory aliasing, even for 4 GB memory
size, which is the maximum amount of memory that H616 is capable of
handling. For this reason, we have to configure minimum amount of
supported rows when testing for columns and vice versa. This way test
code will never step out of 4 GB boundary.
While at it, check for 17 rows maximum. This aligns code with BSP DRAM
driver. There is probably no such configuration which would make sense
with 4 GB memory.
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Wed, 25 Oct 2023 23:28:44 +0000 (00:28 +0100)]
clk: sunxi: Add support for the A100/A133 CCU
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.
Add support for the CCU, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can already use the
existing binding headers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Thu, 2 Jan 2025 11:06:22 +0000 (11:06 +0000)]
spl: reorder SPL_MAX_SIZE defaults for sunxi
Reorder the Kconfig defaults for the maximum SPL size, to make the
Allwinner specific values more readable and extensible: many older SoCs
need to be limited to 32KB, so make this the last ARCH_SUNXI entry, used
as a fallback unless explicitly overridden before.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Andre Przywara [Tue, 18 Mar 2025 00:39:43 +0000 (00:39 +0000)]
sunxi: pmic_bus: Move SPL I2C addresses into Kconfig
Some of the X-Power AXP PMICs can be ordered with an alternative I2C
address, for instance an AXP717 could be shipped with address 0x34 or
with address 0x35. Similarly the AXP803 lists two possible addresses.
For DM (DT) based drivers this is no problem, but the Allwinner SPL
code relies on exactly one hardcoded address per PMIC so far.
Add a Kconfig variable that holds the I2C address used by the PMIC
accessed in the SPL, and provide the (mostly only one) supported address
as its default, for the PMICs we use. Boards using the other address
can easily set this in their defconfig.
This effectively moves the hardcoding from C code to Kconfig.
That enables to use the AXP717 on some boards with the new Allwinner
A523 chip, which use the other I2C address there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Andre Przywara [Wed, 26 Feb 2025 11:37:11 +0000 (11:37 +0000)]
sunxi: mmc: Fix T113-s3 MMC clock divider
On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
But we have still the hidden divisor of 2 in the MMC mod clock, so
need to explicitly compensate for that on those SoCs.
This leads to the actually programmed clock rate to be double compared
to before, which increases the MMC performance on those SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Liya Huang [Fri, 31 Jan 2025 01:12:43 +0000 (09:12 +0800)]
sunxi: kconfig : Make CHIP_DIP_SCAN depend on ARCH_SUNXI
The CHIP_DIP_SCAN configuration option
is relevant only to ARCH_SUNXI.
Make CHIP_DIP_SCAN dependent
on ARCH_SUNXI so that it does not show up on other goals.
Signed-off-by: Liya Huang <1425075683@qq.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Sughosh Ganu [Wed, 26 Mar 2025 16:53:36 +0000 (22:23 +0530)]
test: lmb: fix the lmb_alloc_addr() based test cases
Commit 56f186a68b3 ("lmb: check if a region can be reserved by
lmb_reserve()") fixed the lmb_reserve() and lmb_alloc_addr() API's for
some corner case scenarios, and also added corresonding test cases for
these corner cases. These tests were checking, among other things, the
lmb_alloc_addr() API. The above commit was applied to the next branch.
Subsequently, there was commit 67be24906fe
("lmb: change the return code on lmb_alloc_addr()") which was first
applied on the master branch, and subsequently got merged to next as
part of the rebase. The second commit changes the return value of the
lmb_alloc_addr() API, which now results in some of the tests added as
part of the first commit to fail. Fix those test cases.
Adam Ford [Tue, 25 Mar 2025 02:54:48 +0000 (21:54 -0500)]
imx: imx9: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX9
family to display the CPU type, temperature grade and
current operating temperature. The older file,
arch/arm/mach-imx/cpu.c, does not support i.MX9, so this config
is enabled in various IMX9 boards. Instead of having this option
enabled in every IMX9, select this driver by default for the
platform.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:47 +0000 (21:54 -0500)]
imx: imx8: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX8Q
family. When it is enabled, it acts as an alternative to
arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver
model where cpu.c does not. Imply this newer driver by default.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:46 +0000 (21:54 -0500)]
imx: imx8m: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX8M
family, and when it is enabled, it acts as an alternative to
arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver
model where cpu.c does not. Imply this newer driver by default.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:45 +0000 (21:54 -0500)]
cpu: imx8_cpu: Print Speed grade if IMX_TMU
Much of the data that is display by imx8_cpu.c is also displayed from
arch/arm/mach-imx/cpu.c, except the temperature grade and active
temperature are only displayed when SoC is an i.MX9. Since IMX9 now
implies IMX_TMU, change this to check for IMX_TMU in the same way
it's done in mach-imx/cpu.c to enable displaying this information
for any SoC with either of this config enabled.
Since additional text may appear due to this commit, remove
the extra space in the message displaying the temperature
grade.
Before:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
After:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
CPU: Industrial temperature grade (-40C to 105C) at 28C
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:44 +0000 (21:54 -0500)]
imx: imx8m: Imply IMX_TMU
If the CPU Information is displayed from imx8_cpu, it displays the
cpu temperature grade and operating temperature if CONFIG_IMX9 is
defined. This behavior is similar to what happens mach-imx/cpu.c,
except that the latter checks for IMX_THERMAL or IMX_TMU.
In preparation to make imx8_cpu act like the previous implementation
for any CPU, make IMX8M imply IMX_TMU so it will be always displayed
unless a user decides to disable it.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:43 +0000 (21:54 -0500)]
cpu: imx8_cpu: Expand get_imx_type_str list of supported CPUs
The imx8_cpu is capable of running on IMX8, IMX8M, and IMX9
families, but the CPU list is limited on the 8M variants. Expand
this list to show more variants and their respective names.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Tue, 25 Mar 2025 02:54:42 +0000 (21:54 -0500)]
imx: imx9: Imply IMX_TMU
If the CPU Information is displayed from imx8_cpu, it displays
the cpu temperature grade and operating temperature if
CONFIG_IMX9 is defined. This behavior is similar to what
happens arch/arm/mach-imx/cpu.c except that the latter
checks for CONFIG_IMX_THERMAL or CONFIG_IMX_TMU.
In preparation to make imx8_cpu act like the previous
implementation for any CPU, make IMX9 imply IMX_TMU, so
it will be always displayed unless a user decides to
disable it.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Adam Ford [Mon, 24 Mar 2025 23:27:25 +0000 (18:27 -0500)]
board: beacon: imx8mp: Fix GIC clock for Overdrive mode
There is a config option to run the PMIC at nominal voltages
which is not enabled on the i.MX8MP Beacon kit, so it the PMIC
runs at overdrive voltages. Unfortuately, the check for this
condition to set the GIC clock parent and rate is backwards from
what it should be, and accidentally sets the GIC clock to nominal
if the PMIC is in overdrive, and sets the GIC clock to overdrive
if the PMIC is in nominal. Fix this by inverting the logic on the
check.
Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit") Signed-off-by: Adam Ford <aford173@gmail.com>
As binman already creates nodes based on CONFIG_OF_LIST we don't need to
add extra nodes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # StarFIve VisionFive 2 Reviewed-by: E Shattow <e@freeshell.de>
board: starfive: spl: strip off 'starfive/' prefix
The configuration descriptions generated by binman contain the vendor
device-tree directory. Instead of adding it to all match strings just strip
it off.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
riscv: dts: no default configuration for MULTI_DTB_FIT
JH7110 boards are currently the only use case for multi DTB FIT images
on RISC-V.
Booting JH7110 systems with a VisionFive 2 device-tree used to kind of
work without causing harm to the hardware. But there is no guarantee
that this will hold true in future. So we should not rely on it.
Before the current patch series booting failed on unsupported boards due
to the lack of a device-tree in the binman generated default configuration
when reaching main U-Boot.
By not setting a default configuration booting will now fail on
unsupported boards already in SPL. This allows SPL to
continue with the next boot source for a possible recovery.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: E Shattow <e@freeshell.de>
Binman can automatically generate device-tree and configuration entries in
the FIT image based on CONFIG_MULTI_DTB_FIT if the binman node includes the
right sub-nodes.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: E Shattow <e@freeshell.de>
Yao Zi [Fri, 7 Mar 2025 17:09:22 +0000 (17:09 +0000)]
riscv: dts: cv18xx: Drop unused dummy clocks
Introduced in commit 5a4e0625ac77 ("riscv: dts: sophgo: Add ethernet
node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet
controller. As the real clock controller has been added, drop them to
clean the devicetree up.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The zkr ISA extension can be used to generate random numbers. Since RVA22
zkr is an optional ISA extension. It can be emulated by QEMU. Our RNG
driver detects if the extension is usable during driver binding. Let's
enable it by default on QEMU.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Junhui Liu [Sun, 23 Feb 2025 06:19:26 +0000 (14:19 +0800)]
riscv: dts: spacemit: Update UART compatible for k1
Update UART compatible in k1 dts to "intel,xscale-uart", introduced in
commit 2d84e1519c5b ("serial: ns16550: Add Intel XScale support")
recently, aligning dts with the upstream kernel.
Tested-by: Huan Zhou <me@per1cycle.org> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@gentoo.org>
configs: SiFive Unmatched: add 'nvme scan' to preboot
Without 'nvme scan' the ESP on the NVMe drive is not found early.
EFI variables cannot be persisted.
Hit any key to stop autoboot: 0
Cannot persist EFI variables without system partition
** Booting bootflow '<NULL>' with efi_mgr
Loading Boot0000 'mmc 0' failed
EFI boot manager: Cannot load any image
Boot failed (err=-14)
scanning bus for devices...
** Booting bootflow 'nvme#1.blk#1.bootdev.part_1' with efi
Booting /\EFI\BOOT\BOOTRISCV64.EFI
error: no suitable video mode found.
GNU GRUB version 2.12
With 'nmve scan' booting works as expected.
Hit any key to stop autoboot: 0
** Booting bootflow '<NULL>' with efi_mgr
Loading Boot0000 'mmc 0' failed
Loading Boot0001 'nvme 0' failed
Booting: nvme 1
error: no suitable video mode found.
GNU GRUB version 2.12
Reported by Yuri Zaporozhets <yuriz@vodafonemail.de> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* msm8916 gets proper sysreset and spin-table support
* The first new IPQ platform is added - the IPQ9574. The IPQ series are
used in routers. The flashing process is also documented
* mach-snapdragon gains the ability to boot with an internal FDT and
still parse memory from an externally provided one
* SC7280 gets a pinctrl driver and various clock driver improvements.
* Qualcom clock drivers will now actually return an error when
attempting
to enable a clock which isn't described.
* Qualcomm pinctrl drivers will now return an error when attempting to
configure an invalid function mux
Ilias Apalodimas [Fri, 14 Mar 2025 10:57:02 +0000 (12:57 +0200)]
lmb: change the return code on lmb_alloc_addr()
Ben reports a failure to boot the kernel on hardware that starts its
physical memory from 0x0.
The reason is that lmb_alloc_addr(), which is supposed to reserve a
specific address, takes the address as the first argument, but then also
returns the address for success or failure and treats 0 as a failure.
Since we already know the address change the prototype to return an int.
Reported-by: Ben Schneider <ben@bens.haus> Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Ben Schneider <ben@bens.haus> Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
In case ENV_IS_IN_SPI_FLASH is disabled, returning ENVL_SPI_FLASH
leads to failure to find environment driver on start up. Fix this
by testing whether ENV_IS_IN_SPI_FLASH is enabled and if not, then
return ENVL_NOWHERE instead.
Marek Vasut [Sun, 23 Mar 2025 15:58:52 +0000 (16:58 +0100)]
clk: clk-fixed-factor: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:50 +0000 (16:58 +0100)]
clk: clk-divider: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:47 +0000 (16:58 +0100)]
clk: imx: pllv3: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:45 +0000 (16:58 +0100)]
clk: imx: Convert clock-osc-* back to osc_*
Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k.
These are the clock which match clock tables in Linux. This is now
possible because the clock drivers now resolve clock names based on
clock-names DT property in the CCM DT node.
Marek Vasut [Sun, 23 Mar 2025 15:58:43 +0000 (16:58 +0100)]
clk: clk-composite: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:39 +0000 (16:58 +0100)]
clk: imx: gate2: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:37 +0000 (16:58 +0100)]
clk: clk-gate: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:33 +0000 (16:58 +0100)]
clk: clk-mux: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Marek Vasut [Sun, 23 Mar 2025 15:58:31 +0000 (16:58 +0100)]
clk: clk-mux: Fold clk_register_mux()
Neither clk_register_mux_table() nor clk_hw_register_mux_table()
are called outside of clk-mux.c , fold both into clk_register_mux().
No functional change.
Marek Vasut [Sun, 23 Mar 2025 15:58:30 +0000 (16:58 +0100)]
clk: Add clk_resolve_parent_clk()
Add clk_resolve_parent_clk() to resolve parent clock udevice name
based on clock-names DT property. This is used in SoC clock drivers
to look up the clock name in clock tables, which matches a clock
name in DT clock-names property, and convert it into udevice name
which is used by U-Boot clock framework to look up parent clock in
e.g. clk_register() using uclass_get_device_by_name(UCLASS_CLK,
parent_name, &parent);
- Allow the registration and enablement of the i.MX UART clocks via DM,
without the need of manually calling init_uart_clk().
- Remove duplicated 'mmc dev ${mmcdev}' commands.
- Rework some of the RAM related Kconfig symbols for phycore_imx8mp.
Marek Vasut [Wed, 19 Mar 2025 22:07:52 +0000 (23:07 +0100)]
usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise
it crashes. This is a result of the previous hard-coded EP setup in
drivers/usb/gadget/epautoconf.c which did special-case EP allocation
for SPL builds, and which was since converted to this callback, but
without the special-case EP allocation in SPL part.
This reinstates the SPL part in an isolated manner, only for NXP iMX
SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint.
spl_perform_fixups is redundant in the current implementation. SPLs call
dram_init during spl_enable_cache in arch/arm/mach-k3/common.c. In
U-Boot, dram_init and dram_init_banksize are automatically called in
init_sequence_f. Therefore, SPLs and U-Boot always determine the correct
RAM size. During Linux boot, fdt_fixup_memory_banks adjusts the RAM size
in the Linux device tree, ensuring correct RAM usage.
dram_init() calls get_ram_size() for the Verdin AM62, which determines
the correct RAM size through read/write operations. However, due to the
K3 bootflow placing ATF in RAM and requiring cache coherence, calling
get_ram_size() with caches enabled prevents ATF boot. Removing this call
restores ATF boot functionality.
This fixes a regression introduced in commit 4164289db882 ("board:
verdin-am62: fix missing memory fixup call") which prevents some of our
Verdin AM62 modules from booting.
Tom Rini [Sat, 15 Mar 2025 01:29:16 +0000 (19:29 -0600)]
phycore_imx8mp: Rework some of the RAM related Kconfig symbols
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. In this case we can easily fix this
by dropping the select line as the following choice statement handles
things correctly. We also drop the "default false" line as false / n is
the default.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Adam Ford [Tue, 18 Mar 2025 23:38:37 +0000 (18:38 -0500)]
configs: imx8mp_beacon: Select SPL_CLK_IMX8MP
In preparation to remove manual references for enabling some clocks,
enable SPL_CLK_IMX8MP which automatically enables SPL_CCF and
SPL_CLK_COMPOSITE_CCF which permit various drivers to activate
their respective clocks automatically.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Tue, 18 Mar 2025 23:38:36 +0000 (18:38 -0500)]
clk: imx: select SPL_CLK_COMPOSITE_CCF when SPL_CLK_IMX8MP
If SPL_CLK_IMX8MP is selected alone, it causes a build error.
The clock composite is required when using the clock framework, so
select it when SPL_CLK_IMX8MP is enabled. This is already being
done outside of SPL.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Tue, 18 Mar 2025 23:38:33 +0000 (18:38 -0500)]
serial: mxc: Support bulk enabling clocks
Depending on the platform, there may be multiple clock sources
required to enable a UART. Use the bulk functions to get and
enable the clocks when the UART probes. This can facilitate
the removal of functions to manually enable the clock.
This is made dependent on CLK_CCF which is used on imx6q,
imx8m[mnqp], several imxrt, imx9. If/when the UART clock
registration is done for older boards, this limitation
could be updated.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Tue, 18 Mar 2025 23:38:30 +0000 (18:38 -0500)]
clk: imx6q: Register UART clocks
In order to use the driver model and clock system to enable UART
clocks from the serial driver, it's necessary to register the UART
clocks. With the helper function to check for imx6qp vs other
variants, the UART can register for both scenarios.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Tue, 18 Mar 2025 23:38:29 +0000 (18:38 -0500)]
clk: imx6q: Properly handle imx6qp ECSPI clk_sels
The ECSPI clock has the ability to select between pll3_60m and
osc on the imx6qp, where it's fixed on other variants. Fix this
by adding using a helper function to determine SoC variant and
register the clock accordingly.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Paul Barker [Fri, 28 Feb 2025 12:47:54 +0000 (12:47 +0000)]
net: phy: ksz90x1: Load skew values from device tree
Various signal skew values may be set in the device tree for the ksz9131
Ethernet PHY. For example, the RZ/G2L board requires non-default values
for rxc-skew-psec & txc-skew-psec.
This is based on the ksz9131 phy driver in Linux v6.11.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Paul Barker [Fri, 28 Feb 2025 12:47:52 +0000 (12:47 +0000)]
net: phy: Port set/clear bits from Linux
To simply porting phy drivers from Linux to U-Boot, define
phy_set_bits() and phy_clear_bits() functions with a similar API to
those used in Linux.
The U-Boot versions of these functions include the `devad` argument
which is not present in the Linux versions, to keep them aligned with
the other phy functions in U-Boot.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Paul Barker [Tue, 11 Mar 2025 20:57:45 +0000 (20:57 +0000)]
reset: rzg2l-usbphy-ctrl: Connect up vbus regulator
Bind the USB VBUS regulator driver under the USB PHY reset driver for
the Renesas RZ/G2L and related SoCs. This additional bind is needed as
the corresponding device tree node does not contain a compatible string.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Tom Rini [Tue, 18 Mar 2025 19:12:51 +0000 (13:12 -0600)]
Merge patch series "pxe: Precursor series for supporting read_all() in extlinux / PXE"
Simon Glass <sjg@chromium.org> says:
This series includes some patches related to allowing read_all() to be
used with the extlinux / PXE bootmeths.
These patches were split out from the stb4 series, since it will need to
have additional patches for LWIP, to avoid breaking PXE booting when
LWIP is used.
Simon Glass [Thu, 6 Mar 2025 00:25:23 +0000 (17:25 -0700)]
net: Provide a function to run network operations
Add a new netboot_run() function which can be used for simple network
operations, such as loading a file. Put the implementation in an
internal function, used by the existing code.
Place this function into the net/ code, so that it does not need the
command line to be available.
Document which network operations are supported, i.e. a limited subset,
for now.
For the one board which uses lwip, it is not quite clear how to avoid
using the cmdline interface. This will need some discussion.
Simon Glass [Thu, 6 Mar 2025 00:25:21 +0000 (17:25 -0700)]
net: Refactor part of netboot_common() into a function
Move the core code for starting an netboot operation into a separate
function, so that we can (with additional work) move towards calling it
from outside the file.
Simon Glass [Thu, 6 Mar 2025 00:25:20 +0000 (17:25 -0700)]
net: Return the size from parse_args()
Rather than setting global variables, return the size, if provided. For
tftput, use the addr argument to store the save address, to avoid adding
yet another parameter.
projects / thirdparty / u-boot.git / log
