Conor Dooley [Tue, 25 Oct 2022 07:58:49 +0000 (08:58 +0100)]
riscv: dts: fix the mpfs's reference clock frequency
The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.
Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Conor Dooley [Tue, 25 Oct 2022 07:58:48 +0000 (08:58 +0100)]
clk: microchip: mpfs: fix criticality of peripheral clocks
Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.
Conor Dooley [Tue, 25 Oct 2022 07:58:47 +0000 (08:58 +0100)]
clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.
As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.
Conor Dooley [Tue, 25 Oct 2022 07:58:45 +0000 (08:58 +0100)]
clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()
Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.
Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.
Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.
The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.
Conor Dooley [Tue, 25 Oct 2022 07:58:44 +0000 (08:58 +0100)]
dt-bindings: clk: add missing clk ids for microchip mpfs
When this binding header was initally upstreamed, the PLL clocking the
microprocessor subsystem (MSS) and the RTC reference clocks were
omitted. Add them now, matching the IDs used in Linux.
Conor Dooley [Wed, 26 Oct 2022 07:49:19 +0000 (08:49 +0100)]
i2c: microchip: fix erroneous late ack send
A late ack is currently being sent at the end of a transfer due to
incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
bit is being written to the controller's control reg after the last
byte has been received, causing it to sent another byte with the ack.
Instead, the AA flag should be written to the control register when
the penultimate byte is read so it is sent out for the last byte.
Conor Dooley [Wed, 26 Oct 2022 07:49:18 +0000 (08:49 +0100)]
i2c: microchip: fix ack sending logic
"Master receive mode" was not correctly sending ACKs/NACKs in the
interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
M_RX_DATA_NACKED in line with the Linux driver.
Tom Rini [Sat, 29 Oct 2022 00:27:10 +0000 (20:27 -0400)]
Convert CONFIG_SYS_NONCACHED_MEMORY to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to
gate if we are going to have noncached_... functions available and then
continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said
cache. We make this new option depend on both the architectures which
implement support and the drivers which make use of it.
Cc: Tom Warren <twarren@nvidia.com> Cc: Mingming lee <mingming.lee@mediatek.com> Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:07 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MONITOR_LEN to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MONITOR_LEN
To do this, we set a default of 0 for everyone because there are a
number of cases where we define CONFIG_SYS_MONITOR_LEN but the only
impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN +
CONFIG_ENV_SIZE, so we must continue to allow all boards to set this
value. Update the SPL code to use 200 KB as the default raw U-Boot size
directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:02 +0000 (20:27 -0400)]
Convert CONFIG_SYS_LOADS_BAUD_CHANGE et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_LOADS_ECHO
As part of this, we move CMD_SAVES to be after CMD_LOADS as they are
logically related (load or save an s-record format file) and this makes
grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:59 +0000 (20:26 -0400)]
fs: jffs2: Move SYS_JFFS2_SORT_FRAGMENTS to Kconfig
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only
remaining part of doc/README.JFFS2 that is still relevant and useful to
the help for this option.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:58 +0000 (20:26 -0400)]
Remove unused symbols CONFIG_SYS_JFFS2_FIRST_BANK et al
This removes the following symbols:
CONFIG_RTC_MCFRRTC
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LIME_SIZE
CONFIG_SYS_MAMR
CONFIG_SYS_MCFRRTC_BASE
CONFIG_SYS_MONITOR_SEC
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Fabio Estevam [Fri, 4 Nov 2022 11:12:54 +0000 (08:12 -0300)]
wandboard: Pass mmc aliases
Originally, the mmc aliases node was present in imx6qdl-wandboard.dtsi.
After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a regression in which the SD card cannot be found anymore:
Since commit the aliases node has been removed
U-Boot 2022.10-00999-gcca41ed3d63f-dirty (Nov 03 2022 - 22:07:38 -0300)
CPU: Freescale i.MX6QP rev1.0 at 792 MHz
Reset cause: POR
DRAM: 2 GiB
Core: 62 devices, 17 uclasses, devicetree: separate
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... MMC: no card present
*** Warning - No block device, using default environment
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the SD card (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 13:43:41 +0000 (08:43 -0500)]
configs: imx8mn_beacon: Re-align memory to standard imx8mn settings
The imx8mn_beacon board does not use the same memory map as the reference
design from NXP or other imx8mn boards. As such, memory is more limited
in SPL.
Moving SPL_BSS_START_ADDR and SPL_STACK to default locations increases
the amount of available meory for the SPL stack. Doing this allows
the board to no longer define CONFIG_MALLOC_F_ADDR.
Since SYS_LOAD_ADDR also does not align with other boards, move it too.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marcel Ziswiler [Mon, 7 Nov 2022 21:22:36 +0000 (22:22 +0100)]
imxrt1050: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.
Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.
The IMX8M based Venice boards all have device-tree fec nodes that
use proper dt with a phy-handle pointing to a phy with reg assigned
to the proper phy address.
There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when
a proper dt is used - remove it.
This was previously done in commit 400eebf10d9b
("configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR")
but got clobbered by commit 6889412ad5e7
("Convert CONFIG_SYS_BARGSIZE to Kconfig")
Tim Harvey [Fri, 4 Nov 2022 15:43:06 +0000 (08:43 -0700)]
board: gateworks: venice: remove redundance adjustment of thermal trip points
commit 0543a1ed2787 ("imx8m: fixup thermal trips") moved updating the
thermal trip points to all IMX8M so we can remove it from our board
specific dt config.
Simon Glass [Sun, 30 Oct 2022 01:47:17 +0000 (19:47 -0600)]
dm: sandbox: Switch over to using the new host uclass
Update the sandbox implementation to use UCLASS_HOST and adjust all
the pieces to continue to work:
- Update the 'host' command to use the new API
- Replace various uses of UCLASS_ROOT with UCLASS_HOST
- Disable test_eficonfig since it doesn't work (this should have a unit
test to allow this to be debugged)
- Update the blk test to use the new API
- Drop the old header file
Unfortunately it does not seem to be possible to split this change up
further.
Simon Glass [Sun, 30 Oct 2022 01:47:15 +0000 (19:47 -0600)]
dm: sandbox: Create a new HOST uclass
Sandbox supports block devices which can access files on the host machine.
At present there is no uclass for this. The devices are attached to the
root devic. The block-device type is therefore set to UCLASS_ROOT which
is confusing.
Block devices should be attached to a 'media' device instead, something
which handles access to the actual media and provides the block driver
for the block device.
Create a new uclass to handle this. It supports two operations, to attach
and detach a file on the host machine.
Simon Glass [Sun, 30 Oct 2022 01:47:14 +0000 (19:47 -0600)]
dm: blk: Tidy up obtaining a block device from its parent
This function now finds its block-device child by looking for a child
device of the correct uclass (UCLASS_BLK). It cannot produce a device of
any other type, so drop the superfluous check.
Provide a version which does not probe the device, since that is often
needed when setting up the device's platdata.
Simon Glass [Sun, 30 Oct 2022 01:47:13 +0000 (19:47 -0600)]
test: Add a way to detect a test that breaks another
When running unit tests, some may have side effects which cause a
subsequent test to break. This can sometimes be seen when using 'ut dm'
or similar.
Add a new argument which allows a particular (failing) test to be run
immediately after a certain number of tests have run. This allows the
test causing the failure to be determined.
Simon Glass [Sun, 30 Oct 2022 01:47:08 +0000 (19:47 -0600)]
dm: test: Clear the block cache after running a test
Some tests access data in block devices and so cause the cache to fill
up. This results in memory being allocated.
Some tests check the malloc usage at the beginning and then again at the
end, to ensure there is no memory leak caused by the test. The block cache
makes this difficult, since the any test may cause entries to be allocated
or even freed, if the cache becomes full.
It is simpler to clear the block cache after each test. This ensures that
it will not introduce noise in tests which check malloc usage.
Add the logic to clear the cache, using the existing blkcache_invalidate()
function. Drop the duplicate code at the same time.
Martyn Welch [Tue, 25 Oct 2022 09:55:01 +0000 (10:55 +0100)]
drivers: power: pmic: Enable use of rn5t567 PMIC in SPL
The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.
Adam Ford [Sat, 22 Oct 2022 14:28:24 +0000 (09:28 -0500)]
imx: imx8mm-beacon: Move Environment to eMMC partition 2
The downstream U-Boot distributed by Beacon stores the environment
in the eMMC and the end of partition 2. This allow the environment
to stay on the SOM regardless of the boot source.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 14:28:23 +0000 (09:28 -0500)]
imx: imx8mm-beacon: Enable USB booting via SDP
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL. Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode. Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 14:28:22 +0000 (09:28 -0500)]
imx: imx8mm_beacon: Eliminate a few extras to free up SPL space
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit. Remove the extras.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Adam Ford [Sat, 22 Oct 2022 13:43:44 +0000 (08:43 -0500)]
imx: imx8mn-beacon: Fix out of spec voltage
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Sat, 22 Oct 2022 13:43:42 +0000 (08:43 -0500)]
regulator: bd718x7: Only bind children when PMIC_CHILDREN is enabled
If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error. Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.
Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Fabio Estevam <festevam@gmail.com>
- The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0.
While the old register values were saved, the actual masking was
missing.
- imx_udelay() expects the system counter to run at its base frequency,
but the system counter is switched to a lower frequency earlier in
psci_system_suspend(), leading to a much longer delay than intended.
Replace the call with an equivalent loop (linux-imx 5.15 does the same)
This fixes the SoC hanging forever when there was already a wakeup IRQ
pending while suspending.
Chris Packham [Sat, 5 Nov 2022 04:24:00 +0000 (17:24 +1300)]
arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Sat, 5 Nov 2022 04:23:59 +0000 (17:23 +1300)]
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
projects / thirdparty / u-boot.git / log
