Alan Modra [Wed, 16 Sep 2015 08:37:03 +0000 (18:07 +0930)]
Fix slowdown in ld -r for most common case of out-of-order relocs
I chose insertion sort since relocs are mostly sorted, but there is a
common case we can handle better; A run of relocs put out of order
due to not linking input files in order.
PR 18867
* elflink.c (elf_link_adjust_relocs): Modify insertion sort to
insert a run. Return status in case of malloc failure.
Adjust callers.
bfd/
* elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value
plus addend rather than the original st_value when looking up
entries in opd->adjust.
ld/testsuite/
* ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s,
ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s,
ld-powerpc/tocopt6.d: New test.
* ld-powerpc/powerpc.exp (ppc64elftests): Add it.
Alan Modra [Fri, 3 Jul 2015 01:26:26 +0000 (10:56 +0930)]
Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
Peter Bergner [Mon, 22 Jun 2015 19:55:24 +0000 (14:55 -0500)]
PPC sync instruction accepts invalid and incompatible operands
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC. Edmar added
support for this insruction varient here:
Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC. This patch changes the assembler to
error out on invalid and incompatible operand usage.
opcodes/
* ppc-opc.c (insert_ls): Test for invalid LS operands.
(insert_esync): New function.
(LS, WC): Use insert_ls.
(ESYNC): Use insert_esync.
Peter Bergner [Fri, 19 Jun 2015 22:17:07 +0000 (17:17 -0500)]
Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
Peter Bergner [Fri, 12 Jun 2015 20:06:07 +0000 (15:06 -0500)]
Remove unused MTMSRD_L macro and re-add accidentally deleted comment.
In the commit that added PowerPC Pair Singles, Ben accidentally removed
a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
This was probably just an oversite when he was refreshing his patch to
trunk.
opcodes/
* ppc-opc.c: Add comment accidentally removed by old commit.
(MTMSRD_L): Delete.
Alan Modra [Fri, 5 Jun 2015 09:05:40 +0000 (18:35 +0930)]
ppc476 linker workaround shared lib fixes
When building a shared lib from non-PIC objects, we'll get dynamic
text relocations. These need to move with any insns we move.
Otherwise the dynamic reloc will modify the branch, resulting in
crashes and other unpleasant behaviour.
Also, ld -r --ppc476-workaround used with sufficiently aligned PIC
objects needs a fix for emitted REL16 relocs.
bfd/
* elf64-ppc.c (ppc_elf_relocate_section): Move dynamic text
relocs with insns moved by --ppc476-workaround. Correct
output of REL16 relocs.
ld/testsuite/
* ld-powerpc/ppc476-shared.s,
* ld-powerpc/ppc476-shared.lnk,
* ld-powerpc/ppc476-shared.d,
* ld-powerpc/ppc476-shared2.d: New tests.
* ld-powerpc/powerpc.exp: Run them.
Peter Bergner [Fri, 5 Jun 2015 01:27:03 +0000 (20:27 -0500)]
Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.
opcodes/
* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
gas/testsuite/
* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
* gas/ppc/power4.d: Likewise.
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