[AArch64] Fix off by one error in instruction relaxation mask.

The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to
ensure that destination register in a relaxed ldr instruction is
always X0.  The mask has an off by one error resulting in the most
significant bit of the destination register being retained in the
relaxed instruction.  The issue generally appears when the compiler
emits TLS accesses code under high register pressure resulting in a
broken code sequence.

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[AArch64 disassembler] Add missing checks of undefined encodings on
st1/st2/st3/st4 instructions.

opcodes/

* aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
instructions.

binutils/testsuite/

* binutils-all/aarch64/aarch64.exp: New test driver for AArch64.
* binutils-all/aarch64/unallocated-encoding.s: New testcase.
* binutils-all/aarch64/unallocated-encoding.d: Ditto.

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Fix memory size for gather/scatter instructions

For gathers with indices larger than elements (e. g.)

vpgatherqd      ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123]

We currently treat memory size as a size of index register, while it is
actually should be size of destination register:

vpgatherqd      ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123]

This patch fixes it.

opcodes/

        * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
        vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
        vscatterqps.
        * i386-tbl.h: Regenerate.

gas/testsuite/

        * gas/i386/avx512pf-intel.d: Change memory size for vgatherpf0qps,
        vgatherpf1qps, vscatterpf0qps, vscatterpf1qps.
        * gas/i386/avx512pf.s: Ditto.
        * gas/i386/x86-64-avx512pf-intel.d: Ditto.
        * gas/i386/x86-64-avx512pf.s: Ditto.
        * gas/i386/avx512f-intel.d: Change memory size for vgatherqps,
        vpgatherqd, vpscatterqd, vscatterqps.
        * gas/i386/avx512f.s: Ditto.
        * gas/i386/x86-64-avx512f-intel.d: Ditto.
        * gas/i386/x86-64-avx512f.s: Ditto.

Remove bogus vcvtps2ph variant.

We currently support version of vcvtps2ph with sae and only 1 register operand.
This version is encoded as if missing operand was equal to ymm0.
I didn't found any references to this variant in
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
This patch removes it.

opcodes/

        * i386-opc.tbl: Remove wrong variant of vcvtps2ph
        * i386-tbl.h: Regenerate.

Add support for CPUID PREFETCHWT1

Latest AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Has CPUID PREFETCHWT1 for prefetchwt1 instruction, which we list as AVX512PF.
This patch introduces CPUID PREFETCHWT1.

gas/

        * config/tc-i386.c (cpu_arch): Add .prefetchwt1.
        * doc/c-i386.texi: Document .prefetchwt1/prefetchwt1.

opcodes/

        * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
        (cpu_flags): Add CpuPREFETCHWT1.
        * i386-init.h: Regenerate.
        * i386-opc.h (CpuPREFETCHWT1): New.
        (i386_cpu_flags): Add cpuprefetchwt1.
        * i386-opc.tbl: Change CPU of prefetchwt1 from CpuAVX512PF to
CpuPREFETCHWT1.
        * i386-tbl.h: Regenerate.

gas/testsuite

        * gas/i386/avx512pf-intel.d: Remove prefetchwt1.
        * gas/i386/avx512pf.s: Ditto.
        * gas/i386/avx512pf.d: Ditto.
        * gas/i386/x86-64-avx512pf-intel.d: Ditto.
        * gas/i386/x86-64-avx512pf.s: Ditto.
        * gas/i386/x86-64-avx512pf.d: Ditto.
        * gas/i386/prefetchwt1-intel.d: New file.
        * gas/i386/prefetchwt1.s: Ditto.
        * gas/i386/prefetchwt1.d: Ditto.
        * gas/i386/x86-64-prefetchwt1-intel.d: Ditto.
        * gas/i386/x86-64-prefetchwt1.s: Ditto.
        * gas/i386/x86-64-prefetchwt1.d: Ditto.

Use Anysize on invlpg/clflush/prefetch*

opcodes/
2013-10-08  Jan Beulich <jbeulich@suse.com>

* i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
(clflush): Use Anysize instead of Byte|Unspecified.
(prefetch*): Likewise.
* i386-tbl.h: Re-generate.

Change cpu for vptestnmd and vptestnmq instructions.

In latest release of AVX512 spec
http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
Vptestnmq and vptestnmq instructions have CPUID AVX512F, not AVX512CD.
This patch fixes it.

opcodes/

        * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
        to CpuAVX512F.
        * i386-tbl.h: Regenerate.

gas/testsuite/

        * gas/i386/avx512cd-intel.d: Remove vptestnmq, vptestnmd.
        * gas/i386/avx512cd.s: Ditto.
        * gas/i386/avx512cd.d: Ditto.
        * gas/i386/x86-64-avx512cd-intel.d: Ditto.
        * gas/i386/x86-64-avx512cd.s: Ditto.
        * gas/i386/x86-64-avx512cd.d: Ditto.
        * gas/i386/avx512f-intel.d: Add vptestnmq, vptestnmd.
        * gas/i386/avx512f.s: Ditto.
        * gas/i386/avx512f.d: Ditto.
        * gas/i386/x86-64-avx512f-intel.d: Ditto.
        * gas/i386/x86-64-avx512f.s: Ditto.
        * gas/i386/x86-64-avx512f.d: Ditto.

Add clflushopt, xsaves, xsavec, xrstors

gas/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

* config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
* doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
clflushopt/.clfushopt.

gas/testsuite/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

* gas/i386/clflushopt-intel.d: New.
* gas/i386/clflushopt.d: Ditto.
* gas/i386/clflushopt.s: Ditto.
* gas/i386/i386.exp: Run new tests.
* gas/i386/x86-64-clflushopt-intel.d: New.
* gas/i386/x86-64-clflushopt.d: Ditto.
* gas/i386/x86-64-clflushopt.s: Ditto.
* gas/i386/x86-64-xsavec-intel.d: Ditto.
* gas/i386/x86-64-xsavec.d: Ditto.
* gas/i386/x86-64-xsavec.s: Ditto.
* gas/i386/x86-64-xsaves-intel.d: Ditto.
* gas/i386/x86-64-xsaves.d: Ditto.
* gas/i386/x86-64-xsaves.s: Ditto.
* gas/i386/xsavec-intel.d: Ditto.
* gas/i386/xsavec.d: Ditto.
* gas/i386/xsavec.s: Ditto.
* gas/i386/xsaves-intel.d: Ditto.
* gas/i386/xsaves.d: Ditto.
* gas/i386/xsaves.s: Ditto.

opcodes/

2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>

* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
MOD_0FC7_REG_5.
(PREFIX enum): Add PREFIX_0FAE_REG_7.
(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
(prefix_table): Add clflusopt.
(mod_table): Add xrstors, xsavec, xsaves.
* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
* i386-init.h: Regenerate.
* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
xsaves64, xsavec, xsavec64.
* i386-tbl.h: Regenerate.

Don't run x86-64-disassem for mingw targets

mingw targets pad text sections which won't work with x86-64-disassem.

* gas/i386/i386.exp: Don't run x86-64-disassem for mingw targets.

Properly handle ljmp/lcall with invalid MODRM byte

gas/testsuite/

2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

* gas/i386/disassem.s: New.
* gas/i386/disassem.d: Likewise.
* gas/i386/x86-64-disassem.s: Likewise.
* gas/i386/x86-64-disassem.d: Likewise.
* gas/i386/i386.exp: Run disassem and x86-64-disassem.

opcodes/

2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

* i386-dis.c (MOD_FF_REG_3): New.
(MOD_FF_REG_5): Likewise.
(mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
(reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.

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2014-03-07  Michael Hudson-Doyle  <michael.hudson@linaro.org>
    Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

bfd/
* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Use correct
offset while calculating relocation address.
(elfNN_aarch64_create_small_pltn_entry): Likewise.
(elfNN_aarch64_init_small_plt0_entry): Likewise.

 (cherry-pick from commit f44a1f8e513b37bcc52ba9ea0c172c3e94852756)

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Apply ld-arm/gc-hidden-1 to all ELF targets, not just *eabi* targets

ld/testsuite/
* ld-arm/gc-hidden-1.d: Remove target, add not-target to match
other ELF-only tests in this directory.  Loosen regexps so they
don't care what the exact addresses are.

(cherry picked from commit c125dbfb8c4c6755e188815de1bb65bcb7f1f159)

Fix check_relocs/gc_sweep_hook mismatch

PR ld/16643
* elflink.c (elf_gc_sweep): Call gc_sweep_hook for exactly
the same conditions we called check_relocs.

(cherry picked from commit 9850436d9e423d66d67d27135896582b2725782e)

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opcodes/

* aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.

gas/testsuite/

* gas/aarch64/fp-const0-parsing.s: New test.
* gas/aarch64/fp-const0-parsing.d: Likewise.

opcodes/

* aarch64-opc.c (print_register_offset_address): Call
get_int_reg_name to prepare the register name.

gas/testsuite/

* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
* gas/aarch64/ldst-reg-reg-offset.d: Update.

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* cache.c (bfd_cache_max_open): Cast RLIM_INFINITY to rlim_t.

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Add gather/scatter tests with incorrect memory operand

2014-01-31  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

PR gas/16488
* gas/i386/inval-avx512f.s: Add test for incorrect memory operand
for gather/scatter instructions.
* gas/i386/x86-64-inval-avx512f.s: Likewise.
* gas/i386/inval-avx512f.l: Adjust correspondingly.
* gas/i386/x86-64-inval-avx512f.l: Likewise.

Conflicts:
gas/testsuite/ChangeLog

Fix shift for AVX512F gather/scatter instructions

opcodes/

2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
    Jan Beulich  <jbeulich@suse.com>

PR binutils/16490
* i386-dis.c (OP_E_memory): Fix shift computation for
vex_vsib_q_w_dq_mode.

gas/testsuite/

2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
    Jan Beulich  <jbeulich@suse.com>

PR binutils/16490
* gas/i386/avx512f.d: Fix test output.
* gas/i386/avx512f-intel.d: Likewise.
* gas/i386/x86-64-avx512f.d: Likewise.
* gas/i386/x86-64-avx512f-intel.d: Likewise.

Conflicts:
gas/testsuite/ChangeLog

Remove regzmm from AVX2 gather assert

Since regzmm can't be used in AVX2 gather instructions, there is no need
to check regzmm in AVX2 gather assert.

2014-01-22  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

* config/tc-i386.c (check_VecOperands): Remove regzmm from AVX2
gather assert.

Add check for invalid register in AVX512 gathers

AVX512 gather instructions shouldn't accept the same register for both
destination and index.

gas/

2014-01-22  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

PR gas/16489
* config/tc-i386.c (check_VecOperands): Add check for invalid
register set in AVX512 gathers.

gas/testsuite/

2014-01-22  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>

PR gas/16489
* gas/i386/vgather-check.s: Add tests for AVX512 gathers.
* gas/i386/x86-64-vgather-check.s: Likewise.
* gas/i386/vgather-check-error.l: Update correspondingly.
* gas/i386/vgather-check-none.d: Likewise.
* gas/i386/vgather-check-warn.d: Likewise.
* gas/i386/vgather-check-warn.e: Likewise.
* gas/i386/vgather-check.d: Likewise.
* gas/i386/x86-64-vgather-check-error.l: Likewise.
* gas/i386/x86-64-vgather-check-none.d: Likewise.
* gas/i386/x86-64-vgather-check-warn.d: Likewise.
* gas/i386/x86-64-vgather-check-warn.e: Likewise.
* gas/i386/x86-64-vgather-check.d: Likewise.

Conflicts:
gas/ChangeLog
gas/testsuite/ChangeLog

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