ada: Fix miscompilation of loop over boolean range

The optimized form generated in this case turns out to be problematic.

gcc/ada/

* gcc-interface/trans.cc (Loop_Statement_to_gnu): Always use the
simpler form for a loop with a boolean iteration variable.

ada: Fix issue with indefinite vector of overaligned unconstrained array

The problem is that the aligning machinery is not consistently triggered,
depending on whether a constrained view or the nominal unconstrained view
of the element type is used to perform the allocations and deallocations.

gcc/ada/

* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Array_Subtype>: Put
the alignment directly on the type in the constrained case too.
* gcc-interface/utils.cc (maybe_pad_type): For an array type, take
the alignment of the element type as the original alignment.

ada: Compiler crash on container aggregate with loop_parameter_specifications

The compiler crashes on a container aggregate with more than one
iterated_element_association given by a loop_parameter_specification.
In such a case, the tree contains N_Iterated_Component_Association
nodes rather than N_Iterated_Element_Association nodes, and the code
for handling those needs to obtain the bounds from the Discrete_Choices
field of each N_Iterated_Component_Association rather than assuming
that the association has a normal list of choices.

gcc/ada/

* sem_aggr.adb (Resolve_Container_Aggregate): In the case where Comp
is an N_Iterated_Component_Association, pick up Discrete_Choices rather
than Choices.

ada: Another couple of cleanups in the finalization machinery

For package specs and bodies that need finalizers, Build_Finalizer is
invoked from the Standard scope so it needs to adjust the scope stack
before creating new objects; this changes it to do so only once.

For other kinds of scopes, it is invoked from Expand_Cleanup_Actions,
which assumes that the correct scope is already on the stack; that's
why Cleanup_Scopes adjusts the scope stack explicitly, but it should
use Pop_Scope instead of End_Scope to do it.

gcc/ada/

* exp_ch7.adb (Build_Finalizer): For package specs and bodies, push
and pop the specs onto the scope stack only once.
* inline.adb (Cleanup_Scopes): Call Pop_Scope instead of End_Scope.

ada: Deep delta aggregates in postconditions

Fix a bug in handling array-valued deep delta aggregates occurring in
postconditions. The bug could result in a spurious compilation failure.

gcc/ada/

* sem_aggr.adb (Resolve_Delta_Array_Aggregate): In the case of a
deep delta choice, the expected type for the expression will
typically not be the component type of the array type, so a call
to Analyze_And_Resolve that assumes otherwise would be an error.
It turns out that such a call, while wrong, is usually harmless
because the expression has already been marked as analyzed. This
doesn't work if the aggregate occurs in a postcondition and, in
any case, we don't want to rely on this. So do not perform the
call in the deep case.

ada: Small consistency fix for -gnatwv warning

The goal is to arrange for the warning to be issued consistently between
objects whose address is taken and objects whose address is not taken.

gcc/ada/

* sem_warn.adb (Check_References.Type_OK_For_No_Value_Assigned):
New predicate.
(Check_References): For Warn_On_No_Value_Assigned, use the same test
on the type in the address-not-taken and default cases.

gcc/testsuite/ChangeLog:

* gnat.dg/warn25.adb: Add xfail.

ada: Compiler error reporting illegal prefix on legal loop iterator with "in"

During semantic analysis, the compiler fails to determine the cursor type
in the case of a generalized iterator loop with "in", in the case where the
iterator type has a parent type that is a controlled type (for example) and
its ancestor iterator interface type is given after as a progenitor. It also
improperly determines the ancestor interface type during expansion (within
Expand_Iterator_Loop_Over_Container), for both "in" and "of" iterator forms.
The FE was assuming that the iterator interface is simply the parent type
of the iterator type, but that type can occur later in the interface list,
or be inherited. A new function is added that properly locates a type's
iterator interface ancestor, if any, and is called for analysis and expansion.

gcc/ada/

* exp_ch5.adb (Expand_Iterator_Loop_Over_Container): Retrieve the
iteration type's iteration interface progenitor via
Iterator_Interface_Ancestor, in the case of both "in" and "of"
iterators. Narrow the scope of Pack, so it's declared and
initialized only within the code related to "of" iterators, and
change its name to Cont_Type_Pack. Adjust comments.
* sem_ch5.adb (Get_Cursor_Type): In the case of a derived type,
retrieve the iteration type's iterator interface progenitor (if it
exists) via Iterator_Interface_Ancestor rather than assuming that
the parent type is the interface progenitor.
* sem_util.ads (Iterator_Interface_Ancestor): New function.
* sem_util.adb (Iterator_Interface_Ancestor): New function
returning a type's associated iterator interface type, if any, by
collecting and traversing the type's interfaces.

ada: Fix internal error on 'Address of task component

This happens when the prefix of the selected component is of an access type,
i.e. there is an implicit dereference. because the prefix is not resolved.

gcc/ada/

* sem_attr.adb (Resolve_Attribute) <Attribute_Address>: Remove the
bypass for prefixes with task type.

ada: Avoid Style_Checks pragmas affecting other units

gcc/ada/

* par.adb: Restore Style_Checks after parsing each unit.

ada: Fix type for SPARK expansion on deep delta aggregates

gcc/ada/

* exp_spark.adb (Expand_SPARK_Delta_Or_Aggregate): Fix type.

ada: Further cleanup in finalization machinery

The bodies of generic units are instantiated separately by GNAT at the end
of the processing of the compilation unit.  This requires the deferral of
the generation of cleanups and finalization actions in enclosing scopes,
except for instantiations in generic units where they are not generated.

The criterion used to detect this latter case is Inside_A_Generic, but this
global variable is not properly updated during the instantiation of generic
bodies, leading to problems with nested instantiations, so it is changed to
Expander_Active instead.  As a matter of fact, the exact same idiom is used
a few lines above to clear the Needs_Body variable.

gcc/ada/

* sem_ch12.adb (Analyze_Package_Instantiation): Test Expander_Active
to detect generic contexts for the generation of cleanup actions.

ada: Fix string indexing within GNAT.Calendar.Time_IO.Value

The patch fixes an issue in the compiler whereby calls to
GNAT.Calendar.Time_IO.Value where the actual for formal String Date with
indexing starting at any value besides one would result in a spurious runtime
exception.

gcc/ada/

* libgnat/g-catiio.adb (Value): Modify conditionals to use 'Last
instead of 'Length

ada: Small improvement to Null_Status function

The function is used to optimize away access checks.

gcc/ada/

* sem_util.adb (Null_Status): Deal with unchecked type conversions.

ada: Further cleanup in finalization machinery

This removes the specific treatment of transient scopes in initialization
procedures, which is obsolete.

gcc/ada/

* exp_aggr.adb (Convert_To_Assignments): Do not treat initialization
procedures specially when it comes to creating a transient scope.
* exp_ch7.adb (Build_Finalizer.Process_Declarations): Likewise.
* exp_util.adb (Requires_Cleanup_Actions): Likewise.

ada: Use CLOCK_MONOTONIC on VxWorks

The monotonic clock keeps track of the time that has elapsed since
system startup; that is, the value returned by clock_gettime() is the
amount of time (in seconds and nanoseconds) that has passed since the
system booted. The monotonic clock cannot be reset. As a result,
time interval measurements made relative to the monotonic clock are
not subject to errors resulting from the clock time being unexpectedly
adjusted between the interval start and end.

gcc/ada/

* s-oscons-tmplt.c: #define CLOCK_RT_Ada "CLOCK_MONOTONIC" for
__vxworks

ada: Deep delta aggregates cleanup.

Cleanup after the introduction of deep delta aggregates.
Eliminate a new gnatcheck message.

gcc/ada/

* sem_aggr.adb: Replace "not Present (...)" call with "No (...)" call.

ada: Small cleanup in finalization machinery

This removes an obsolete flag and adjusts a couple of obsolete comments.

gcc/ada/

* gen_il-fields.ads (Opt_Field_Enum): Remove Is_Finalization_Wrapper
* gen_il-gen-gen_nodes.adb (N_Block_Statement): Likewise.
* sinfo.ads (Is_Finalization_Wrapper): Delete.
* exp_ch7.adb (Build_Finalizer.Process_Declarations): Adjust comment
and remove obsolete code testing the Is_Finalization_Wrapper flag.
* exp_util.adb (Requires_Cleanup_Actions): Likewise.

ada: Runtime recompilation instructions improvements.

Revise instructions to work on both cross and native targets hosted
on Linux

gcc/ada/

* libgnat/libada.gpr: Revise section 1

ada: Deep delta aggregates

Add support for "deep" delta aggregates, a GNAT-defined language extension
conditionally enabled via the -gnatX0 switch. In a deep delta aggregate, a
delta choice may specify a subcomponent (as opposed to just a component).

gcc/ada/

* par.adb: Add new Boolean variable Inside_Delta_Aggregate.
* par-ch4.adb (P_Simple_Expression): Add support for a deep delta
aggregate choice. We turn a sequence of selectors into a peculiar
tree. We build a component (Indexed or Selected) whose prefix is
another such component, etc. The leftmost prefix at the bottom of
the tree has a "name" which is the first selector, without any
further prefix. For something like "with delta (1)(2) => 3" where
the type of the aggregate is an array of arrays of integers, we'll
build an N_Indexed_Component whose prefix is an integer literal 1.
This is consistent with the trees built for "regular"
(Ada-defined) delta aggregates.
* sem_aggr.adb (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice):
New queries.
(Resolve_Deep_Delta_Assoc): new procedure.
(Resolve_Delta_Array_Aggregate): call Resolve_Deep_Delta_Assoc in
deep case.
(Resolve_Delta_Record_Aggregate): call Resolve_Deep_Delta_Assoc in
deep case.
(Get_Component_Type): new function replaces old Get_Component
function.
* sem_aggr.ads (Is_Deep_Choice, Is_Root_Prefix_Of_Deep_Choice):
New queries.
* exp_aggr.adb (Expand_Delta_Array_Aggregate): add nested function
Make_Array_Delta_Assignment_LHS; call it instead of
Make_Indexed_Component.
(Expand_Delta_Record_Aggregate): add nested function
Make_Record_Delta_Assignment_LHS; call it instead of
Make_Selected_Component.
* exp_spark.adb (Expand_SPARK_Delta_Or_Update): Insert range
checks for indexes in deep delta aggregates.

ada: Fix Ada.Text_IO.Delete with "encoding=8bits" form

Before this patch, on Windows, file with non-ASCII Latin1 names could be created
with Ada.Text_IO.Create by passing "encoding=8bits" through the Form
parameter and a Latin1-encoded string through the Name parameter,
but calling Ada.Text_IO.Delete on them raised an illegitimate exception.

This patch fixes this by making the wrappers of the unlink system function
aware of the encoding value passed through the Form parameter. It also
removes an unnecessary curly-brace block.

gcc/ada/

* adaint.c (__gnat_unlink): Add new parameter and fix text
conversion on Windows. Remove unnecessary curly braces.
* adaint.h (__gnat_unlink): Add new parameter.
* libgnat/i-cstrea.ads (unlink): Adapt to __gnat_unlink signature
change.
* libgnat/i-cstrea.adb (unlink): New Subprogram definition.
* libgnat/s-crtl.ads (unlink): Adapt to __gnat_unlink signature
change.
* libgnat/s-fileio.adb (Delete): Pass encoding argument to unlink.

ada: Fix spurious error on call with default parameter in generic package

This occurs when the default value is a function call returning a private
type, and is caused by a bad interaction between two internal mechanisms.

gcc/ada/

* sem_ch12.adb (Save_Global_References.Set_Global_Type): Beef up
comment about the setting of the full view.
* sem_res.adb (Resolve_Actuals.Insert_Default): Add another bypass
for the case of a generic context.

ada: Fix misplaced index directive in documentation

The index directive must be located before the indexed element, at least
for the generated texinfo to be correct. See:

https://www.sphinx-doc.org/en/master/usage/restructuredtext/directives.html#directive-index

This was reported along with changes done in https://inbox.sourceware.org/gcc-patches/20230223102714.3606058-3-arsen@aarsen.me/

gcc/ada/

* doc/gnat_ugn/the_gnat_compilation_model.rst: Move index
directives.
* gnat_ugn.texi: Regenerate.

ada: Fix SCOs generation for aspect specifications

The recent overhaul for the representation of aspect specifications in
the tree broke SCOs generation: decisions that appeared in aspects were
processed twice, leading to the emission of erroneous obligations. Tweak
SCOs generation to skip aspect specifications the second time to go back
to the previous behavior.

gcc/ada/

* par_sco.adb (Process_Decisions)<Process_Node>: Skip aspect
specifications.

ada: Always use -gnatg in run-time GPR files

This patch makes it so -gnatg is always passed to the compiler when
rebuilding the run-time library with the dedicated GPR files. Before
this patch, if a user rebuilt the run-time with -XADAFLAGS=XXX where
XXX didn't include "-gnatg", the build would immediately fail. This
case occurs when following the instructions in libada.gpr, which
use '-XADAFLAGS="-gnatn"'.

gcc/ada/

* libgnat/libgnat_common.gpr: Unconditionally pass -gnatg.

ada: Trivial typo fix in comment

gcc/ada/

* exp_util.ads: Typo fix.

gcov: Formatting fixes

I've noticed the r14-5579 commit introduced some formatting issues,
this patch fixes what I saw.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

gcc/
* tree-profile.cc (gen_counter_update, tree_profiling): Formatting
fixes.
libgcc/
* libgcov.h (GCOV_SUPPORTS_ATOMIC): Formatting fixes.

testsuite: Fix up pr111309-2.c on arm [PR111309]

ARM defaults to -fshort-enums and the following testcase FAILs there in 2
lines.  The difference is that in C++, E0 has enum E type, which normally
has unsigned int underlying type, so it isn't int nor something that
promotes to int, which is why we diagnose it (in C it is promoted to int).
But with -fshort-enums, the underlying type is unsigned char in that case,
which promotes to int just fine.

The following patch adjusts the expectations, such that we don't expect
it on arm or when people manually test with -fshort-enums.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

PR c/111309
* c-c++-common/pr111309-2.c (foo): Don't expect errors for C++ with
-fshort-enums if second argument is E0.

builtins: Fix fold_builtin_query clzg/ctzg side-effects handling [PR112639]

As the testcase shows, I've missed one spot where initially the code thinks
it could use 2 argument IFN_CLZ/IFN_CTZ form, but then verifies it can't
because it doesn't have the right target value and turns it into the
arg0 ? arg1 : .C[LT]Z (arg0)
form.  That form evaluates the argument twice though and so needs save_expr,
which I've missed to call in that case.  In other cases where it is known
from the beginning that it will be needed (e.g. the __builtin_clzg case
on types smaller than unsigned int where we'll need to add an addend
to the clz value) or the unsigned __int128 expansion called save_expr
before.

2023-11-21  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/112639
* builtins.cc (fold_builtin_bit_query): If arg0 has side-effects, arg1
is specified but cleared, call save_expr on arg0.

* gcc.dg/torture/pr112639.c: New test.

[APX PPX] Support Intel APX PPX

PPX stands for Push-Pop Acceleration. PUSH/PUSH2 and its corresponding POP
can be marked with a 1-bit hint to indicate that the POP reads the
value written by the PUSH from the stack. The processor tracks these marked
instructions internally and fast-forwards register data between
matching PUSH and POP instructions, without going through memory or
through the training loop of the Fast Store Forwarding Predictor (FSFP).
This feature can also be adopted to PUSH2/POP2.

For GCC, we emit explicit suffix 'p' (paired) to indicate the push/pop
pair are marked with PPX hint. To separate form original push/pop, we
add an UNSPEC on top of those PUSH/POP patterns.

In the first implementation we only emit them under prologue/epilogue
when saving/restoring callee-saved registers to make sure push/pop are
paired. So an extra flag was added to check if PPX insns can be emitted
for those register save/restore interfaces.

The PPX hint is purely a performance hint. If the 'p' suffix is not
emitted for paired push/pop, the PPX optimization will be disabled,
while program sematic will not be affected at all.

gcc/ChangeLog:

* config/i386/i386-expand.h (gen_push): Add default bool
parameter.
(gen_pop): Likewise.
* config/i386/i386-opts.h (enum apx_features): Add apx_ppx, add
it to apx_all.
* config/i386/i386.cc (ix86_emit_restore_reg_using_pop): Add
ppx_p parameter for function declaration.
(gen_push2): Add ppx_p parameter, emit push2p if ppx_p is true.
(gen_push): Likewise.
(ix86_emit_restore_reg_using_pop2): Likewise for pop2p.
(ix86_emit_save_regs): Emit pushp/push2p under TARGET_APX_PPX.
(ix86_emit_restore_reg_using_pop): Add ppx_p, emit popp insn
and adjust cfi when ppx_p is ture.
(ix86_emit_restore_reg_using_pop2): Add ppx_p and parse to its
callee.
(ix86_emit_restore_regs_using_pop2): Likewise.
(ix86_expand_epilogue): Parse TARGET_APX_PPX to
ix86_emit_restore_reg_using_pop.
* config/i386/i386.h (TARGET_APX_PPX): New.
* config/i386/i386.md (UNSPEC_APX_PPX): New unspec.
(pushp_di): New define_insn.
(popp_di): Likewise.
(push2p_di): Likewise.
(pop2p_di): Likewise.
* config/i386/i386.opt: Add apx_ppx enum.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-interrupt-1.c: Adjust option to restrict them
under certain subfeatures.
* gcc.target/i386/apx-push2pop2-1.c: Likewise.
* gcc.target/i386/apx-push2pop2_force_drap-1.c: Likewise.
* gcc.target/i386/apx-push2pop2_interrupt-1.c: Likewise.
* gcc.target/i386/apx-ppx-1.c: New test.

middle-end/112622 - adjust arm testcases

The error message improved, adjust arm specific testcases.

* gcc.target/arm/bfloat16_vector_typecheck_1.c: Adjust.
* gcc.target/arm/bfloat16_vector_typecheck_2.c: Likewise.
* gcc.target/aarch64/bfloat16_vector_typecheck_1.c: Likewise.
* gcc.target/aarch64/bfloat16_vector_typecheck_2.c: Likewise.

tree-optimization/111970 - fix issue with SLP of emulated gather/scatter

There's a missed index adjustment for the SLP vector number when
computing the index/data vectors for emulated gather/scatter with SLP.
The following fixes this.

PR tree-optimization/111970
* tree-vect-stmts.cc (vectorizable_load): Fix offset calculation
for SLP gather load.
(vectorizable_store): Likewise for SLP scatter store.

LoongArch: Fix libgcc build failure when libc is not available

To use int64_t we included <stdint.h> in loongarch-def.h.
Unfortunately, loongarch-def.h is also used by libgcc etc., causing a
build failure when building a "stage1" cross compiler at which the
target libc is not built yet.

As int64_t is used for a C-compatible replacement of HOST_WIDE_INT, it's
not directly or indirectly referred by the target libraries.  So
guard everything requiring stdint.h with #if then they'll not block
target libraries.

gcc/ChangeLog:

* config/loongarch/loongarch-def.h (stdint.h): Guard with #if to
exclude it for target libraries.
(loongarch_isa_base_features): Likewise.
(loongarch_isa): Likewise.
(loongarch_abi): Likewise.
(loongarch_target): Likewise.
(loongarch_cpu_default_isa): Likewise.

RISC-V: Fix reduc_run-9.c test value check bug

The current test value check is incorrect which is exposed on -march=rv64gcv_zvl256b

Confirm on X86 also abort:
[jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$./a.out
------33.000000,4078.000000,45001776.000000,63369904.000000---
Aborted (core dumped)

Adapt the value check according to X86 result.

Pushed as it is obvious.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/reduc/reduc_run-9.c: Fix bug.

Support reduc_{and,ior,xor}_scal_m for V4HI/V8QI/V4QImode

gcc/ChangeLog:

PR target/112325
* config/i386/i386-expand.cc (emit_reduc_half): Hanlde
V8QImode.
* config/i386/mmx.md (reduc_<code>_scal_<mode>): New expander.
(reduc_<code>_scal_v4qi): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr112325-mmx-1.c: New test.

Daily bump.

Trivial typo fix in variadic

Fix all occurences of varadic, except for Rust (will be part of another change).

gcc/ChangeLog:

* config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic.
* config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name.
(nvptx_declare_function_name): Likewise.
(nvptx_call_args): Likewise.
(nvptx_expand_call): Likewise.

gcc/cp/ChangeLog:

* lambda.cc (compare_lambda_sig): Fix typo in variadic.

libcpp/ChangeLog:

* macro.cc (parse_params): Fix typo in variadic.
(create_iso_definition): Likewise.

Signed-off-by: Marc Poulhiès <dkm@kataplop.net>

gcov: Use unshare_expr() in gen_counter_update()

This fixes issues like this:

  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c: In function 'main':
  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: error: incorrect sharing of tree nodes
  __gcov0.main[0]
  # .MEM_12 = VDEF <.MEM_9>
  __gcov0.main[0] = PROF_edge_counter_4;
  during IPA pass: profile
  gcc/testsuite/gcc.dg/no_profile_instrument_function-attr-1.c:19:1: internal compiler error: verify_gimple failed

Unshare the counter expression in the second gimple_build_assign() in
gen_counter_update().  This is similar to the original
gimple_gen_edge_profiler() for "ref":

void
gimple_gen_edge_profiler (int edgeno, edge e)
{
  tree one;

  one = build_int_cst (gcov_type_node, 1);

  if (flag_profile_update == PROFILE_UPDATE_ATOMIC)
[...]
  else
    {
      tree ref = tree_coverage_counter_ref (GCOV_COUNTER_ARCS, edgeno);
      tree gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node,
   NULL, "PROF_edge_counter");
      gassign *stmt1 = gimple_build_assign (gcov_type_tmp_var, ref);
      gcov_type_tmp_var = make_temp_ssa_name (gcov_type_node,
      NULL, "PROF_edge_counter");
      gassign *stmt2 = gimple_build_assign (gcov_type_tmp_var, PLUS_EXPR,
    gimple_assign_lhs (stmt1), one);
      gassign *stmt3 = gimple_build_assign (unshare_expr (ref),
    gimple_assign_lhs (stmt2));
      gsi_insert_on_edge (e, stmt1);
      gsi_insert_on_edge (e, stmt2);
      gsi_insert_on_edge (e, stmt3);
    }
}

However, the orignal gimple_gen_time_profiler() did not use unshare_expr() for
the counter expression (tree_time_profiler_counter):

void
gimple_gen_time_profiler (unsigned tag)
{
[...]

  /* Emit: counters[0] = ++__gcov_time_profiler_counter.  */
  if (flag_profile_update == PROFILE_UPDATE_ATOMIC)
[...]
  else
    {
      tree tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile");
      gassign *assign = gimple_build_assign (tmp, tree_time_profiler_counter);
      gsi_insert_before (&gsi, assign, GSI_NEW_STMT);

      tmp = make_temp_ssa_name (type, NULL, "PROF_time_profile");
      assign = gimple_build_assign (tmp, PLUS_EXPR, gimple_assign_lhs (assign),
    one);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
      assign = gimple_build_assign (original_ref, tmp);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
      assign = gimple_build_assign (tree_time_profiler_counter, tmp);
      gsi_insert_after (&gsi, assign, GSI_NEW_STMT);
    }
}

gcc/ChangeLog:

* tree-profile.cc (gen_counter_update): Use unshare_expr() for the
counter expression in the second gimple_build_assign().

inter-procedural value range propagation

implement very basic propapgation of return value ranges from VRP
pass.  This helps std::vector's push_back since we work out value range of
allocated block.  This propagates only within single translation unit.  I hoped
we will also do the propagation at WPA stage, but that needs more work on
ipa-cp side.

I also added code auto-detecting return_nonnull and corresponding -Wsuggest-attribute.

gcc/ChangeLog:

* cgraph.cc (add_detected_attribute_1): New function.
(cgraph_node::add_detected_attribute): Likewise.
* cgraph.h (cgraph_node::add_detected_attribute): Declare.
* common.opt: Add -Wsuggest-attribute=returns_nonnull.
* doc/invoke.texi: Document new flag.
* gimple-range-fold.cc (fold_using_range::range_of_call):
Use known reutrn value ranges.
* ipa-prop.cc (struct ipa_return_value_summary): New type.
(class ipa_return_value_sum_t): New type.
(ipa_return_value_sum): New summary.
(ipa_record_return_value_range): New function.
(ipa_return_value_range): New function.
* ipa-prop.h (ipa_return_value_range): Declare.
(ipa_record_return_value_range): Declare.
* ipa-pure-const.cc (warn_function_returns_nonnull): New funcion.
* ipa-utils.h (warn_function_returns_nonnull): Declare.
* symbol-summary.h: Fix comment.
* tree-vrp.cc (execute_ranger_vrp): Record return values.

gcc/testsuite/ChangeLog:

* g++.dg/ipa/devirt-2.C: Add noipa attribute to prevent ipa-vrp.
* g++.dg/ipa/devirt-7.C: Disable ipa-vrp.
* g++.dg/ipa/ipa-icf-2.C: Disable ipa-vrp.
* g++.dg/ipa/ipa-icf-3.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-1.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-3.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-5.C: Disable ipa-vrp.
* g++.dg/ipa/ivinline-8.C: Disable ipa-vrp.
* g++.dg/ipa/nothrow-1.C: Disable ipa-vrp.
* g++.dg/ipa/pure-const-1.C: Disable ipa-vrp.
* g++.dg/ipa/pure-const-2.C: Disable ipa-vrp.
* g++.dg/lto/inline-crossmodule-1_0.C: Disable ipa-vrp.
* gcc.c-torture/compile/pr106433.c: Add noipa attribute to prevent ipa-vrp.
* gcc.c-torture/execute/frame-address.c: Likewise.
* gcc.dg/vla-1.c: Add noipa attribute to prevent ipa-vrp.
* gcc.dg/ipa/fopt-info-inline-1.c: Disable ipa-vrp.
* gcc.dg/ipa/ipa-icf-25.c: Disable ipa-vrp.
* gcc.dg/ipa/ipa-icf-38.c: Disable ipa-vrp.
* gcc.dg/ipa/pure-const-1.c: Disable ipa-vrp.
* gcc.dg/ipa/remref-0.c: Add noipa attribute to prevent ipa-vrp.
* gcc.dg/tree-prof/time-profiler-1.c: Disable ipa-vrp.
* gcc.dg/tree-prof/time-profiler-2.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/pr110269.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/pr20701.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/vrp05.c: Disable ipa-vrp.
* gcc.dg/tree-ssa/return-value-range-1.c: New test.

tree-optimization/112618 - unused .MASK_CALL

We have to make sure to remove unused .MASK_CALL internal function
calls after vectorization.

PR tree-optimization/112618
* tree-vect-loop.cc (vect_transform_loop_stmt): For not
relevant and unused .MASK_CALL make sure we remove the
scalar stmt.

* gcc.dg/pr112618.c: New testcase.

tree-optimization/112281 - loop distribution and zero dependence distances

The following fixes an omission in dependence testing for loop
distribution.  When the overall dependence distance is not zero but
the dependence direction in the innermost common loop is = there is
a conflict between the partitions and we have to merge them.

PR tree-optimization/112281
* tree-loop-distribution.cc
(loop_distribution::pg_add_dependence_edges): For = in the
innermost common loop record a partition conflict.

* gcc.dg/torture/pr112281-1.c: New testcase.
* gcc.dg/torture/pr112281-2.c: Likewise.

middle-end/112622 - convert and vector-to-float

The following avoids ICEing when trying to convert a vector to
a scalar float.

PR middle-end/112622
* convert.cc (convert_to_real_1): Use element_precision
where a vector type might appear.  Provide specific
diagnostic for unexpected vector argument.

* gcc.dg/pr112622.c: New testcase.
* gcc.dg/simd-2.c: Adjust.
* gcc.target/i386/vect-bfloat16-typecheck_1.c: Likewise.
* gcc.target/i386/vect-bfloat16-typecheck_2.c: Likewise.

RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax

ICE:
bug.c:10:1: error: unrecognizable insn:
   10 | }
      | ^
(insn 10 9 11 2 (set (reg:V4SI 140)
        (unspec:V4SI [
                (unspec:V4BI [
                        (const_vector:V4BI [
                                (const_int 1 [0x1]) repeated x4
                            ])
                        (const_int 4 [0x4])
                        (const_int 2 [0x2]) repeated x3
                        (reg:SI 66 vl)
                        (reg:SI 67 vtype)
                    ] UNSPEC_VPREDICATE)
                (unspec:V4SI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF)
                (subreg:V4SI (reg:V2DI 138 [ v ]) 0)
                (subreg:SI (reg/v:DI 136 [ b ]) 0)
            ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1
     (nil))

The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI which is totally same as V4SI
on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax.

The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use get_vector_mode to get
right mode.

PR target/112597

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
* config/riscv/vector.md: Fix slide1 intermediate mode bug.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.

RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv.

We currently allow 64-bit indices/offsets for vector indexed loads and
stores even on rv32 but we should not.

This patch adjusts the iterators as well as the insn conditions to
reflect the RVV spec.

It also fixes an oversight in the VLS modes of the demote iterator that
was found while testing the patch.

gcc/ChangeLog:

* config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p):
Add check for XLEN == 32.
* config/riscv/vector-iterators.md: Change VLS part of the
demote iterator to 2x elements modes
* config/riscv/vector.md: Adjust iterators and insn conditions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c: Moved to...
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c: ...here.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c:
Adjust include.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c: New test.
* gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c: New test.

arm: [MVE intrinsics] rework vldq1 vst1q

Implement vld1q, vst1q using the new MVE builtins framework.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-base.cc (vld1_impl, vld1q)
(vst1_impl, vst1q): New.
* config/arm/arm-mve-builtins-base.def (vld1q, vst1q): New.
* config/arm/arm-mve-builtins-base.h (vld1q, vst1q): New.
* config/arm/arm_mve.h
(vld1q): Delete.
(vst1q): Delete.
(vld1q_s8): Delete.
(vld1q_s32): Delete.
(vld1q_s16): Delete.
(vld1q_u8): Delete.
(vld1q_u32): Delete.
(vld1q_u16): Delete.
(vld1q_f32): Delete.
(vld1q_f16): Delete.
(vst1q_f32): Delete.
(vst1q_f16): Delete.
(vst1q_s8): Delete.
(vst1q_s32): Delete.
(vst1q_s16): Delete.
(vst1q_u8): Delete.
(vst1q_u32): Delete.
(vst1q_u16): Delete.
(__arm_vld1q_s8): Delete.
(__arm_vld1q_s32): Delete.
(__arm_vld1q_s16): Delete.
(__arm_vld1q_u8): Delete.
(__arm_vld1q_u32): Delete.
(__arm_vld1q_u16): Delete.
(__arm_vst1q_s8): Delete.
(__arm_vst1q_s32): Delete.
(__arm_vst1q_s16): Delete.
(__arm_vst1q_u8): Delete.
(__arm_vst1q_u32): Delete.
(__arm_vst1q_u16): Delete.
(__arm_vld1q_f32): Delete.
(__arm_vld1q_f16): Delete.
(__arm_vst1q_f32): Delete.
(__arm_vst1q_f16): Delete.
(__arm_vld1q): Delete.
(__arm_vst1q): Delete.
* config/arm/mve.md (mve_vld1q_f<mode>): Rename into ...
(@mve_vld1q_f<mode>): ... this.
(mve_vld1q_<supf><mode>): Rename into ...
(@mve_vld1q_<supf><mode>) ... this.
(mve_vst1q_f<mode>): Rename into ...
(@mve_vst1q_f<mode>): ... this.
(mve_vst1q_<supf><mode>): Rename into ...
(@mve_vst1q_<supf><mode>) ... this.

arm: [MVE intrinsics] fix vst1 tests

vst1q intrinsics return void, so we should not do 'return vst1q_f16 (base, value);'

This was OK so far, but will trigger an error/warning with the new
implementation of these intrinsics.

This patch just removes the 'return' keyword.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/testsuite/
* gcc.target/arm/mve/intrinsics/vst1q_f16.c: Remove 'return'.
* gcc.target/arm/mve/intrinsics/vst1q_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vst1q_u8.c: Likewise.

arm: [MVE intrinsics] add load and store shapes

This patch adds the load and store shapes descriptions.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (load, store): New.
* config/arm/arm-mve-builtins-shapes.h (load, store): New.

arm: [MVE intrinsics] Add support for contiguous loads and stores

This patch adds base support for load/store intrinsics to the
framework, starting with loads and stores for contiguous memory
elements, without extension nor truncation.

Compared to the aarch64/SVE implementation, there's no support for
gather/scatter loads/stores yet.  This will be added later as needed.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-functions.h (multi_vector_function)
(full_width_access): New classes.
* config/arm/arm-mve-builtins.cc
(find_type_suffix_for_scalar_type, infer_pointer_type)
(require_pointer_type, get_contiguous_base, add_mem_operand)
(add_fixed_operand, use_contiguous_load_insn)
(use_contiguous_store_insn): New.
* config/arm/arm-mve-builtins.h (memory_vector_mode)
(infer_pointer_type, require_pointer_type, get_contiguous_base)
(add_mem_operand)
(add_fixed_operand, use_contiguous_load_insn)
(use_contiguous_store_insn): New.

arm: [MVE intrinsics] Add support for void and load/store pointers as argument types.

This patch adds support for '_', 'al' and 'as' for void, load pointer
and store pointer argument/return value types in intrinsic signatures.

It also adds a mew memory_scalar_type() helper to function_instance,
which is used by 'al' and 'as'.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (build_const_pointer):
New.
(parse_type): Add support for '_', 'al' and 'as'.
* config/arm/arm-mve-builtins.h (function_instance): Add
memory_scalar_type.
(function_base): Likewise.

arm: Fix arm_simd_types and MVE scalar_types

So far we define arm_simd_types and scalar_types using type
definitions like intSI_type_node, etc...

This is causing problems with later patches which re-implement
load/store MVE intrinsics, leading to error messages such as:
  error: passing argument 1 of 'vst1q_s32' from incompatible pointer type
  note: expected 'int *' but argument is of type 'int32_t *' {aka 'long int *'}

This patch uses get_typenode_from_name (INT32_TYPE) instead, which
defines the types as appropriate for the target/C library.

2023-11-16  Christophe Lyon  <christophe.lyon@linaro.org>

gcc/
* config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Fix
initialization of arm_simd_types[].eltype.
* config/arm/arm-mve-builtins.def (DEF_MVE_TYPE): Fix scalar
types.

RISC-V Regression: Remove scalable compile option

Since we already set scalable vectorization by default, this flag is redundant.

Also, we are start to full coverage testing with different compile option.
E.g --param=riscv-autovec-preference=fixed-vlmax.
To avoid compile option confusion. Remove it.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Remove scalable compile option.

c, c++: Add new value for vector types for __builtin_classify_type

While filing a clang request to return 18 on _BitInts for
__builtin_classify_type instead of -1 they return currently, I've
noticed that we return -1 for vector types.  Initially I wanted to change
behavior just for __builtin_classify_type (type) form, as that is new in
GCC 14 and we've returned for 20+ years -1 for __builtin_classify_type
on vector expressions, but I was convinved otherwise, so this changes
the behavior even for that and now returns 19.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

gcc/
* typeclass.h (enum type_class): Add vector_type_class.
* builtins.cc (type_to_class): Return vector_type_class for
VECTOR_TYPE.
* doc/extend.texi (__builtin_classify_type): Mention bit-precise
integer types and vector types.
gcc/testsuite/
* c-c++-common/builtin-classify-type-1.c (main): Add tests for vector
types.

vect: Add bool pattern handling for COND_OPs.

In order to handle masks properly for conditional operations this patch
teaches vect_recog_mask_conversion_pattern to also handle conditional
operations.  Now we convert e.g.

 _mask = *_6;
 _ifc123 = COND_OP (_mask, ...);

into
 _mask = *_6;
 patt200 = (<signed-boolean:1>) _mask;
 patt201 = COND_OP (patt200, ...);

This way the mask will be properly recognized as boolean mask and the
correct vector mask will be generated.

gcc/ChangeLog:

PR middle-end/112406

* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Convert masks for conditional operations as well.

gcc/testsuite/ChangeLog:

* gfortran.dg/pr112406.f90: New test.

tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization for direct optab [PR90693]

On Fri, Nov 17, 2023 at 03:01:04PM +0100, Jakub Jelinek wrote:
> As a follow-up, I'm considering changing in this routine the popcount
> call to IFN_POPCOUNT with 2 arguments and during expansion test costs.

Here is the follow-up which does the rtx costs testing.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/90693
* tree-ssa-math-opts.cc (match_single_bit_test): Mark POPCOUNT with
result only used in equality comparison against 1 with direct optab
support as .POPCOUNT call with 2 arguments.
* internal-fn.h (expand_POPCOUNT): Declare.
* internal-fn.def (DEF_INTERNAL_INT_EXT_FN): New macro, document it,
undefine at the end.
(POPCOUNT): Use it instead of DEF_INTERNAL_INT_FN.
* internal-fn.cc (DEF_INTERNAL_INT_EXT_FN): Define to nothing before
inclusion to define expanders.
(expand_POPCOUNT): New function.

tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization [PR90693]

Per the earlier discussions on this PR, the following patch folds
popcount (x) == 1 (and != 1) into (x ^ (x - 1)) > x - 1 (or <=)
if the corresponding popcount optab isn't implemented (I think any
double-word popcount or call will be necessarily slower than the
above cheap 3 op check and even for -Os larger or same size).

I've noticed e.g. C++ aligned new starts with std::has_single_bit
which does popcount (x) == 1.

As a follow-up, I'm considering changing in this routine the popcount
call to IFN_POPCOUNT with 2 arguments and during expansion test costs.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/90693
* tree-ssa-math-opts.cc (match_single_bit_test): New function.
(math_opts_dom_walker::after_dom_children): Call it for EQ_EXPR
and NE_EXPR assignments and GIMPLE_CONDs.

* gcc.target/i386/pr90693.c: New test.

internal-fn: Always undefine DEF_INTERNAL* macros at the end of internal-fn.def

I have noticed we are inconsistent, some DEF_INTERNAL*
macros (most of them) were undefined at the end of internal-fn.def (but in
some cases uselessly undefined again after inclusion), while others were not
(and sometimes undefined after the inclusion).  I've changed it to always
undefine at the end of internal-fn.def.

2023-11-20  Jakub Jelinek  <jakub@redhat.com>

* internal-fn.def: Document missing DEF_INTERNAL* macros and make sure
they are all undefined at the end.
* internal-fn.cc (lookup_hilo_internal_fn, lookup_evenodd_internal_fn,
widening_fn_p, get_len_internal_fn): Don't undef DEF_INTERNAL_*FN
macros after inclusion of internal-fn.def.

testsuite: arm: fix arm_movt cut&pasto

I got spurious fails of tests that required arm_thumb1_movt_ok on a
target cpu that did not support movt.  Looking into it, I found the
arm_movt property to have been cut&pasted into other procs that
checked for different properties.  They shouldn't share the same test
results cache entry, so I'm changing their prop names.  Or rather its
prop name, because the other occurrence was already fixed recently.

for  gcc/testsuite/ChangeLog

* lib/target-supports.exp
(check_effective_target_arm_thumb1_cbz_ok): Fix prop name
cut&pasto.

testsuite: analyzer: expect alignment warning with -fshort-enums

On targets that have -fshort-enums enabled by default, the type casts
in the pr108251 analyzer tests warn that the byte-aligned enums may
not be sufficiently aligned to be a struct connection *.  The function
can't know better, the warning is reasonable, the code doesn't
expected enums to be shorter and less aligned than the struct.

Rather than use -fno-short-enums, I decided to embrace the warning on
targets that have short_enums enabled by default.

However, C++ doesn't issue the warning, because even with
-fshort-enums, enumeration types are not TYPE_PACKED, and the
expression is not sufficiently simplified by the C++ front-end for
check_and_warn_address_or_pointer_of_packed_member to identify the
insufficiently aligned pointer.  So don't expect the warning there.

for  gcc/testsuite/ChangeLog

* c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early-O2.c:
Expect "unaligned pointer value" warning on short_enums
targets, but not in c++.
* c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c:
Likewise.

testsuite: scev: expect fail on ilp32

I've recently patched scev-3.c and scev-5.c because it only passed by
accident on ia32.  It also fails on some (but not all) arm-eabi
variants.  It seems hard to characterize the conditions in which the
optimization is supposed to pass, but expecting them to fail on ilp32
targets, though probably a little excessive and possibly noisy, is not
quite as alarming as getting a fail in test reports, so I propose
changing the xfail marker from ia32 to ilp32.

I'm also proposing to add a similar marker to scev-4.c.  Though it
doesn't appear to be failing for me, I've got reports that suggest it
still does for others, and it certainly did for us as well.

for  gcc/testsuite/ChangeLog

* gcc.dg/tree-ssa/scev-3.c: xfail on all ilp32 targets,
though some of these do pass.
* gcc.dg/tree-ssa/scev-4.c: Likewise.
* gcc.dg/tree-ssa/scev-5.c: Likewise.

Initial support for AVX10.1

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_available_features):
Add avx10_set and version and detect avx10.1.
(cpu_indicator_init): Handle avx10.1-512.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_256_SET): New.
(OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1.
(ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512.
Add indicator for explicit no-avx512 and no-avx10.1 options.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
AVX10_1_256 and AVX10_1_512.
* config/i386/cpuid.h (bit_AVX10): New.
(bit_AVX10_256): Ditto.
(bit_AVX10_512): Ditto.
* config/i386/driver-i386.cc (check_avx10_avx512_features): New.
(host_detect_local_cpu): Do not append "-mno-" options under
specific scenarios to avoid emitting a warning.
* config/i386/i386-isa.def
(EVEX512): Add DEF_PTA(EVEX512).
(AVX10_1_256): Add DEF_PTA(AVX10_1_256).
(AVX10_1_512): Add DEF_PTA(AVX10_1_512).
* config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and
-mavx10.1-512.
(ix86_function_specific_save): Save explicit no indicator.
(ix86_function_specific_restore): Restore explicit no indicator.
(ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and
avx10.1-512.
(ix86_valid_target_attribute_tree): Handle avx512 function
attributes with avx10.1 command line option.
(ix86_option_override_internal): Handle AVX10.1 options.
* config/i386/i386.h: Add PTA_EVEX512 for AVX512 target
machines.
* config/i386/i386.opt: Add variable ix86_no_avx512_explicit and
ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and
-mavx10.1-512.
* doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512.
* doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512.
* doc/sourcebuild.texi: Document target avx10.1, avx10.1-256
and avx10.1-512.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx10_1-1.c: New test.
* gcc.target/i386/avx10_1-10.c: Ditto.
* gcc.target/i386/avx10_1-11.c: Ditto.
* gcc.target/i386/avx10_1-12.c: Ditto.
* gcc.target/i386/avx10_1-13.c: Ditto.
* gcc.target/i386/avx10_1-14.c: Ditto.
* gcc.target/i386/avx10_1-15.c: Ditto.
* gcc.target/i386/avx10_1-16.c: Ditto.
* gcc.target/i386/avx10_1-17.c: Ditto.
* gcc.target/i386/avx10_1-18.c: Ditto.
* gcc.target/i386/avx10_1-19.c: Ditto.
* gcc.target/i386/avx10_1-2.c: Ditto.
* gcc.target/i386/avx10_1-20.c: Ditto.
* gcc.target/i386/avx10_1-21.c: Ditto.
* gcc.target/i386/avx10_1-22.c: Ditto.
* gcc.target/i386/avx10_1-23.c: Ditto.
* gcc.target/i386/avx10_1-3.c: Ditto.
* gcc.target/i386/avx10_1-4.c: Ditto.
* gcc.target/i386/avx10_1-5.c: Ditto.
* gcc.target/i386/avx10_1-6.c: Ditto.
* gcc.target/i386/avx10_1-7.c: Ditto.
* gcc.target/i386/avx10_1-8.c: Ditto.
* gcc.target/i386/avx10_1-9.c: Ditto.

c++: compare one level of template parms

There should never be a reason to compare more than one level of template
parameters; additional levels are for the enclosing context, which is either
irrelevant (for a template template parameter) or already compared (for a
member template).

Also, the comp_template_parms handling of type parameters was wrongly
checking for TEMPLATE_TYPE_PARM when a type parameter appears here as a
TYPE_DECL.

gcc/cp/ChangeLog:

* pt.cc (comp_template_parms): Just one level.
(template_parameter_lists_equivalent_p): Likewise.

c++: add DECL_IMPLICIT_TEMPLATE_PARM_P macro

Let's use a more informative name instead of DECL_VIRTUAL_P directly.

gcc/cp/ChangeLog:

* cp-tree.h (DECL_TEMPLATE_PARM_CHECK): New.
(DECL_IMPLICIT_TEMPLATE_PARM_P): New.
(decl_template_parm_check): New.
* mangle.cc (write_closure_template_head): Use it.
* parser.cc (synthesize_implicit_template_parm): Likewise.
* pt.cc (template_parameters_equivalent_p): Likewise.

Add i?86-*-* and x86_64-*-* to vect_logical_reduc

x86 backend support reduc_{and,ior,xor>_scal_m for vector integer
modes.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp (vect_logical_reduc): Add i?86-*-*
and x86_64-*-*.

Support reduc_{plus,xor,and,ior}_scal_m for vector integer mode.

BB vectorizer relies on the backend support of
.REDUC_{PLUS,IOR,XOR,AND} to vectorize reduction.

gcc/ChangeLog:

PR target/112325
* config/i386/sse.md (reduc_<code>_scal_<mode>): New expander.
(REDUC_ANY_LOGIC_MODE): New iterator.
(REDUC_PLUS_MODE): Extend to VxHI/SI/DImode.
(REDUC_SSE_PLUS_MODE): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr112325-1.c: New test.
* gcc.target/i386/pr112325-2.c: New test.

RISC-V: Implement -mmemcpy-strategy= options[PR112537]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112537

-mmemcpy-strategy=[auto|libcall|scalar|vector]

auto: Current status, use scalar or vector instructions.
libcall: Always use a library call.
scalar: Only use scalar instructions.
vector: Only use vector instructions.

PR target/112537

gcc/ChangeLog:

* config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum): Strategy enum.
* config/riscv/riscv-string.cc (riscv_expand_block_move): Disabled based on options.
(expand_block_move): Ditto.
* config/riscv/riscv.opt: Add -mmemcpy-strategy=.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/cpymem-strategy-1.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-2.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-3.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-4.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy-5.c: New test.
* gcc.target/riscv/rvv/base/cpymem-strategy.h: New test.

LoongArch: Modify MUSL_DYNAMIC_LINKER.

Use no suffix at all in the musl dynamic linker name for hard
float ABI. Use -sf and -sp suffixes in musl dynamic linker name
for soft float and single precision ABIs. The following table
outlines the musl interpreter names for the LoongArch64 ABI names.

musl interpreter            | LoongArch64 ABI
--------------------------- | -----------------
ld-musl-loongarch64.so.1    | loongarch64-lp64d
ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f
ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s

gcc/ChangeLog:

* config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.

Daily bump.

RISC-V: Optimize constant AVL for LRA pattern

This optimization was discovered in the tuple move splitted bug fix patch.

Before this patch:

vsetivli        zero,4,e16,mf2,ta,ma
        lhu     a3,96(a5)
        vlseg8e16.v     v1,(a5)
        lw      a4,%lo(e)(a2)
        vsetvli a6,zero,e64,m2,ta,ma
        addi    a0,a7,8
        vse16.v v1,0(a7)
        vse16.v v2,0(a0)
        addi    a0,a0,8
        vse16.v v3,0(a0)
        addi    a0,a0,8
        vse16.v v4,0(a0)
        addi    a0,a0,8
        vse16.v v5,0(a0)
        addi    a0,a0,8
        vse16.v v6,0(a0)
        addi    a0,a0,8
        vse16.v v7,0(a0)
        addi    a0,a0,8
        vse16.v v8,0(a0)

After this patch:

vsetivli zero,4,e64,m2,ta,ma
addi a0,a7,8
vlseg8e16.v v1,(a5)
vse16.v v1,0(a7)
vse16.v v2,0(a0)
addi a0,a0,8
vse16.v v3,0(a0)
addi a0,a0,8
vse16.v v4,0(a0)
addi a0,a0,8
vse16.v v5,0(a0)
addi a0,a0,8
vse16.v v6,0(a0)
addi a0,a0,8
vse16.v v7,0(a0)
addi a0,a0,8
vse16.v v8,0(a0)

gcc/ChangeLog:

* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Optimize constant AVL.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/post-ra-avl.c: New test.

c++: Set DECL_CONTEXT for __cxa_thread_atexit [PR99187]

Modules streaming requires DECL_CONTEXT to be set on declarations that
are streamed. This ensures that __cxa_thread_atexit is given translation
unit context much like is already done with many other support
functions.

PR c++/99187

gcc/cp/ChangeLog:

* cp-tree.h (enum cp_tree_index): Add CPTI_THREAD_ATEXIT.
(thread_atexit_node): New.
* decl.cc (get_thread_atexit_node): Cache in thread_atexit_node.

gcc/testsuite/ChangeLog:

* g++.dg/modules/pr99187.C: New test.

Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
Signed-off-by: Nathan Sidwell <nathan@acm.org>

[committed] RISC-V: Infrastructure for instruction fusion

I've been meaning to extract this and upstream it for a long time.  The work is
primarily Philipp from VRULL with one case added by Raphael and light bugfixing
on my part.

Essentially there's 10 distinct fusions supported and they can be selected
individually by building a suitable mask in the uarch tuning structure.
Additional cases can be added -- the bulk of the effort is in recognizing the
two fusible instructions.

The cases supported in this patch are all from the Veyron V1 processor, though
the hope is they will be useful elsewhere.  I would encourage those familiar
with other uarch implementations to enable fusion cases for those uarchs and
extend the set of supported cases if any are missing.

gcc/
* config/riscv/riscv-protos.h (extract_base_offset_in_addr): Prototype.
* config/riscv/riscv.cc (riscv_fusion_pairs): New enum.
(riscv_tune_param): Add fusible_ops field.
(riscv_tune_param_rocket_tune_info): Initialize new field.
(riscv_tune_param_sifive_7_tune_info): Likewise.
(thead_c906_tune_info): Likewise.
(generic_oo_tune_info): Likewise.
(optimize_size_tune_info): Likewise.
(riscv_macro_fusion_p): New function.
(riscv_fusion_enabled_p): Likewise.
(riscv_macro_fusion_pair_p): Likewise.
(TARGET_SCHED_MACRO_FUSION_P): Define.
(TARGET_SCHED_MACRO_FUSION_PAIR_P): Likewise.
(extract_base_offset_in_addr): Moved into riscv.cc from...
* config/riscv/thead.cc: Here.

Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
Co-authored-by: Jeff Law <jlaw@ventanamicro.com>

[committed] Fix missing mode on a few unspec/unspec_volatile operands

This is fix for a minor problem Jivan and I found while testing the ext-dce work originally from Joern.

The ext-dce pass will transform zero/sign extensions into subreg accesses when
the upper bits are actually unused.  So it's more likely with the ext-dce work
to get a sequence like this prior to combine:

>
>> (insn 10 9 11 2 (set (reg:SI 144)
>>         (unspec_volatile [
>>                 (const_int 0 [0])
>>             ] UNSPECV_FRFLAGS)) "j.c":11:3 discrim 1 362 {riscv_frflags}
>>      (nil))
>> (insn 11 10 55 2 (set (reg:DI 140 [ _12 ])
>>         (subreg:DI (reg:SI 144) 0)) "j.c":11:3 discrim 1 206 {*movdi_64bit}
>>      (expr_list:REG_DEAD (reg:SI 144)
>>         (nil)))

When we try to combine insn 10->11 we'll ultimately call simplify_subreg with
something like

(subreg:DI (unspec_volatile [...]) 0)

Note the lack of a mode on the unspec_volatile.  That in turn will cause
simplify_subreg to trigger an assertion.

The modeless unspec is generated by the RISC-V backend and the more I've
pondered this issue over the last few days the more I'm convinced it's a
backend bug.  Basically if the LHS of the set has a mode, then the RHS of the
set should have a mode as well.

I've audited the various backends and only found a few problems which are fixed
by this patch.  I've tested the relevant ports in my tester.  c6x, sh, mips and
s390[x].

There are other patterns that are potentially problematical in various ports.
They have a REG destination and an UNSPEC source, but the REG has no mode in
the pattern.  Since it wasn't clear what mode to give the UNSPEC, I left those
alone.

gcc/

* config/c6x/c6x.md (mvilc): Add mode to UNSPEC source.
* config/mips/mips.md (rdhwr_synci_step_<mode>): Likewise.
* config/riscv/riscv.md (riscv_frcsr, riscv_frflags): Likewise.
* config/s390/s390.md (@split_stack_call<mode>): Likewise.
(@split_stack_cond_call<mode>): Likewise.
* config/sh/sh.md (sp_switch_1): Likewise.

testsuite: Don't use -mfloat128 with AIX.

AIX doesn't support IEEE 128 floating point.  Don't add the -mfloat128
on AIX.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp (add_options_for___float128): Only add
-mfloat128 to powerpc*-*-linux*.

Signed-off-by: David Edelsohn <dje.gcc@gmail.com>

Makefile.tpl: Avoid race condition in generating site.exp from the top level

A command like "make -j 2 check-gcc-c check-gcc-c++" run in the top level of
a fresh build directory does not work reliably. That will spawn two
independent make processes inside the "gcc" directory, and each of those
will attempt to create site.exp if it doesn't exist and will interfere with
each other, producing often a corrupted or empty site.exp. Resolve that by
making these targets depend on a new phony target which makes sure site.exp
is created first before starting the recursive makes.

ChangeLog:

* Makefile.in: Regenerate.
* Makefile.tpl: Add dependency on site.exp to check-gcc-* targets

libcpp: split decls out to rich-location.h

The various decls relating to rich_location are in
libcpp/include/line-map.h, but they don't relate to line maps.

Split them out to their own header: libcpp/include/rich-location.h

No functional change intended.

gcc/ChangeLog:
* Makefile.in (CPPLIB_H): Add libcpp/include/rich-location.h.
* coretypes.h (class rich_location): New forward decl.

gcc/analyzer/ChangeLog:
* analyzer.h: Include "rich-location.h".

gcc/c-family/ChangeLog:
* c-lex.cc: Include "rich-location.h".

gcc/cp/ChangeLog:
* mapper-client.cc: Include "rich-location.h".

gcc/ChangeLog:
* diagnostic.h: Include "rich-location.h".
* edit-context.h (class fixit_hint): New forward decl.
* gcc-rich-location.h: Include "rich-location.h".
* genmatch.cc: Likewise.
* pretty-print.h: Likewise.

gcc/rust/ChangeLog:
* rust-location.h: Include "rich-location.h".

libcpp/ChangeLog:
* Makefile.in (TAGS_SOURCES): Add "include/rich-location.h".
* include/cpplib.h (class rich_location): New forward decl.
* include/line-map.h (class range_label)
(enum range_display_kind, struct location_range)
(class semi_embedded_vec, class rich_location, class label_text)
(class range_label, class fixit_hint): Move to...
* include/rich-location.h: ...this new file.
* internal.h: Include "rich-location.h".

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

RISC-V: Fix bug of tuple move splitter

PR target/112561

gcc/ChangeLog:

* config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112561.c: New test.

analyzer: new warning: -Wanalyzer-undefined-behavior-strtok [PR107573]

This patch:
- adds support to the analyzer for tracking API-private state
  or which we don't have a decl (such as strtok's internal state),
- uses it to implement a new -Wanalyzer-undefined-behavior-strtok which
  warns when strtok (NULL, delim) is called as the first call to
  strtok after main.

gcc/analyzer/ChangeLog:
PR analyzer/107573
* analyzer.h (register_known_functions): Add region_model_manager
param.
* analyzer.opt (Wanalyzer-undefined-behavior-strtok): New.
* call-summary.cc
(call_summary_replay::convert_region_from_summary_1): Handle
RK_PRIVATE.
* engine.cc (impl_run_checkers): Pass model manager to
register_known_functions.
* kf.cc (class undefined_function_behavior): New.
(class kf_strtok): New.
(register_known_functions): Add region_model_manager param.
Use it to register "strtok".
* region-model-manager.cc
(region_model_manager::get_or_create_conjured_svalue): Add "idx"
param.
* region-model-manager.h
(region_model_manager::get_or_create_conjured_svalue): Add "idx"
param.
(region_model_manager::get_root_region): New accessor.
* region-model.cc (region_model::scan_for_null_terminator): Handle
"expr" being null.
(region_model::get_representative_path_var_1): Handle RK_PRIVATE.
* region-model.h (region_model::called_from_main_p): Make public.
* region.cc (region::get_memory_space): Handle RK_PRIVATE.
(region::can_have_initial_svalue_p): Handle MEMSPACE_PRIVATE.
(private_region::dump_to_pp): New.
* region.h (MEMSPACE_PRIVATE): New.
(RK_PRIVATE): New.
(class private_region): New.
(is_a_helper <const private_region *>::test): New.
* store.cc (store::replay_call_summary_cluster): Handle
RK_PRIVATE.
* svalue.h (struct conjured_svalue::key_t): Add "idx" param to
ctor and "m_idx" field.
(class conjured_svalue::conjured_svalue): Likewise.

gcc/ChangeLog:
PR analyzer/107573
* doc/invoke.texi: Add -Wanalyzer-undefined-behavior-strtok.

gcc/testsuite/ChangeLog:
PR analyzer/107573
* c-c++-common/analyzer/strtok-1.c: New test.
* c-c++-common/analyzer/strtok-2.c: New test.
* c-c++-common/analyzer/strtok-3.c: New test.
* c-c++-common/analyzer/strtok-4.c: New test.
* c-c++-common/analyzer/strtok-cppreference.c: New test.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Daily bump.

MAINTAINERS: Update my email address.

Update my email address in the MAINTAINERS file.

2023-11-18 Petter Tomner <tomner@bahnhof.se>

ChangeLog:
* MAINTAINERS: Update my email address.

libstdc++: Check string value_type in std::make_format_args [PR112607]

libstdc++-v3/ChangeLog:

PR libstdc++/112607
* include/std/format (basic_format_arg::_S_to_arg_type): Check
value_type for basic_string_view and basic_string
specializations.
* testsuite/std/format/arguments/112607.cc: New test.

libstdc++: Add fast path for std::format("{}", x) [PR110801]

This optimizes the simple case of formatting a single string, integer
or bool, with no format-specifier (so no padding, alignment, alternate
form etc.)

libstdc++-v3/ChangeLog:

PR libstdc++/110801
* include/std/format (_Sink_iter::_M_reserve): New member
function.
(_Sink::_Reservation): New nested class.
(_Sink::_M_reserve, _Sink::_M_bump): New virtual functions.
(_Seq_sink::_M_reserve, _Seq_sink::_M_bump): New virtual
overrides.
(_Iter_sink<O, ContigIter>::_M_reserve): Likewise.
(__do_vformat_to): Use new functions to optimize "{}" case.

LoongArch: Fix "-mexplict-relocs=none -mcmodel=medium" producing %call36 when the assembler does not support it

Even if !HAVE_AS_SUPPORT_CALL36, const_call_insn_operand should still
return false when -mexplict-relocs=none -mcmodel=medium to make
loongarch_legitimize_call_address emit la.local or la.global.

gcc/ChangeLog:

* config/loongarch/predicates.md (const_call_insn_operand):
Remove buggy "HAVE_AS_SUPPORT_CALL36" conditions.  Change "1" to
"true" to make the coding style consistent.

LoongArch: Add fine-grained control for LAM_BH and LAMCAS

gcc/ChangeLog:

* config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas):
Add.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-cpucfg-map.h: Regenerate.
* config/loongarch/loongarch-cpu.cc
(ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH
and OPTION_MASK_ISA_LAMCAS.
* config/loongarch/sync.md (atomic_add<mode:SHORT>): Use
TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110.  Remove empty
lines from assembly output.
(atomic_exchange<mode>_short): Likewise.
(atomic_exchange<mode:SHORT>): Likewise.
(atomic_fetch_add<mode>_short): Likewise.
(atomic_fetch_add<mode:SHORT>): Likewise.
(atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead
of ISA_BASE_IS_LA64V110.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_compare_and_swap<mode:GPR>): Likewise.
(atomic_compare_and_swap<mode:SHORT>): Likewise.
* config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump
status if -mlam-bh and -mlamcas if -fverbose-asm.

LoongArch: Don't emit dbar 0x700 if -mld-seq-sa

This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other".  Thus
we can omit the "load-load" barrier dbar 0x700.

This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.

gcc/ChangeLog:

* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
print dbar 0x700 if TARGET_LD_SEQ_SA.
* config/loongarch/sync.md (atomic_load<mode>): Likewise.

LoongArch: Take the advantage of -mdiv32 if it's enabled

With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
of a 64-bit GPR even if it's not sign-extended.

gcc/ChangeLog:

* config/loongarch/loongarch.md (DIV): New mode iterator.
(<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
(<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
(*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
(<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/div-div32.c: New test.
* gcc.target/loongarch/div-no-div32.c: New test.

LoongArch: Add evolution features of base ISA revisions

* config/loongarch/loongarch-def.h:
(loongarch_isa_base_features): Declare.  Define it in ...
* config/loongarch/loongarch-cpu.cc
(loongarch_isa_base_features): ... here.
(fill_native_cpu_config): If we know the base ISA of the CPU
model from PRID, use it instead of la64 (v1.0).  Check if all
expected features of this base ISA is available, emit a warning
if not.
* config/loongarch/loongarch-opts.cc (config_target_isa): Enable
the features implied by the base ISA if not -march=native.

LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution

LoongArch v1.10 introduced the concept of ISA evolution.  During ISA
evolution, many independent features can be added and enumerated via
CPUCFG.

Add a data file into genopts storing the CPUCFG word, bit, the name
of the command line option controlling if this feature should be used
for compilation, and the text description.  Make genstr.sh process these
info and add the command line options into loongarch.opt and
loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for
mapping CPUCFG output to the corresponding option.  When handling
-march=native, use the information in loongarch-cpucfg-map.h to generate
the corresponding option mask.  Enable the features implied by -march
setting unless the user has explicitly disabled the feature.

The added options (-mdiv32 and -mld-seq-sa) are not really handled yet.
They'll be used in the following patches.

gcc/ChangeLog:

* config/loongarch/genopts/isa-evolution.in: New data file.
* config/loongarch/genopts/genstr.sh: Translate info in
isa-evolution.in when generating loongarch-str.h, loongarch.opt,
and loongarch-cpucfg-map.h.
* config/loongarch/genopts/loongarch.opt.in (isa_evolution):
New variable.
* config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
rule.
(loongarch-str.h): Depend on isa-evolution.in.
(loongarch.opt): Depend on isa-evolution.in.
(loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch-def.h (loongarch_isa):  Add field
for evolution features.  Add helper function to enable features
in this field.
Probe native CPU capability and save the corresponding options
into preset.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
Probe native CPU capability and save the corresponding options
into preset.
(cache_cpucfg): Simplify with C++11-style for loop.
(cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ...
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Enable the ISA evolution
feature options implied by -march and not explicitly disabled.
(loongarch_asm_code_end): New function, print ISA information as
comments in the assembly if -fverbose-asm.  It makes easier to
debug things like -march=native.
(TARGET_ASM_CODE_END): Define.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-cpucfg-map.h: Generate.
(cpucfg_useful_idx, N_CPUCFG_WORDS) ... here.

LoongArch: Fix internal error running "gcc -march=native" on LA664

On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture
is guessed ISA_BASE_LA64V100.  This causes a warning to be outputed:

    cc1: warning: base architecture 'la64' differs from PRID preset '?'

But we've not set the "?" above in loongarch_isa_base_strings, thus it's
a nullptr and then an ICE is triggered.

Add ISA_BASE_LA64V110 to genopts and initialize
loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE.
The warning itself will be fixed later.

gcc/ChangeLog:

* config/loongarch/genopts/loongarch-strings:
(STR_ISA_BASE_LA64V110): Add.
* config/loongarch/genopts/loongarch.opt.in:
(ISA_BASE_LA64V110): Add.
* config/loongarch/loongarch-def.c
(loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
to STR_ISA_BASE_LA64V110.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.

gcov: Improve -fprofile-update=atomic

The code coverage support uses counters to determine which edges in the control
flow graph were executed.  If a counter overflows, then the code coverage
information is invalid.  Therefore the counter type should be a 64-bit integer.
In multi-threaded applications, it is important that the counter increments are
atomic.  This is not the case by default.  The user can enable atomic counter
increments through the -fprofile-update=atomic and
-fprofile-update=prefer-atomic options.

If the target supports 64-bit atomic operations, then everything is fine.  If
not and -fprofile-update=prefer-atomic was chosen by the user, then non-atomic
counter increments will be used.  However, if the target does not support the
required atomic operations and -fprofile-atomic=update was chosen by the user,
then a warning was issued and as a forced fallback to non-atomic operations was
done.  This is probably not what a user wants.  There is still hardware on the
market which does not have atomic operations and is used for multi-threaded
applications.  A user which selects -fprofile-update=atomic wants consistent
code coverage data and not random data.

This patch removes the fallback to non-atomic operations for
-fprofile-update=atomic the target platform supports libatomic.  To
mitigate potential performance issues an optimization for systems which
only support 32-bit atomic operations is provided.  Here, the edge
counter increments are done like this:

  low = __atomic_add_fetch_4 (&counter.low, 1, MEMMODEL_RELAXED);
  high_inc = low == 0 ? 1 : 0;
  __atomic_add_fetch_4 (&counter.high, high_inc, MEMMODEL_RELAXED);

In gimple_gen_time_profiler() this split operation cannot be used, since the
updated counter value is also required.  Here, a library call is emitted.  This
is not a performance issue since the update is only done if counters[0] == 0.

gcc/c-family/ChangeLog:

* c-cppbuiltin.cc (c_cpp_builtins):  Define
__LIBGCC_HAVE_LIBATOMIC for libgcov.

gcc/ChangeLog:

* doc/invoke.texi (-fprofile-update): Clarify default method.  Document
the atomic method behaviour.
* tree-profile.cc (enum counter_update_method): New.
(counter_update): Likewise.
(gen_counter_update): Use counter_update_method.  Split the
atomic counter update in two 32-bit atomic operations if
necessary.
(tree_profiling): Select counter_update_method.

libgcc/ChangeLog:

* libgcov.h (GCOV_SUPPORTS_ATOMIC): Always define it.
Set it also to 1, if __LIBGCC_HAVE_LIBATOMIC is defined.

gcov: Add gen_counter_update()

Move the counter update to the new gen_counter_update() helper function.  Use
it in gimple_gen_edge_profiler() and gimple_gen_time_profiler().  The resulting
gimple instructions should be identical with the exception of the removed
unshare_expr() call.  The unshare_expr() call was used in
gimple_gen_edge_profiler().

gcc/ChangeLog:

* tree-profile.cc (gen_assign_counter_update): New.
(gen_counter_update): Likewise.
(gimple_gen_edge_profiler): Use gen_counter_update().
(gimple_gen_time_profiler): Likewise.

Add TARGET_HAVE_LIBATOMIC

Add target data to indicate if libatomic is available.

gcc/ChangeLog:

* config/rtems.h (TARGET_HAVE_LIBATOMIC): Define.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_HAVE_LIBATOMIC): Add.
* target.def (have_libatomic): New.

gcov: Remove TARGET_GCOV_TYPE_SIZE target hook

This reverts commit 8cdcea51c0fd753e6a652c9b236e91b3a6e0911c.

gcc/c-family/ChangeLog:

* c-cppbuiltin.cc (c_cpp_builtins): Do not define
__LIBGCC_GCOV_TYPE_SIZE.

gcc/ChangeLog:

* config/sparc/rtemself.h (SPARC_GCOV_TYPE_SIZE): Remove.
* config/sparc/sparc.cc (sparc_gcov_type_size): Likewise.
(TARGET_GCOV_TYPE_SIZE): Likewise.
* coverage.cc (get_gcov_type): Use LONG_LONG_TYPE_SIZE instead
of removed target hook.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_GCOV_TYPE_SIZE): Remove.
* target.def: Likewise.
* targhooks.cc (default_gcov_type_size): Likewise.
* targhooks.h (default_gcov_type_size): Likewise.

libgcc/ChangeLog:

* libgcov.h (gcov_type): Use LONG_LONG_TYPE_SIZE.
(gcov_type_unsigned): Likewise.

RISC-V: Fix mismatched new delete for unique_ptr

gcc/ChangeLog:

* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch): Use char[] for
std::unique_ptr to prevent mismatched new delete issue.
(riscv_process_one_target_attr): Ditto.
(riscv_process_target_attr): Ditto.

MAINTAINERS: Update my e-mail address

* MAINTAINERS: Change my address.

RISC-V: Refactor RVV iterators[NFC]

This patch refactors RVV iteratros for easier maintain.

E.g.

(define_mode_iterator V [
  RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")

  RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")

  (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
  (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
  (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")

  RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")

  (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")

  (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
  (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")

  (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
  (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
])

change it into:

(define_mode_iterator V [VI VF_ZVFHMIN])

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Refactor iterators.

Testsuite: remove unused variables

Missing from earlier commit, which removed the only use of those two
variables.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray/caf.exp: Remove unused variable.
* gfortran.dg/dg.exp: Remove unused variable.

libsanitizer: fix build on darwin

Upstream report of the issue at
https://github.com/llvm/llvm-project/issues/72639

libsanitizer/ChangeLog:

* asan/asan_mac.cpp: Protect Apple blocks behind the
MISSING_BLOCKS_SUPPORT macro.

LoongArch: atomic_load and atomic_store are implemented using dbar grading.

Because the la464 memory model design allows the same address load out of order,
so in the following test example, the Load of 23 lines may be executed first over
the load of 21 lines, resulting in an error.
So when memmodel is MEMMODEL_RELAXED, the load instruction will be followed by
"dbar 0x700" when implementing _atomic_load.

  1 void *
  2 gomp_ptrlock_get_slow (gomp_ptrlock_t *ptrlock)
  3 {
  4   int *intptr;
  5   uintptr_t oldval = 1;
  6
  7   __atomic_compare_exchange_n (ptrlock, &oldval, 2, false,
  8                                MEMMODEL_RELAXED, MEMMODEL_RELAXED);
  9
 10   /* futex works on ints, not pointers.
 11      But a valid work share pointer will be at least
 12      8 byte aligned, so it is safe to assume the low
 13      32-bits of the pointer won't contain values 1 or 2.  */
 14   __asm volatile ("" : "=r" (intptr) : "0" (ptrlock));
 15 #if __BYTE_ORDER == __BIG_ENDIAN
 16   if (sizeof (*ptrlock) > sizeof (int))
 17     intptr += (sizeof (*ptrlock) / sizeof (int)) - 1;
 18 #endif
 19   do
 20     do_wait (intptr, 2);
 21   while (__atomic_load_n (intptr, MEMMODEL_RELAXED) == 2);
 22   __asm volatile ("" : : : "memory");
 23   return (void *) __atomic_load_n (ptrlock, MEMMODEL_ACQUIRE);
 24 }

gcc/ChangeLog:

* config/loongarch/sync.md (atomic_load<mode>): New template.

LoongArch: Implement atomic operations using LoongArch1.1 instructions.

1. short and char type calls for atomic_add_fetch and __atomic_fetch_add are
   implemented using amadd{_db}.{b/h}.
2. Use amcas{_db}.{b/h/w/d} to implement __atomic_compare_exchange_n and __atomic_compare_exchange.
3. The short and char types of the functions __atomic_exchange and __atomic_exchange_n are
   implemented using amswap{_db}.{b/h}.

gcc/ChangeLog:

* config/loongarch/loongarch-def.h: Add comments.
* config/loongarch/loongarch-opts.h (ISA_BASE_IS_LA64V110): Define macro.
* config/loongarch/loongarch.cc (loongarch_memmodel_needs_rel_acq_fence):
Remove redundant code implementations.
* config/loongarch/sync.md (d): Added QI, HI support.
(atomic_add<mode>): New template.
(atomic_exchange<mode>_short): Likewise.
(atomic_cas_value_strong<mode>_amcas): Likewise..
(atomic_fetch_add<mode>_short): Likewise.

LoongArch: Add LA664 support.

Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1.
Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664.

gcc/ChangeLog:

* config.gcc: Support LA664.
* config/loongarch/genopts/loongarch-strings: Likewise.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise.
* config/loongarch/loongarch-def.c: Likewise.
* config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise.
(ISA_BASE_LA64V110): Define macro.
(N_ARCH_TYPES): Update value.
(N_TUNE_TYPES): Update value.
(CPU_LA664): New macro.
* config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise.
(isa_base_compat_p): Likewise.
* config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled
when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110.
(TARGET_uARCH_LA664): Define macro.
* config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise.
* config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width):
Add LA664 support.
* config/loongarch/loongarch.opt: Regenerate.

LoongArch: Add code generation support for call36 function calls.

When compiling with '-mcmodel=medium', the function call is made through
'pcaddu18i+jirl' if binutils supports call36, otherwise the
native implementation 'pcalau12i+jirl' is used.

gcc/ChangeLog:

* config.in: Regenerate.
* config/loongarch/loongarch-opts.h (HAVE_AS_SUPPORT_CALL36): Define macro.
* config/loongarch/loongarch.cc (loongarch_legitimize_call_address):
If binutils supports call36, the function call is not split over expand.
* config/loongarch/loongarch.md: Add call36 generation code.
* config/loongarch/predicates.md: Likewise.
* configure: Regenerate.
* configure.ac: Check whether binutils supports call36.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/func-call-medium-5.c: If the assembler supports call36,
the test is abandoned.
* gcc.target/loongarch/func-call-medium-6.c: Likewise.
* gcc.target/loongarch/func-call-medium-7.c: Likewise.
* gcc.target/loongarch/func-call-medium-8.c: Likewise.
* lib/target-supports.exp: Added a function to see if the assembler supports
the call36 relocation.
* gcc.target/loongarch/func-call-medium-call36-1.c: New test.
* gcc.target/loongarch/func-call-medium-call36.c: New test.

Co-authored-by: Xi Ruoyao <xry111@xry111.site>

analyzer: new warning: -Wanalyzer-infinite-loop [PR106147]

This patch implements a new analyzer warning: -Wanalyzer-infinite-loop.

It works by examining the exploded graph once the latter has been
fully built.  It attempts to detect cycles in the exploded graph in
which:
- no externally visible work occurs
- no escape is possible from the cycle once it has been entered
- the program state is "sufficiently concrete" at each step:
  - no unknown activity could be occurring
  - the worklist was fully drained for each enode in the cycle
    i.e. every enode in the cycle is processed

For example, it correctly complains about this bogus "for" loop:

  int sum = 0;
  for (struct node *iter = n; iter; iter->next)
    sum += n->val;
  return sum;

like this:

infinite-loop-linked-list.c: In function ‘for_loop_noop_next’:
infinite-loop-linked-list.c:110:31: warning: infinite loop [CWE-835] [-Wanalyzer-infinite-loop]
  110 |   for (struct node *iter = n; iter; iter->next)
      |                               ^~~~
  ‘for_loop_noop_next’: events 1-5
    |
    |  110 |   for (struct node *iter = n; iter; iter->next)
    |      |                               ^~~~
    |      |                               |
    |      |                               (1) infinite loop here
    |      |                               (2) when ‘iter’ is non-NULL: always following ‘true’ branch...
    |      |                               (5) ...to here
    |  111 |     sum += n->val;
    |      |     ~~~~~~~~~~~~~
    |      |         |   |
    |      |         |   (3) ...to here
    |      |         (4) looping back...
    |

gcc/ChangeLog:
PR analyzer/106147
* Makefile.in (ANALYZER_OBJS): Add analyzer/infinite-loop.o.
* doc/invoke.texi: Add -fdump-analyzer-infinite-loop and
-Wanalyzer-infinite-loop.  Add missing CWE link for
-Wanalyzer-infinite-recursion.
* timevar.def (TV_ANALYZER_INFINITE_LOOPS): New.

gcc/analyzer/ChangeLog:
PR analyzer/106147
* analyzer.opt (Wanalyzer-infinite-loop): New option.
(fdump-analyzer-infinite-loop): New option.
* checker-event.h (start_cfg_edge_event::get_desc): Drop "final".
(start_cfg_edge_event::maybe_describe_condition): Convert from
private to protected.
* checker-path.h (checker_path::get_logger): New.
* diagnostic-manager.cc (process_worklist_item): Update for
new context param of maybe_update_for_edge.
* engine.cc
(impl_region_model_context::impl_region_model_context): Add
out_could_have_done_work param to both ctors and use it to
initialize mm_out_could_have_done_work.
(impl_region_model_context::maybe_did_work): New vfunc
implementation.
(exploded_node::on_stmt): Add out_could_have_done_work param and
pass to ctxt ctor.
(exploded_node::on_stmt_pre): Treat setjmp and longjmp as "doing
work".
(exploded_node::on_longjmp): Likewise.
(exploded_edge::exploded_edge): Add "could_do_work" param and use
it to initialize m_could_do_work_p.
(exploded_edge::dump_dot_label): Add result of could_do_work_p.
(exploded_graph::add_function_entry): Mark edge as doing no work.
(exploded_graph::add_edge): Add "could_do_work" param and pass to
exploded_edge ctor.
(add_tainted_args_callback): Treat as doing no work.
(exploded_graph::process_worklist): Likewise when merging nodes.
(maybe_process_run_of_before_supernode_enodes::item): Likewise.
(exploded_graph::maybe_create_dynamic_call): Likewise.
(exploded_graph::process_node): Likewise for phi nodes.
Pass in a "could_have_done_work" bool when handling stmts and use
when creating edges.  Assume work is done at bifurcation.
(exploded_path::feasible_p): Update for new context param of
maybe_update_for_edge.
(feasibility_state::feasibility_state): New ctor.
(feasibility_state::operator=): New.
(feasibility_state::maybe_update_for_edge): Add ctxt param and use
it.  Fix missing newline when logging state.
(impl_run_checkers): Call exploded_graph::detect_infinite_loops.
* exploded-graph.h
(impl_region_model_context::impl_region_model_context): Add
out_could_have_done_work param to both ctors.
(impl_region_model_context::maybe_did_work): New decl.
(impl_region_model_context::checking_for_infinite_loop_p): New.
(impl_region_model_context::on_unusable_in_infinite_loop): New.
(impl_region_model_context::m_out_could_have_done_work): New
field.
(exploded_node::on_stmt): Add "out_could_have_done_work" param.
(exploded_edge::exploded_edge): Add "could_do_work" param.
(exploded_edge::could_do_work_p): New accessor.
(exploded_edge::m_could_do_work_p): New field.
(exploded_graph::add_edge): Add "could_do_work" param.
(exploded_graph::detect_infinite_loops): New decl.
(feasibility_state::feasibility_state): New ctor.
(feasibility_state::operator=): New decl.
(feasibility_state::maybe_update_for_edge): Add ctxt param.
* infinite-loop.cc: New file.
* program-state.cc (program_state::on_edge): Log the rejected
constraint when region_model::maybe_update_for_edge fails.
* region-model.cc (region_model::on_assignment): Treat any writes
other than to the stack as "doing work".
(region_model::on_stmt_pre): Treat all asm stmts as "doing work".
(region_model::on_call_post): Likewise for all calls to functions
with unknown side effects.
(region_model::handle_phi): Add svals_changing_meaning param.
Mark widening svalue in phi nodes as changing meaning.
(unusable_in_infinite_loop_constraint_p): New.
(region_model::add_constraint): If we're checking for an infinite
loop, bail out on unusable svalues, or if we don't have a definite
true/false for the constraint.
(region_model::update_for_phis): Gather all svalues changing
meaning in phi nodes, and purge constraints involving them.
(region_model::replay_call_summary): Treat all call summaries as
doing work.
(region_model::can_merge_with_p): Purge constraints involving
svalues that change meaning.
(model_merger::on_widening_reuse): New.
(test_iteration_1): Likewise.
(selftest::test_iteration_1): Remove assertion that model6 "knows"
that i < 157.
* region-model.h (region_model::handle_phi): Add
svals_changing_meaning param
(region_model_context::maybe_did_work): New pure virtual func.
(region_model_context::checking_for_infinite_loop_p): Likewise.
(region_model_context::on_unusable_in_infinite_loop): Likewise.
(noop_region_model_context::maybe_did_work): Implement.
(noop_region_model_context::checking_for_infinite_loop_p):
Likewise.
(noop_region_model_context::on_unusable_in_infinite_loop):
Likewise.
(region_model_context_decorator::maybe_did_work): Implement.
(region_model_context_decorator::checking_for_infinite_loop_p):
Likewise.
(region_model_context_decorator::on_unusable_in_infinite_loop):
Likewise.
(model_merger::on_widening_reuse): New decl.
(model_merger::m_svals_changing_meaning): New field.
* sm-signal.cc (register_signal_handler::impl_transition): Assume
the edge "does work".
* supergraph.cc (supernode::get_start_location): Use CFG edge's
goto_locus if available.
(supernode::get_end_location): Likewise.
(cfg_superedge::dump_label_to_pp): Dump edges with a "goto_locus"
* supergraph.h (cfg_superedge::get_goto_locus): New.
* svalue.cc (svalue::can_merge_p): Call on_widening_reuse for
widening values.
(involvement_visitor::visit_widening_svalue): New.
(svalue::involves_p): Update assertion to allow widening svalues.

gcc/testsuite/ChangeLog:
PR analyzer/106147
* c-c++-common/analyzer/gzio-2.c: Add dg-warning for infinite
loop, marked as xfail.
* c-c++-common/analyzer/infinite-loop-2.c: New test.
* c-c++-common/analyzer/infinite-loop-4.c: New test.
* c-c++-common/analyzer/infinite-loop-crc32c.c: New test.
* c-c++-common/analyzer/infinite-loop-doom-d_main-IdentifyVersion.c:
New test.
* c-c++-common/analyzer/infinite-loop-doom-v_video.c: New test.
* c-c++-common/analyzer/infinite-loop-g_error.c: New test.
* c-c++-common/analyzer/infinite-loop-linked-list.c: New test.
* c-c++-common/analyzer/infinite-recursion-inlining.c: Add
dg-warning directives for infinite loop.
* c-c++-common/analyzer/inlining-4-multiline.c: Update expected
paths for event 5 having a location.
* gcc.dg/analyzer/boxed-malloc-1.c: Add dg-warning for infinite
loop.
* gcc.dg/analyzer/data-model-20.c: Likewise.  Add comment about
suspect code, and create...
* gcc.dg/analyzer/data-model-20a.c: ...this new test by cleaning
it up.
* gcc.dg/analyzer/edges-1.c: Add a placeholder statement to avoid
the "...to here" from the if stmt occurring at the "while", and
thus being treated as a bogus event.
* gcc.dg/analyzer/explode-2a.c: Add dg-warning for infinite loop.
* gcc.dg/analyzer/infinite-loop-1.c: New test.
* gcc.dg/analyzer/malloc-1.c: Add dg-warning for infinite loop.
* gcc.dg/analyzer/out-of-bounds-coreutils.c: Add TODO.
* gcc.dg/analyzer/paths-4.c: Add dg-warning for infinite loop.
* gcc.dg/analyzer/pr103892.c: Likewise.
* gcc.dg/analyzer/pr93546.c: Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>