H.J. Lu [Thu, 8 Jun 2023 17:01:03 +0000 (10:01 -0700)]
x86-64: Add R_X86_64_CODE_4_GOTPCRELX
For
mov name@GOTPCREL(%rip), %reg
test %reg, name@GOTPCREL(%rip)
binop name@GOTPCREL(%rip), %reg
where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions,
add
# define R_X86_64_CODE_4_GOTPCRELX 43
if the instruction starts at 4 bytes before the relocation offset. It
similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX
as R_X86_64_GOTPCREL or convert the above instructions to
Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to
support Intel SHSTK in Linux kernel.
For now only userspace shadow stack and kernel IBT are supported by the
linux kernel. This note should be used instead of NT_X86_CET introduced
in the commit "x86: Add NT_X86_CET note", as it is outdated and only
used by old binutils versions.
* i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs.
(print_insn): Add #UD exception for jmpabs.
(dis386): Modify a1 unit for support jmpabs.
* i386-mnem.h: Regenerated.
* i386-opc.tbl: New insns.
* i386-tbl.h: Regenerated.
Hu, Lin1 [Thu, 28 Dec 2023 01:06:41 +0000 (01:06 +0000)]
Support APX NDD optimized encoding.
This patch aims to optimize:
add %r16, %r15, %r15 -> add %r16, %r15
gas/ChangeLog:
* config/tc-i386.c (check_Rex_required): New function.
(can_convert_NDD_to_legacy): Ditto.
(match_template): If we can optimzie APX NDD insns, so rematch
template.
* testsuite/gas/i386/x86-64.exp: Add test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto.
* gas/config/tc-i386.c (operand_size_match):
Support APX NDD that the number of operands is 3.
(build_apx_evex_prefix): Change for ndd encode.
(process_operands): Ditto.
(build_modrm_byte): Ditto.
(match_template): Support swap the first two operands for
APX NDD.
* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Add tests for APX GPR32 with extend evex prefix
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't
support gpr32.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add new test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
Cui, Lili [Thu, 28 Dec 2023 01:06:40 +0000 (01:06 +0000)]
Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
Cui, Lili [Thu, 28 Dec 2023 01:06:39 +0000 (01:06 +0000)]
Support APX GPR32 with rex2 prefix
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy
instructions. We added the NoEgpr flag in i386-gen.c for instructions
that do not support EGPR.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c
(enum i386_error): Add unsupported_EGPR_for_addressing
and invalid_pseudo_prefix.
(struct _i386_insn): Add rex2 and rex2_encoding for
gpr32.
(cpu_arch): Add apx_f.
(is_cpu): Ditto.
(register_number): Handle RegRex2 for gpr32.
(is_apx_rex2_encoding): New func. Test rex2 prefix encoding.
(build_rex2_prefix): New func. Build legacy insn in
opcode 0/1 use gpr32 with rex2 prefix.
(establish_rex): Handle rex2 and rex2_encoding.
(optimize_encoding): Handel add r16-r31 for registers.
(md_assemble): Handle apx encoding.
(parse_insn): Handle Prefix_REX2.
(check_EgprOperands): New func. Check if Egprs operands
are valid for the instruction
(match_template): Handle Egpr operands check.
(set_rex_rex2): New func. set i.rex and i.rex2.
(build_modrm_byte): Ditto.
(output_insn): Handle rex2 2-byte prefix output.
(check_register): Handle check egpr illegal without
target apx, 64-bit mode and with rex_prefix.
* doc/c-i386.texi: Document .apx.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid
in 64-bit mode.
* testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/rex-bad: Adjust rex testcase.
* testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.d: Ditto.
* testsuite/gas/i386/x86-64-opcode-inval.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test.
* testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Run APX tests.
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-rex2.d: New test.
* testsuite/gas/i386/x86-64-apx-rex2.s: New test.
The PRU architecture documentation [1] was used for the initial GNU
simulator implementation. But recently [2] TI confirmed the carry
behaviour was wrongly documented. In reality, the PRU carry behaves
like the carry in ARM processors.
This patch fixes simulator to align with latest recommendations from TI.
The new carry.s test was also validated to pass on real hardware -
a BeaglePlay board [3]. That test is a bit long because TI still
has not released official updates for the PRU documents. And I wanted
to ensure simulator handles all edge cases exactly as the real hardware
does.
The addend of SUB_ULEB128 should be zero if using .uleb128, but we make it
non-zero by accident in assembler before. This causes troubles by applying
the above commit, since the calculation is changed to support .reloc *SUB*
relocations with non-zero addend.
We encourage people to rebuild their stuff to get the non-zero addend of
SUB_ULEB128, but that might need some times, so report warnings to inform
people need to rebuild their stuff if --check-uleb128 is enabled.
Since the failed .reloc cases for ADD/SET/SUB/ULEB128 are rarely to use,
it may acceptable that stop supproting them until people rebuld their stuff,
maybe half-year or a year later. Or maybe we should teach people that don't
write the .reloc R_RISCV_SUB* with non-zero constant, and then report
warnings/errors in assembler.
bfd/
* elfnn-riscv.c (perform_relocation): Ignore the non-zero addend of
R_RISCV_SUB_ULEB128.
(riscv_elf_relocate_section): Report warnings to inform people need
to rebuild their stuff if --check-uleb128 is enabled. So that can
get the right non-zero addend of R_RISCV_SUB_ULEB128.
* elfxx-riscv.h (struct riscv_elf_params): Added bool check_uleb128.
ld/
* NEWS: Updated.
* emultempl/riscvelf.em: Added linker risc-v target options,
--[no-]check-uleb128, to enable/disable checking if the addend of
uleb128 is non-zero or not. So that people will know they need to
rebuild the objects with binutils 2.42 and up, to get the right zero
addend of SUB_ULEB128 relocation, or they may get troubles if using
.reloc.
* ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* ld/testsuite/ld-riscv-elf/pr31179*: New test cases.
Alan Modra [Tue, 26 Dec 2023 12:16:56 +0000 (22:46 +1030)]
asan: buffer overflow in loongarch_elf_rtype_to_howto
Seen when running ld-loongarch-elf/tlsdesc-dso test.
elfxx-loongarch.c:1844:32: runtime error: index 125 out of bounds for
type 'loongarch_reloc_howto_type [124]'
So either the loongarch_howto_table needs three more
LOONGARCH_EMPTY_HOWTO entries, or loongarch_elf_rtype_to_howto should
be testing for r_type < ARRAY_SIZE (loongarch_howto_table). I figure
it's worth wasting a little more space to get faster lookup.
* elfxx-loongarch.c (loongarch_howto_table): Add
LOONGARCH_EMPTY_HOWTO entries for 121..123.
(loongarch_elf_rtype_to_howto): Don't support slow lookup.
Assert exact table size and r_type indexing. Omit return cast.
(loongarch_reloc_name_lookup): Omit assertion and return cast.
(loongarch_reloc_type_lookup): Likewise.
Alan Modra [Tue, 26 Dec 2023 05:50:34 +0000 (16:20 +1030)]
PR31191, objcopy leaves temporary files
Fix the ENOTDIR rmdir too.
PR 31191
* objcopy.c (copy_archive): Localise uses of "l". Remove
const from name_list.name. Unlink output element on bfd_close
error, and NULL list->name to indicate file is removed. Adjust
cleanup to prevent rmdir on non-existent file.
Mike Frysinger [Wed, 27 Dec 2023 03:53:31 +0000 (22:53 -0500)]
sim: common: pull in newlib extensions for Linux compatibility
Since newlib allows people to opt-in to extra errno names, pull them
into our table too. The values don't conflict with each other -- the
newlib names & values are distinct from newlib's Linux compatibility.
Lulu Cai [Tue, 31 Oct 2023 08:11:56 +0000 (16:11 +0800)]
LoongArch: Add support for TLSDESC in ld.
1.The linker for each DESC generates a R_LARCH_TLS_DESC64 dynamic
relocation, which relocation is placed at .rela.dyn.
TLSDESC always allocates two GOT slots and one dynamic relocation
space to TLSDESC.
2. When using multiple ways to access the same TLS variable, a
maximum of 5 GOT slots are used. For example, using GD, TLSDESC,
and IE to access the same TLS variable, GD always uses the first
two of the five GOT, TLSDESC uses the third and fourth, and IE
uses the last.
Alan Modra [Sun, 24 Dec 2023 04:11:06 +0000 (14:41 +1030)]
Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">
This fixes the buffer overflow added in commit 22b78fad28, and a few
other problems.
* loongarch-coder.c (loongarch_split_args_by_comma): Don't
overflow buffer when args == "". Don't remove unbalanced
quotes. Don't trim last arg if max number of args exceeded.
Simon Marchi [Thu, 21 Dec 2023 16:51:38 +0000 (16:51 +0000)]
gdb: make value::allocate_register_lazy store id of next non-inline frame
Some spots loop on the frame chain to find the first next non-inline
frame, and pass that as the "next frame" to
value::allocate_register_lazy / value::allocate_register. This is
necessary if the value is used in the process of computing the id of
"this frame". If the frame next to "this frame" is inlined into "this
frame", then you that next frame won't have a computed id yet. You have
to go past that to find the next non-inline frame, which will have a
computed id.
In other cases, it's fine to store the id of an inline frame as the
"next frame id" in a register struct value. When trying to unwind a
register from it, it will just call inline_frame_prev_register, which
will forward the request to the next next frame, until we hit the next
physical frame.
I think it would make things simpler to just never store the id of an
inline frame as the next frame id of register struct values, and go with
the first next non-inline frame directly. This way, we don't have to
wonder which code paths have to skip inline frames when creating
register values and which don't.
So, change value::allocate_register_lazy to do that work, and remove the
loops for the callers that did it.
Simon Marchi [Sun, 24 Dec 2023 15:38:35 +0000 (10:38 -0500)]
gdb: remove VALUE_REGNUM, add value::regnum
Remove VALUE_REGNUM, replace it with a method on struct value. Set
`m_location.reg.regnum` directly from value::allocate_register_lazy,
which is fine because allocate_register_lazy is a static creation
function for struct value.
Remove VALUE_NEXT_FRAME_ID, replace it with a method on struct value. Set
`m_location.reg.next_frame_id` directly from value::allocate_register_lazy,
which is fine because allocate_register_lazy is a static creation
function for struct value.
Simon Marchi [Thu, 21 Dec 2023 16:32:55 +0000 (16:32 +0000)]
gdb: implement address_from_register using value_from_register
As explained in the comment removed by the previous commit "gdb: pass
non-nullptr frame to gdbarch_value_from_register in
address_from_register", address_from_register copies some implementation
bits from value_from_register:
/* This routine may be called during early unwinding, at a time
where the ID of FRAME is not yet known. Calling value_from_register
would therefore abort in get_frame_id. However, since we only need
a temporary value that is never used as lvalue, we actually do not
really need to set its VALUE_NEXT_FRAME_ID. Therefore, we re-implement
the core of value_from_register, but use the null_frame_id. */
This is no longer relevant, since we now create a value with a valid next
frame id, so change address_from_register to use value_from_register.
By now, all register struct values should have a valid next frame id
(assuming they are created using value::allocate_register or
value::allocate_register_lazy), so there should be no need to pass a
frame alongside the value to read_frame_register_value. Remove the
frame parameter and adjust read_frame_register_value accordingly.
While at it, make read_frame_register_value static, it's only used in
findvar.c.
Simon Marchi [Thu, 21 Dec 2023 16:21:52 +0000 (16:21 +0000)]
gdb: add type parameter to value::allocate_register and add value::allocate_register_lazy
Some places that create register struct values don't use register_type
to obtain the value type. This prevents them from using the current
version of value::allocate_register. One spot (value_of_register_lazy)
also creates a lazy register value.
Add a value::allocate_register_lazy method. Add some type parameters
to value::allocate_register and value::allocate_register_lazy, to let
the caller specify the type to use for the value. The parameters
default to nullptr, in which case we use register_type to obtain the
type.
Simon Marchi [Thu, 21 Dec 2023 16:10:17 +0000 (16:10 +0000)]
gdb: pass non-nullptr frame to gdbarch_value_from_register in address_from_register
address_from_register used to pass null_frame_id to
gdbarch_value_from_register as "this frame"'s id, because it's possible
for it to be called during unwind, when "this frame"'s id is not yet
known. This create an oddity where those register struct values are
created without a valid next frame id. I would much prefer for things
to be consistent and have all register struct values to have a valid
next frame id.
Since gdbarch_value_from_register takes a frame_info_ptr now, rather
than a frame_id, we can pass down "this frame", even if it doesn't have
a valid id. gdbarch_value_from_register implementations can obtain the
next frame from it.
However, it's possible for the "this frame"'s next frame to be an
inline frame, inlined in "this frame", in which case that next frame's
id is also not known. So, loop until we get to the next non-inline
frame (which is actually the frame where registers for "this frame" are
unwound from). This is the same thing that we do in
value_of_register_lazy, for the same reason. A later patch will factor
out this "while next frame is inline" loop to apply it to all register
struct values, so this is somewhat temporary.
Simon Marchi [Thu, 21 Dec 2023 16:03:02 +0000 (16:03 +0000)]
gdb: pass frame_info_ptr to gdbarch_value_from_register
Pass a frame_info_ptr rather than a frame_id. This avoids having to do
a frame lookup on the callee side, when we can just pass the frame down
directly.
I think this fixes a bug in rs6000-tdep.c where the id of the wrong
frame was set to `VALUE_NEXT_FRAME_ID (v)`.
Mike Frysinger [Sun, 24 Dec 2023 10:06:57 +0000 (05:06 -0500)]
sim: cgen: mark cgen_rtx_error noreturn
Since this function never returns, mark it as such to fix some unused
variable warnings in error code paths.
For example, cris triggers:
sim/cris/semcrisv10f-switch.c:3558:11: error:
variable 'tmp_newval' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized]
Even though it has an "else" path that calls this error function.
Mike Frysinger [Sun, 24 Dec 2023 08:59:02 +0000 (03:59 -0500)]
sim: sh: refine pwsb & pwad nops
Since these insns don't do anything and are effectively ignored,
return early to avoid doing any common processing at the end as
that requires initializing variables like "res" with something.
Mike Frysinger [Sun, 24 Dec 2023 08:53:03 +0000 (03:53 -0500)]
sim: sh: fix plds Dz,MACL implementation
The plds Dz,MACL insn stores the Dz bit into MACL. The current code
was storing the "res" variable into Dz and then into MACL, but not
setting "res" to anything. Delete that logic and make it match the
existing plds Dz,MACH insn.
Mike Frysinger [Fri, 22 Dec 2023 23:05:50 +0000 (18:05 -0500)]
sim: m32c: fix -Wshadow=local warnings
These decoders declare a lot of common variables for use by substeps,
and then shadows a few because of how the opc generator is implemented.
Easiest way around it is to rename the per-substep vars as needed as
anything more would require substantial changes to the opc logic.
Mike Frysinger [Sat, 23 Dec 2023 04:17:45 +0000 (23:17 -0500)]
sim: cris: disable -Wshadow=local in generated mloop files
The mloop files include CGEN generated switch files which have some
nested assignments that expand into repeated shadowed variables.
Fixing this looks fairly non-trivial as it appears to be interplay
between the common CGEN code and how this particular set of cris
insns are defined. Disable the warning instead.
In file included from sim/cris/mloop.in:286:
sim/cris/semcrisv10f-switch.c: In function ‘crisv10f_engine_run_full’:
sim/cris/semcrisv10f-switch.c:12383:8: error: declaration of ‘opval’ shadows a previous local [-Werror=shadow=local]
12383 | SI opval = tmp_addr;
| ^~~~~
sim/cris/semcrisv10f-switch.c:12371:9: note: shadowed declaration is here
12371 | USI opval = ({ SI tmp_addr;
| ^~~~~
And the code looks like:
USI opval = ({
...
{
SI opval = tmp_addr;
...
}
...
});
Since the CGEN code treats "opval" as an internal variable that the cpu
definitions don't have direct access to, the likelihood of this being a
real bug is low, so leave it be. The warning is suppressed for more code
that is hand written (e.g. the mloop logic), but disabling for the entire
file is the easiest way to suppress while keeping it on everywhere else in
the sim.
Mike Frysinger [Fri, 22 Dec 2023 01:03:41 +0000 (20:03 -0500)]
sim: arm: fix -Wshadow=local warnings
Remove duplicate nested variable declarations, rename some to avoid
confusion when the type is different or the original value should be
retained, and fix some weirdness with nested enums in structs.
Mike Frysinger [Fri, 22 Dec 2023 01:01:31 +0000 (20:01 -0500)]
sim: aarch64: fix -Wshadow=local warnings
These functions have local vars named "val" of type float, and
then create nested vars named "val" of type double. This is a
bit confusing and causes build time warnings.
Tom Tromey [Tue, 12 Dec 2023 17:09:55 +0000 (10:09 -0700)]
Avoid exception from attach in DAP
I noticed that the DAP attach test case (and similarly
remoted-dap.exp) had a rogue exception stack trace in the log. It
turns out that an attach will generate a stop that does not have a
reason.
This patch fixes the problem in the _on_stop event listener by making
it a bit more careful when examining the event reason. It also adds
some machinery so that attach stops can be suppressed, which I think
is the right thing to do.
Reviewed-By: Kévin Le Gouguec <legouguec@adacore.com>
Tom Tromey [Tue, 12 Dec 2023 16:30:41 +0000 (09:30 -0700)]
Add DAP log level parameter
This adds a new parameter to control the DAP logging level. By
default, "expected" exceptions are not logged, but the parameter lets
the user change this when more logging is desired.
This also changes a couple of spots to avoid logging the stack trace
for a DAPException.
This patch also documents the existing DAP logging parameter. I
forgot to document this before.
Reviewed-By: Eli Zaretskii <eliz@gnu.org> Reviewed-By: Kévin Le Gouguec <legouguec@adacore.com>
Tom Tromey [Tue, 12 Dec 2023 16:29:43 +0000 (09:29 -0700)]
Introduce and use DAPException
This introduces a new DAPException class, and then changes various
spots in the DAP implementation to wrap "expected" exceptions in this.
This class will help detect rogue exceptions caused by bugs in the
implementation.
Reviewed-By: Kévin Le Gouguec <legouguec@adacore.com>
Tom Tromey [Mon, 11 Dec 2023 17:04:23 +0000 (10:04 -0700)]
Fix build with clang 16
clang 16 reports a missing declaration in new-op.cc. We believed
these operators to be declared starting with C++14, but apparently
that is not the case.
This patch reverts the earlier change and then updates the comment to
reflect the current state.
Kévin Le Gouguec [Fri, 22 Dec 2023 13:06:15 +0000 (14:06 +0100)]
gdb: fix refactoring hiccup in rs6000_register_to_value
In 2023-12-14 "gdb: make get_frame_register_bytes take the next frame"
(9fc79b42369), *_register_to_value functions were made to (a) call
get_next_frame_sentinel_okay (frame) (b) pass that next frame to
get_frame_register_bytes.
Step (b) was omitted for rs6000-tdep.c; this manifests as a regression on
PPC platforms for e.g. O2_float_param: instead of seeing…
Temporary breakpoint 1, callee.increment (val=val@entry=99.0, msg=...) at callee.adb:19
… we get "optimized_out" for val. Passing next_frame to
get_frame_register_bytes fixes the issue.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Tom Tromey [Thu, 7 Dec 2023 16:51:52 +0000 (09:51 -0700)]
Add 'program' to DAP 'attach' request
In many cases, it's not possible for gdb to discover the executable
when a DAP 'attach' request is used. This patch lets the IDE supply
this information.
Guinevere Larsen [Tue, 16 May 2023 14:25:53 +0000 (16:25 +0200)]
gdb: add git trailer information on gdb/MAINTAINERS
The project has been using Tested-By (tb), Reviewed-By (rb) and
Approved-By (ab) for some time, but there has been no information to be
found in the actual repository. This commit changes that by adding
information about all git trailers to the MAINTAINERS file, so that it
can be easily double-checked. Simply put, the trailers in use work as
follows:
* Tested-by: The person tested the patch and it fixes the problem, or
introduces no regressions (or both).
* Acked-by: The general outline looks good, but the maintainer hasn't
looked at the code
* Reviewed-by: The code looks good, but the reviewer has not approved
the patch to go upstream
* Approved-by: The patch is ready to be pushed to master
These last 3 trailers can also be restricted to one or more areas of GDB
by adding the areas in a comma separated list in parenthesis after the
trailers.
Finally, for completeness sake, the trailers Co-Authored-By and Bug
were added, even though they have been in use for a long time already
Reviewed-By: Kevin Buettner <kevinb@redhat.com> Reviewed-By: Luis Machado <luis.machado@arm.com> Approved-By: John Baldwin <jhb@FreeBSD.org>
Jan Beulich [Fri, 22 Dec 2023 08:35:52 +0000 (09:35 +0100)]
hppa/ELF: fix .text/.data interaction with .previous
For some ELF targets .text/.data are overridden. In that case
obj_elf_{text,data}() need calling, just like .code vectors to that
function for the remaining ELF targets.
While there also hand on the function arguments, even if right now
they're meaningless. This matches what other targets' code does.
Jan Beulich [Fri, 22 Dec 2023 08:35:02 +0000 (09:35 +0100)]
RISC-V: drop .bss override
It doesn't look to be a good idea to override the custom handler that
ELF has; afaict doing so broke .previous, and a sub-section specifier
wasn't accepted either.
Jan Beulich [Fri, 22 Dec 2023 08:34:10 +0000 (09:34 +0100)]
x86-64: refuse "high" 8-bit regs with .insn and VEX/XOP/EVEX encodings
Much like REX, those encodings - if permitting 8-bit regs at all, i.e.
only starting with APX - permit use of "new" 8-bit registers only. %ah,
%ch, %dh, and %bh cannot be encoded and hence should be rejected.
Permit their use outside of 64-bit code though, as "new" registers
simply don't exist there.
Jan Beulich [Fri, 22 Dec 2023 08:33:12 +0000 (09:33 +0100)]
x86: properly respect rex/{rex}
This addresses two issues: For one, a user specified "rex" did not cause
the diagnostic to trigger when there was no other need for a REX prefix;
instead, another than the specified insn+operands was encoded. And then
(which is what this started from) .insn didn't respect {rex} (and was
otherwise similarly flawed as ordinary insns).
The latter requires splitting out code from md_assemble(), for it to
become re-usable. Besides the addition to address the first issue, that
code then also needs generalizing to account for immediate operands, as
with .insn we can't make assumptions anymore on all respective templates
having at most two operands (we still can build upon there being at most
two non-immediate operands, though). While moving the code also simplify
the first if(), by folding redundant checks.
In the new testcase also test a few more things which afaics weren't
tested till now.
Mike Frysinger [Wed, 20 Dec 2023 01:04:34 +0000 (20:04 -0500)]
sim: common: add $LINENO rewriting support to genmloop scripts
The generated mloop files can trigger compile time warnings. It can
be difficult to see/understand where the original code is coming from
as all the diagnostics point to the generated output. Using #line
pragmas, we can point people to the original source files.
Unfortunately, this code is written in POSIX shell, and that lacks
support for line number tracking. The $LINENO variable, even when
available, can just be plain wrong. For example, when using dash
and subshells, $LINENO can end up having negative values. Add a
wrapper script that will uses awk to rewrite the $LINENO variable
to the right value to avoid all that.
Basically lineno.sh takes an input script, rewrites all uses of
$LINENO into the actual line number (and $0 into the original file
name), and then executes the temporary script.
This commit doesn't actually add #line pragmas to any files. That
comes next.
Tom Tromey [Fri, 8 Dec 2023 17:32:07 +0000 (10:32 -0700)]
Rename TUI locator window -> status
The TUI status window is called the "locator" in the source, but
"status" in the documentation. Whenever I've needed to find the code,
I've had to search to "locate" it (ha, ha). This patch renames the
window to match the public name of the window.
Tom Tromey [Fri, 8 Dec 2023 17:14:41 +0000 (10:14 -0700)]
Rename tui-stack -> tui-status
The TUI status line is called the "status" window in the
documentation, but not in the source. There, the relevant files are
named "tui-stack", which to me makes it sound like they have something
to do with backtraces. This patch renames them to "tui-status".
Rainer Orth [Thu, 21 Dec 2023 11:51:26 +0000 (12:51 +0100)]
ld: Add lib32 directories for 32-bit emulation on FreeBSD/amd64
GNU ld currently fails to link 32-bit executables on FreeBSD/amd64 when
the linked libraries have dependencies on shared objects themselves:
$ gcc -m32 -o ei ei.c -lexecinfo
/var/gcc/binutils/amd64/lib/gcc/amd64-pc-freebsd14.0/13.2.0/../../../../amd64-pc-freebsd14.0/bin/ld:
warning: libelf.so.2, needed by /usr/lib/../lib32/libexecinfo.so, not found
(try using -rpath or -rpath-link)
/var/gcc/binutils/amd64/lib/gcc/amd64-pc-freebsd14.0/13.2.0/../../../../amd64-pc-freebsd14.0/bin/ld:
/usr/lib/../lib32/libexecinfo.so: undefined reference to `elf_begin@R1.0'
[...]
Pedro Alves [Thu, 21 Dec 2023 10:43:20 +0000 (10:43 +0000)]
Fix Clang build issue with flexible array member and non-trivial dtor
Commit d5cebea18e7a ("Make cached_reg_t own its data") added a
destructor to cached_reg_t.
That caused a build problem with Clang, which errors out like so:
> CXX python/py-unwind.o
> gdb/python/py-unwind.c:126:16: error: flexible array member 'reg' of type 'cached_reg_t[]' with non-trivial destruction
> 126 | cached_reg_t reg[];
> | ^
This is is not really a problem for our code, which allocates the
whole structure with xmalloc, and then initializes the array elements
with in-place new, and then takes care to call the destructor
manually. Like, commit d5cebea18e7a did:
for (int i = 0; i < cached_frame->reg_count; i++)
- xfree (cached_frame->reg[i].data);
+ cached_frame->reg[i].~cached_reg_t ();
Maybe we should get rid of the flexible array member and use a bog
standard std::vector. I doubt this would cause any visible
performance issue.
Meanwhile, to unbreak the build, this commit switches from C99-style
flexible array member to 0-length array. It behaves the same, and
Clang doesn't complain. I got the idea from here:
projects / thirdparty / binutils-gdb.git / log
