Olliver Schinagl [Wed, 21 Nov 2018 18:05:26 +0000 (20:05 +0200)]
sunxi: pmic_bus: Decrease boot time by not writing duplicate data
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
syscon: dm: Add a new method to get a regmap from DTS
syscon_regmap_lookup_by_phandle() can be used to get the regmap of a syscon
device from a reference in the DTS. It operates similarly to the linux
version of the namesake function.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
usb: dwc3: Fix a compilation error with the edison defconfig
The error is:
In file included from include/part.h:10:0,
from include/usb.h:18,
from include/linux/usb/gadget.h:22,
from drivers/usb/dwc3/ep0.c:20:
include/ide.h:62:14: error: unknown type name ‘uchar’
void ide_led(uchar led, uchar status);
Fixing it by including common.h that defines the uchar type.
The select_dr_mode operation is executed when the glue driver is probed.
The role of this optional function is to configure the operating mode
of the controller at the glue level.
dwc3-generic: Handle the PHYs, the clocks and the reset lines
This make the driver more generic. At this point this driver can replace
the dwc3-of-simple implementation.
Make the description in the Kconfig more generic too.
usb: gadget: Do not call board_usb_xxx() directly in USB gadget drivers
Add 2 functions to wrap the calls to board_usb_init() and
board_usb_cleanup().
This is a preparatory work for DM support for UDC drivers (DM_USB_GADGET).
Takeshi Kihara [Tue, 4 Dec 2018 03:51:01 +0000 (12:51 +0900)]
ARM: rcar_gen3: fix protection area access error
This patch fixes the problem that "main memory domain AXI secure access
protection error" occurs. Exclude the area (0x43f00000 to 0x47DFFFFF)
set by DBSC from the map area.
ARM: rcar_gen3: fix protection area access error at Cortex-A53
This patch fixes the problem that "main memory domain AXI secure
access protection error" occurs when booting Cortex-A53. Exclude
the area (0x43f00000 to 0x47DFFFFF) set by DBSC from the map area.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Felix Brack [Wed, 5 Dec 2018 13:53:42 +0000 (14:53 +0100)]
arm: dts: am33xx: Sync dts with Linux 4.20.0
This patch synchronizes the am33xx SoC specific files with those from
Linux 4.20.0. Hence all board maintainers of am33xx based boards are
on the cc list.
The main purpose of this patch is to prevent further diverging of the
dts files from U-Boot and those from Linux. It aims to set the stage
for the synchronization of board specific dts files. Example: I'm the
maintainer of the PDU001 board: once this patch is applied successfully
I will make changes to the board specific dts file in Linux only and
then post a patch with a copy of this exact dts file to U-Boot. This
will make U-Boot and Linux remain in sync.
The stumbling block of https://patchwork.ozlabs.org/patch/943627 was
removed by the patch https://patchwork.ozlabs.org/patch/962428 from
Lokesh Vutla (many thanks!). This omap-serial driver allows using the
Linux am33xx.dtsi file in U-Boot.
Other changes to dts and dtsi files made by this patch are mainly to
prevent _new_ warnings during the build process. Especially the warning
at pinmux@800 stating 'unnecessary #address-cells/#size-cells without
"ranges" or child "reg"' was not removed. This warning is a good example
showing the benefit of the synchronization: if it needs to be fixed it
will be fixed in Linux and ported back to U-Boot.
Buildman reports all 46 am33xx SoC based boards to build fine, with
warnings of course. Nevertheless this patch should be tested thoroughly
on as many boards as possible to prevent any collateral damage.
Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
Heiko Schocher [Wed, 5 Dec 2018 10:29:54 +0000 (11:29 +0100)]
spl/tpl: change banner into upper case
commit d6330064634a ("spl: Add a define for SPL_TPL_PROMPT")
changes the SPL/TPL banner from upper case into lower
case. As SPL and TPL are three-letter acronyms and they
are written in upper case, change it back to upper case.
Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Mon, 3 Dec 2018 09:52:51 +0000 (10:52 +0100)]
gpio: stm32f7: Add gpio bank holes management
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.
For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.
Felix Brack [Fri, 30 Nov 2018 09:23:36 +0000 (10:23 +0100)]
arm: am335x-pdu001: Enable CONFIG_BLK and CONFIG_DM_MMC
This patch enables CONFIG_BLK as well as CONFIG_DM_MMC for the PDU001
board. It depends on Patrice Chotard's patch 'power: regulator: denied
disable on always-on regulator' which prevents power cycling the vmmc
supply. Without this patch the board will not boot as vmmc is
unfortunately used by other board components, not just eMMC and micro SD
card. Furthermore my patch 'dts: am335x-pdu001: Fix polarity of card
detection input' is required to boot from external micro SD card. Without
this patch no SD card will be detected and hence booting will fail.
Signed-off-by: Felix Brack <fb@ltec.ch> Reviewed-by: Tom Rini <trini@konsulko.com>
Felix Brack [Thu, 29 Nov 2018 12:45:06 +0000 (13:45 +0100)]
dts: am335x-pdu001: Fix polarity of card detection input
When a micro SD card is inserted in the PDU001 card cage, the card
detection switch is opened and the corresponding GPIO input is driven
by a pull-up. Hence change the active level of the card detection
input from low to high.
ARM: at91: lds: add test for SPL binary size and bss size
Add test for the SPL binary size and the bss section size.
This will throw an error at build time if the SPL sections
do not fit in the designated RAM area, thus avoiding oversizing the SPL.
Based on original work by Wenyou Yang.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Carlo Caione [Thu, 6 Dec 2018 08:08:11 +0000 (08:08 +0000)]
pinctrl: meson: axg: Fix GPIO pin offsets
The pin number (first and last) in the bank definition is missing the
pin base offset shifting. This is causing a miscalculation when
retrieving the register and pin offsets in the GPIO driver causing the
'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip
(the AO bank is driven correctly because the shifting is already 0).
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Protect configuration registers with a hardware spinlock.
If a hwspinlock is defined in the device-tree node used it
to be sure that none of the others processors on the SoC could
change the configuration at the same time.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Keerthy [Tue, 27 Nov 2018 12:22:41 +0000 (17:52 +0530)]
board: ti: ks2_evm: Over ride spl_get_load_buffer function
Currently k2 spi boot is broken as the image header
is getting copied to an invalid memory location
CONFIG_SYS_TEXT_BASE - sizeof (struct image_size)
which maps to 0xc000000 - 0x40 = 0xbffffc0 being a reserved
location.
We cannot change the CONFIG_SYS_TEXT_BASE address as the single
stage boots like UART boot will need the address to be 0xc000000
hence override the spl_get_load_buffer to have image_header
address as CONFIG_SYS_TEXT_BASE aka 0xc000000
Philipp Tomsich [Mon, 26 Nov 2018 19:20:19 +0000 (20:20 +0100)]
clk: Allow clock defaults to be set during re-reloc state for SPL only
In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also
during re-reloc state") the earlier guard against setting clock
defaults in pre-reloc state was removed. While it is easy to filter
'assigned-clocks' properties for SPL using CONFIG_OF_SPL_REMOVE_PROPS,
no such mechanism exists for the pre-reloc stage of the full U-Boot.
With the default defconfig for the RK3399-Q7 (which filter the
'assigned-clocks' property for the DTS used by SPL anyway), this
caused a pause during startup of the full U-Boot stage that lasted for
almost 10s (due to the CPU not having been clocked up yet).
This reintroduces the guard from commit f4fcba5c5baa ("clk: Allow
clock defaults to be set also during re-reloc state") and extends it
to only apply outside of a TPL/SPL build: i.e. clk_set_defaults will
now run in pre-reloc state for SPL, but only after reloc for the full
U-Boot.
References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()")
References: commit e5e06b65ad65 ("clk: Allow clock defaults to be set
also during re-reloc state") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Patrick Wildt [Mon, 26 Nov 2018 14:58:13 +0000 (15:58 +0100)]
fs: fix FAT name extraction
The long name apparently can be accumulated using multiple
13-byte slots. Unfortunately we never checked how many we
can actually fit in the buffer we are reading to.
Patrick Wildt [Mon, 26 Nov 2018 14:56:57 +0000 (15:56 +0100)]
fs: check FAT cluster size
The cluster size specifies how many sectors make up a cluster. A
cluster size of zero makes no sense, as it would mean that the
cluster is made up of no sectors. This will later lead into a
division by zero in sect_to_clust(), so better take care of that
early.
The MAX_CLUSTSIZE define can reduced using a define to make some
room in low-memory system. Unfortunately if the code reads a
filesystem with a bigger cluster size it will overflow the buffer.
Priyanka Jain [Mon, 29 Oct 2018 09:11:29 +0000 (09:11 +0000)]
armv8:fsl-layerscape: Add support for Chassis 3.2
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.
Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Priyanka Jain [Thu, 11 Oct 2018 05:11:23 +0000 (05:11 +0000)]
board/freescale/vid: Add correction for ltc3882 read error.
Voltage regulator LTC3882 device has 0.5% voltage read error.
So for NXP SoC devices this generally equates to 2mV
Update set_voltage_to_LTC for below:
1.Add coorection of upto 2mV in voltage comparison
to take care of voltage read error of voltage regulator
2.Add loop max count kept as 100 to avoid infinte loop.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 16 Oct 2018 08:19:22 +0000 (16:19 +0800)]
arm: ls1021a: Add timer_init() in board_init_f for SPL
I2C is used to access DDR SPD in the DDR initialization for SPL. In
i2c_write process, get_timer() will be called. In board_init_f for SPL,
timer_init() is not called before. The system counter is not enabled and
the counter frequency is not set to 12.5MHz in SPL. The parameters for
do_div() are zero too.
It could not be found until CONFIG_USE_PRIVATE_LIBGCC is enabled in
default. When CONFIG_USE_PRIVATE_LIBGCC is enabled, U-Boot will use its
own set of libgcc functions. As the parameters for do_div() are zero,
__div0 will be called. Then the processor will stay in an endless loop
after calling hang().
This patch will add timer_init() in board_init_f for SPL and fix a
series of issues it caused.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Ma [Mon, 22 Oct 2018 02:43:21 +0000 (10:43 +0800)]
armv8: dts: fsl-ls2080a: add sata node support
One ls2080a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Ma [Mon, 22 Oct 2018 02:43:20 +0000 (10:43 +0800)]
scsi: ceva: add ls2080a soc support
Add ahci compatible support for ls2080a soc.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
[YS: add fallthrough comment] Reviewed-by: York Sun <york.sun@nxp.com>
Peng Ma [Mon, 22 Oct 2018 02:39:51 +0000 (10:39 +0800)]
arm64: ls1088a: enable DM support for sata
Enable related configs to support sata DM feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
[YS: moveconfig.py -s -d] Reviewed-by: York Sun <york.sun@nxp.com>
Peng Ma [Mon, 22 Oct 2018 02:39:50 +0000 (10:39 +0800)]
armv8: dts: fsl-ls1088a: add sata node support
One ls1088a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Peng Ma [Thu, 11 Oct 2018 10:34:20 +0000 (10:34 +0000)]
armv8: dts: fsl-ls1046a: add sata node support
One ls1046a, there is one SATA 3.0 advanced host controller interface
which is a high-performance SATA solution that delivers comprehensive
and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA
capabilities, in accordance with the serial ATA revision 3.0 of Serial
ATA International Organization.
Add sata node to support this feature.
Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:03:04 +0000 (18:03 +0000)]
armv8: ls1012aqds: Add TFABOOT support
TFABOOT support includes:
- ls1012aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:53 +0000 (18:02 +0000)]
armv8: ls1012ardb: Add TFABOOT support
TFABOOT support includes:
- ls1012ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- enable PFE validation for secure boot
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:48 +0000 (18:02 +0000)]
armv8: ls1043aqds: Add TFABOOT support
TFABOOT support includes:
- ls1043aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:44 +0000 (18:02 +0000)]
armv8: ls1043ardb: Add TFABOOT support
TFABOOT support includes:
- ls1043ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN and QE address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:40 +0000 (18:02 +0000)]
armv8: ls1046aqds: Add TFABOOT support
TFABOOT support includes:
- ls1046aqds_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:36 +0000 (18:02 +0000)]
armv8: ls1046ardb: Add TFABOOT support
TFABOOT support includes:
- ls1046ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- FMAN address changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Rajesh Bhagat [Mon, 5 Nov 2018 18:02:28 +0000 (18:02 +0000)]
drivers: qe: add TFABOOT support
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.
Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: remove line continuation in quoted string] Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 5 Nov 2018 18:02:09 +0000 (18:02 +0000)]
armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.
projects / thirdparty / u-boot.git / log
