jakub [Sat, 1 Jul 2017 10:11:16 +0000 (10:11 +0000)]
PR sanitizer/81262
* bb-reorder.c (fix_up_fall_thru_edges): Move variable declarations to
the right scopes, make sure cond_jump isn't preserved between multiple
iterations. Search for fallthru edge whenever there are 3+ edges and
use find_fallthru_edge for it.
jakub [Sat, 1 Jul 2017 08:16:27 +0000 (08:16 +0000)]
PR sanitizer/81262
* bb-reorder.c (fix_up_fall_thru_edges): Move variable declarations to
the right scopes, make sure cond_jump isn't preserved between multiple
iterations. Search for fallthru edge whenever there are 3+ edges and
use find_fallthru_edge for it.
* gcc.c-torture/compile/pr81262.c: New test.
* g++.dg/ubsan/pr81262.C: New test.
rearnsha [Fri, 30 Jun 2017 16:36:57 +0000 (16:36 +0000)]
[rtlanal] Do a better job of costing parallel sets containing flag-setting operations.
Many parallel set insns are of the form of a single set that also sets
the condition code flags. In this case the cost of such an insn is
normally the cost of the part that doesn't set the flags, since
updating the condition flags is simply a side effect.
At present all such insns are treated as having unknown cost (ie 0)
and combine assumes that such insns are infinitely more expensive than
any other insn sequence with a non-zero cost.
This patch addresses this problem by allowing insn_rtx_cost to ignore
the condition setting part of a PARALLEL iff there is exactly one
comparison set and one non-comparison set. If the only set operation
is a comparison we still use that as the basis of the insn cost.
* rtlanal.c (insn_rtx_cost): If a parallel contains exactly one
comparison set and one other set, use the cost of the non-comparison
set.
bergner [Fri, 30 Jun 2017 16:04:08 +0000 (16:04 +0000)]
* tree-cfg.c (group_case_labels_stmt): Merge scanning and compressing
loops. Remove now unneeded calls to gimple_switch_set_label() that
just set removed labels to NULL_TREE.
aldyh [Fri, 30 Jun 2017 15:36:41 +0000 (15:36 +0000)]
* tree-ssanames.c (set_range_info_raw): Abstract from ...
(set_range_info): ...here. Only call set_range_info_raw if domain
is useful.
(set_nonzero_bits): Call set_range_info_raw.
* tree-ssanames.h (set_range_info_raw): New.
testsuite/
* gcc.dg/Walloca-14.c: Adapt test to recognize new complaint of
unbounded use.
jakub [Fri, 30 Jun 2017 14:52:24 +0000 (14:52 +0000)]
PR target/81225
* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For
V8FI, V16FI and VI8F_256 iterators, use <store_mask_predicate> instead
of nonimmediate_operand and <store_mask_constraint> instead of m for
the input operand. For V8FI iterator, always split if input is a MEM.
For V16FI and V8SF_256 iterators, don't test if both operands are MEM
if <mask_applied>. For VI4F_256 iterator, use <store_mask_predicate>
instead of register_operand and <store_mask_constraint> instead of v for
the input operand. Make sure both operands aren't MEMs for if not
<mask_applied>.
rguenth [Fri, 30 Jun 2017 13:19:29 +0000 (13:19 +0000)]
2017-06-30 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_slp_analyze_node_operations): Only
analyze the first scalar stmt. Move vector type computation
for the BB case here from ...
* tree-vect-stmts.c (vect_analyze_stmt): ... here. Guard
live operation processing in the SLP case properly.
nathan [Fri, 30 Jun 2017 13:11:01 +0000 (13:11 +0000)]
* call.c (build_new_method_call_1): Use constructo_name to get
ctor name. Move argument processing earlier to merge cdtor
handling blocks.
* decl.c (grokfndecl): Cdtors have special names.
* method.c (implicitly_declare_fn): Likewise. Simplify flag setting.
* pt.c (check_explicit_specialization): Cdtor name is already
special.
* search.c (class_method_index_for_fn): Likewise.
* g++.dg/plugin/decl-plugin-test.C: Expect special ctor name.
krebbel [Fri, 30 Jun 2017 06:45:51 +0000 (06:45 +0000)]
S/390: Adjust to the recent branch probability changes.
This fixes the bootstrap failure triggered by the recent changes wrt
branch probabilities aka emit_cmp_and_jump_insns does not accept
integers as branch probability anymore.
gcc/ChangeLog:
2017-06-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.c (s390_expand_setmem): Adjust to the new data
type for branch probabilities.
naveenh [Fri, 30 Jun 2017 03:58:48 +0000 (03:58 +0000)]
2017-06-29 Julian Brown <julian@codesourcery.com>
Naveen H.S <Naveen.Hurugalawadi@cavium.com>
* config/aarch64/aarch64-fusion-pairs.def: Add ALU_BRANCH entry.
* config/aarch64/aarch64.c (AARCH64_FUSE_ALU_BRANCH): New fusion type.
(thunderx2t99_tunings): Set AARCH64_FUSE_ALU_BRANCH flag.
(aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_ALU_BRANCH.
* config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Push the
check for CC usage into AARCH64_FUSE_CMP_BRANCH.
* config/i386/i386.c (ix86_macro_fusion_pair_p): Push the check for
CC usage from generic code to here.
* sched-deps.c (sched_macro_fuse_insns): Move the condition for
CC usage into the target macros.
* config/rs6000/rs6000.c (toc_relative_expr_p): Make tocrel_base
and tocrel_offset be pointer args rather than implicitly using
static versions.
(legitimate_constant_pool_address_p, rs6000_emit_move,
const_load_sequence_p, adjust_vperm): Add local tocrel_base and
tocrel_offset and use in toc_relative_expr_p call.
(print_operand, print_operand_address): Use static tocrel_base_oac
and tocrel_offset_oac.
(rs6000_output_addr_const_extra): Use static tocrel_base_oac and
tocrel_offset_oac.
ebotcazou [Thu, 29 Jun 2017 19:21:25 +0000 (19:21 +0000)]
* expr.c (expand_expr) <normal_inner_ref>: When testing for unaligned
objects, take into account only the alignment of 'op0' and 'mode1' if
'op0' is a MEM.
sje [Thu, 29 Jun 2017 18:20:14 +0000 (18:20 +0000)]
2017-06-29 Steve Ellcey <sellcey@cavium.com>
* ccmp.c (ccmp_tree_comparison_p): New function.
(ccmp_candidate_p): Update to use above function.
(get_compare_parts): New function.
(expand_ccmp_next): Update to use new functions.
(expand_ccmp_expr_1): Take tree arg instead of gimple, update to use
new functions.
(expand_ccmp_expr): Pass tree instead of gimple to expand_ccmp_expr_1,
take mode as argument.
* ccmp.h (expand_ccmp_expr): Add mode as argument.
* expr.c (expand_expr_real_1): Pass mode as argument.
nathan [Thu, 29 Jun 2017 18:20:13 +0000 (18:20 +0000)]
PR c++/81247
* parser.c (cp_parser_namespace_definition): Immediately close the
namespace if there's no open-brace.
* name-lookup.c (do_pushdecl): Reset OLD when pushing into new
namespace.
segher [Thu, 29 Jun 2017 17:28:47 +0000 (17:28 +0000)]
combine: Print insns with the cost dump
In the combine dump file, at the start there is a list of the RTL cost
of every insn. The only thing listed about the insns is the UID though.
To make it more useful, this patch prints the insn itself as well (in
slim format).
* combine.c (combine_instructions): Print insns to dump_file, together
with their costs.
nathan [Thu, 29 Jun 2017 14:49:46 +0000 (14:49 +0000)]
* cp-tree.h (THIS_NAME, IN_CHARGE_NAME, VTBL_PTR_TYPE,
VTABLE_DELTA_NAME, VTABLE_PFN_NAME): Delete.
* decl.c (initialize_predefined_identifiers): Name cdtor special
names consistently. Use literals for above deleted defines.
(cxx_init_decl_processing): Use literal for vtbl_ptr_type name,
nathan [Thu, 29 Jun 2017 14:38:09 +0000 (14:38 +0000)]
* call.c (check_dtor_name): Use constructor_name for enums too.
(build_new_method_call_1): Use constructor_name for cdtors and
show ~ for dtor.
* class.c (build_self_reference): Use TYPE_NAME to get name of
self reference.
* name-lookup (constructor_name): Use DECL_NAME directly.
(constructor_name_p): Reimplement.
(push_class_level_binding_1): Use TYPE_NAME directly.
rguenth [Thu, 29 Jun 2017 14:04:02 +0000 (14:04 +0000)]
2017-06-29 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_analyze_scalar_cycles_1): Do not add
reduction chains to LOOP_VINFO_REDUCTIONS.
* tree-vect-slp.c (vect_analyze_slp): Continue looking for
SLP reductions after processing reduction chains.
bergner [Thu, 29 Jun 2017 12:58:32 +0000 (12:58 +0000)]
gcc/
PR middle-end/81194
* cfgexpand.c (expand_gimple_stmt_1): Handle switch statements
with only one label.
* stmt.c (expand_case): Assert NCASES is greater than one.
gcc/testsuite/
PR middle-end/81194
* g++.dg/pr81194.C: New test.
rguenth [Thu, 29 Jun 2017 11:25:29 +0000 (11:25 +0000)]
2017-06-29 Richard Biener <rguenther@suse.de>
* tree-cfg.c (group_case_labels_stmt): Return whether we changed
anything.
(group_case_labels): Likewise.
(find_taken_edge): Push sanity checking on val to workers...
(find_taken_edge_cond_expr): ... here
(find_taken_edge_switch_expr): ... and here, handle cases
with just a default label.
* tree-cfg.h (group_case_labels_stmt): Adjust prototype.
(group_case_labels): Likewise.
* tree-cfgcleanup.c (execute_cleanup_cfg_post_optimizing): When
group_case_labels does anything cleanup the CFG again.
rearnsha [Thu, 29 Jun 2017 10:24:04 +0000 (10:24 +0000)]
[arm] Fix bootstrap - missing initializer in tail entry of autogenerated code
My patch yesterday accidentally missed a hunk that added the
update to the tail entry of the autogenerated data structure
produced by parsecpu.awk. This causes native bootstraps to
fail.
This patch adds back the missing hunk.
2017-06-29 Richard Earnshaw <rearnsha@arm.com>
* config/arm/parsecpu.awk (gen_comm_data): Add initializer for
profile to the dummy entry at the end of the list of architectures.
* config/arm/arm-cpu-cdata.h: Regenerated.
collison [Thu, 29 Jun 2017 09:21:57 +0000 (09:21 +0000)]
2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Michael Collison <michael.collison@arm.com>
PR target/70119
* config/aarch64/aarch64.md (*aarch64_<optab>_reg_<mode>3_mask1):
New pattern.
(*aarch64_reg_<mode>3_neg_mask2): New pattern.
(*aarch64_reg_<mode>3_minus_mask): New pattern.
(*aarch64_<optab>_reg_di3_mask2): New pattern.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Account for cost
of shift when the shift amount is masked with constant equal to
the size of the mode.
* config/aarch64/predicates.md (subreg_lowpart_operator): New
predicate.
2017-06-29 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Michael Collison <michael.collison@arm.com>
PR target/70119
* gcc.target/aarch64/var_shift_mask_1.c: New test.
ramana [Wed, 28 Jun 2017 22:09:50 +0000 (22:09 +0000)]
[AArch64] Do not increase data alignment at -Os and with -fconserve-stack.
We unnecessarily align data to 8 byte alignments even when -Os is
specified. This brings the logic in the AArch64 backend more in line
with the ARM backend and helps gain some image size in a few
places. Caught by an internal report on the size of rodata sections
being high with aarch64 gcc.
* config/aarch64/aarch64.h (AARCH64_EXPAND_ALIGNMENT): New.
(DATA_ALIGNMENT): Update to use AARCH64_EXPAND_ALIGNMENT.
(LOCAL_ALIGNMENT): Update to use AARCH64_EXPAND_ALIGNMENT.
Bootstrapped and regression tested on aarch64-none-linux-gnu with no
regressions.
thopre01 [Wed, 28 Jun 2017 15:09:08 +0000 (15:09 +0000)]
[ARM] Consistently check for neon in vect effective targets
Conditions checked for ARM targets in vector-related effective targets
are inconsistent:
* sometimes arm*-*-* is checked
* sometimes Neon is checked
* sometimes arm_neon_ok and sometimes arm_neon is used for neon check
* sometimes check_effective_target_* is used, sometimes
* is-effective-target
This patch consolidate all of these check into using is-effective-target
arm_neon and when little endian was checked, the check is kept.
2017-06-28 Thomas Preud'homme <thomas.preudhomme@arm.com>
rearnsha [Wed, 28 Jun 2017 15:02:38 +0000 (15:02 +0000)]
[arm] Fix incorrect __ARM_ARCH_PROFILE for -march=armv7
ACLE explicitly states that when targetting the common subset of
ARMv7-A, ARMv7-R and ARMv7-M, the __ARM_ARCH_PROFILE macro should not
be set. We currently set it to 'M' which is clearly erroneous.
The logic for creating this is very convoluted and also somewhat
fragile, so I've taken the opportunity to use the new CPU and
architecture definition infrastructure to record the profile for each
architecture explicitly rather than try to reconstruct it from other
data. I think this results in a much more robust solution.
2017-06-28 Richard Earnshaw <rearnsha@arm.com>
* config/arm/parsecpu.awk (profile): Parse new keyword in an arch
context.
(gen_comm_data): Emit architectural setting of arch_prof.
* config/arm/arm-cpus.in (armv6-m, armv6s-m, armv7-a, armv7ve): Set the
profile.
(armv7-r, armv7-m, armv7e-m, armv8-a, armv8.1-a, armv8.2-a): Likewise.
(armv8-m.base, armv8-m.main): Likewise.
* arm-protos.h (arm_build_target): Add profile field.
(arch_option): Likewise.
* config/arm/arm.c (arm_configure_build_target): Copy the profile to
the active target.
* config/arm/arm.h (TARGET_ARM_ARCH_PROFILE): Use
arm_active_target.profile.
rguenth [Wed, 28 Jun 2017 14:24:00 +0000 (14:24 +0000)]
2017-06-28 Richard Biener <rguenther@suse.de>
PR middle-end/81227
* fold-const.c (negate_expr_p): Use TYPE_UNSIGNED, not
TYPE_OVERFLOW_WRAPS.
* match.pd (negate_expr_p): Likewise.
* tree-ssa-reassoc.c (optimize_range_tests_diff): Use
fold_build2, not fold_binary.
wilco [Wed, 28 Jun 2017 14:21:04 +0000 (14:21 +0000)]
This patch fixes a failure in gcc.target/aarch64/reload-valid-spoff.c
triggered by https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01367.html.
In ILP32 all memory accesses must have Pmode as the base address, but
aarch64_expand_mov_immediate wasn't emitting a conversion in one case.
Besides fixing this add an assert that flags any MEM operands that are
not Pmode.
gcc/
* config/aarch64/aarch64 (aarch64_expand_mov_immediate):
Convert memory address to Pmode.
(aarch64_print_operand): Assert MEM operands are always Pmode.
wilco [Wed, 28 Jun 2017 14:13:02 +0000 (14:13 +0000)]
Improve Cortex-A53 shift bypass
The aarch_forward_to_shift_is_not_shifted_reg bypass always returns true
on AArch64 shifted instructions. This causes the bypass to activate in
too many cases, resulting in slower execution on Cortex-A53 like reported
in PR79665.
This patch uses the arm_no_early_alu_shift_dep condition instead which
improves the example in PR79665 by ~7%. Given it is no longer used,
remove aarch_forward_to_shift_is_not_shifted_reg. Also remove an
unnecessary REG_P check.
meissner [Wed, 28 Jun 2017 13:07:12 +0000 (13:07 +0000)]
[gcc]
2017-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
PR ipa/81238
* multiple_target.c (create_dispatcher_calls): Set the default
clone to be static, not public.
[gcc/testsuite]
2017-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* lib/target-supports.exp
(check_ppc_cpu_supports_hw_available): New test to make sure
__builtin_cpu_supports works on power7 and newer.
jsm28 [Wed, 28 Jun 2017 09:21:16 +0000 (09:21 +0000)]
Use ucontext_t not struct ucontext in linux-unwind.h files.
Current glibc no longer gives the ucontext_t type the tag struct
ucontext, to conform with POSIX namespace rules. This requires
various linux-unwind.h files in libgcc, that were previously using
struct ucontext, to be fixed to use ucontext_t instead. This is
similar to the removal of the struct siginfo tag from siginfo_t some
years ago.
This patch changes those files to use ucontext_t instead. As the
standard name that should be unconditionally safe, so this is not
restricted to architectures supported by glibc, or conditioned on the
glibc version.
Tested compilation together with current glibc with glibc's
build-many-glibcs.py.
jakub [Wed, 28 Jun 2017 08:05:20 +0000 (08:05 +0000)]
* gcc.target/i386/cmov7.c (sgn): Renamed to ...
(foo): ... this. Change constants such that it isn't matched
as __builtin_copysign, yet tests the combiner the same.
projects / thirdparty / gcc.git / log
