Tom Tromey [Fri, 31 Mar 2023 15:17:13 +0000 (09:17 -0600)]
Fix maybe-uninitialized warning in frame.c
A recent patch caused my system gcc (Fedora 36, so gcc 12.2.1) to warn
about sym_addr being possibly uninitialized in frame.c. It isn't, but
the compiler can't tell. So, this patch initializes the variable. I
also fixed a formatting buglet that I missed in review.
Tom de Vries [Fri, 31 Mar 2023 15:15:37 +0000 (17:15 +0200)]
[gdb/testsuite] Fix gdb.base/trace-commands.exp with editing off
With test-case gdb.base/trace-commands.exp and editing off, I run into fails
because multi-line commands are issued using gdb_test_sequence, which
doesn't handle them correctly.
Tom de Vries [Fri, 31 Mar 2023 15:15:37 +0000 (17:15 +0200)]
[gdb/testsuite] Fix gdb.threads/threadapply.exp with editing off
With test-case gdb.threads/threadapply.exp and editing set to on, we have:
...
(gdb) define remove^M
Type commands for definition of "remove".^M
End with a line saying just "end".^M
>remove-inferiors 3^M
>end^M
(gdb)
...
but with editing set to off, we run into:
...
(gdb) define remove^M
Type commands for definition of "remove".^M
End with a line saying just "end".^M
>remove-inferiors 3^M
end^M
>(gdb) FAIL: gdb.threads/threadapply.exp: thread_set=all: try remove: \
define remove (timeout)
...
The commands are issued by this test:
...
gdb_define_cmd "remove" {
"remove-inferiors 3"
}
...
which does:
- gdb_test_multiple "define remove", followed by
- gdb_test_multiple "remove-inferiors 3\nend".
Proc gdb_test_multiple has special handling for multi-line commands, which
splits it up into subcommands, and for each subcommand issues it and then
waits for the resulting prompt (the secondary prompt ">" for all but the last
subcommand).
However, that doesn't work as expected in this case because the initial
gdb_test_multiple "define remove" fails to match all resulting output, and
consequently the secondary prompt resulting from "define remove" is counted as
if it was the one resulting from "remove-inferiors 3".
Fix this by matching the entire output of "define remove", including the
secondary prompt.
Tom Tromey [Wed, 29 Mar 2023 19:51:13 +0000 (13:51 -0600)]
Remove language_demangle
I noticed that language_demangle shadows the global
"current_language". When I went to fix this, though, I then saw that
language_demangle is only called in two places, and has a comment
saying it should be removed. This patch removes it. Note that the
NULL check in language_demangle is not needed by either of the
existing callers.
Regression tested on x86-64 Fedora 36.
Approved-By: Simon Marchi <simon.marchi@efficios.com>
Tom Tromey [Fri, 24 Mar 2023 21:53:22 +0000 (15:53 -0600)]
Fix race in background index-cache writing
Tom de Vries pointed out a bug in the index-cache background writer --
sometimes it will fail. He also noted that it fails when the number
of worker threads is set to zero. These turn out to be the same
problem -- the cache can't be written to until the per-BFD's
"index_table" member is set.
This patch avoids the race by rearranging the code slightly, to ensure
the cache cannot possibly be written before the member is set.
Fix a functional regression and restore the handling of DW_CC_program
code of DW_AT_calling_convention attribute for determining the name of
the starting function of the program where the DW_AT_main_subprogram
attribute has not been provided, such as with Fortran code compiled with
GCC versions 4.5.4 and below, or where DWARF version 3 or below has been
requested. Without it "main" is considered the starting function. Cf.
GCC PR fortran/43414.
Original code was removed with commit 6209cde4ddb8 ("Delete DWARF
psymtab code"), and then an update to complement commit 81873cc81eff
("[gdb/symtab] Support DW_AT_main_subprogram with -readnow.") has also
been included here.
Richard Bunt [Fri, 31 Mar 2023 14:31:40 +0000 (15:31 +0100)]
GDB: Favor full symbol main name for backtrace stop
In the case where a Fortran program has a program name of "main" and
there is also a minimal symbol called main, such as with programs built
with GCC version 4.4.7 or below, the backtrace will erroneously stop at
the minimal symbol rather than the user specified main, e.g.:
(gdb) bt
#0 bar () at .../gdb/testsuite/gdb.fortran/backtrace.f90:17
#1 0x0000000000402556 in foo () at .../gdb/testsuite/gdb.fortran/backtrace.f90:21
#2 0x0000000000402575 in main () at .../gdb/testsuite/gdb.fortran/backtrace.f90:31
#3 0x00000000004025aa in main ()
(gdb)
This patch fixes this issue by increasing the precedence of the full
symbol when the language of the current frame is Fortran.
Newer versions of GCC transform the program name to "MAIN__" in this
case, avoiding the problem.
Co-Authored-By: Maciej W. Rozycki <macro@embecosm.com>
Tsukasa OI [Sat, 8 Oct 2022 03:48:24 +0000 (03:48 +0000)]
RISC-V: Allocate "various" operand type
This commit intends to move operands that require very special handling or
operand types that are so minor (e.g. only useful on a few instructions)
under "W". I also intend this "W" to be "temporary" operand storage until
we can find good two character (or less) operand type.
In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved
to "Wif" because of its special handling (and allocating single character
"f" for this operand type seemed too much).
Current expected allocation guideline is as follows:
1. 'W'
2. The most closely related single-letter extension in lowercase
(strongly recommended but not mandatory)
3. Identify operand type
The author currently plans to allocate following three-character operand
types (for operands including instructions from unratified extensions).
1. "Wif" ('Zicbop': fetch offset)
2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions)
3. "Wfm" / "WfM"
'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling
solely for widening conversion instructions.
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from
"f" to "Wif".
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Move from "f" to "Wif".
* riscv-opc.c (riscv_opcodes): Reflect new operand type.
Jan Beulich [Fri, 31 Mar 2023 06:26:06 +0000 (08:26 +0200)]
x86: convert testcases to use .insn
This can't be done for all insns currently encoded with .byte. For one
outside of 64-bit mode unused (typically ignored) register encoding bits
in VEX/XOP/EVEX prefixes can't be set to their non-default values, since
the necessary registers cannot be specified (and some of these bits
can't even be used outside of 64-bit mode). And then there are odd tests
like the first one in bad-bcast.s: Its purpose is to illegaly set EVEX.b
together with EVEX.W (which could be expressed; note though EVEX.W set
is invalid on its own), but then it also clears EVEX.B and EVEX.R' plus
it sets EVEX.vvvv to other than 0xf (rendering the test ambiguous,
because that's another #UD reason).
In {,x86-64-}disassem.s many bogus encodings exist - some with ModR/M
byte but insufficient displacement bytes, some using SIB encoding with
the SIB byte actually being the supposed immediate. Some of these could
be expressed by .insn, but I don't want to introduce bogus examples.
These will all need adjustment anyway once the disassembler is improved
in the way it deals with unrecognized encodings.
Generally generated code is meant to remain the same. {,x86-64-}nops.d
are exceptions because insn prefixes are emitted in a different order.
opcode{,-intel,-suffix}.d are also adjusted (along with an according
correction to opcode.s) to cover an apparent typo in the original tests
(xor when or was meant).
Where necessary --divide is added as gas option, to allow for the use
of the extension opcode functionality.
Comments are being adjusted where obviously wrong/misleading.
Jan Beulich [Fri, 31 Mar 2023 06:22:28 +0000 (08:22 +0200)]
x86: handle immediate operands for .insn
Since we have no insn suffix and it's also not realistic to infer
immediate size from the size of other (typically register) operands
(like optimize_imm() does), and since we also don't have a template
telling us permitted size(s), a new syntax construct is introduced to
allow size (and signedness) specification. In the absence of such, the
size is inferred from significant bits (which obviously may yield
inconsistent results at least for effectively negative values, depending
on whether BFD64 is enabled), and only if supplied expressions can be
evaluated at parsing time. Being explicit is generally recommended to
users.
Size specification is permitted at bit granularity, but of course the
eventually emitted immediate values will be padded up to 8-, 16-, 32-,
or 64-bit fields.
Jan Beulich [Fri, 31 Mar 2023 06:21:30 +0000 (08:21 +0200)]
x86: handle EVEX Disp8 for .insn
In particular the scaling factor cannot always be determined from pre-
existing operand attributes. Introduce a new {:d<N>} vector operand
syntax extension, restricted to .insn only, to allow specifying this in
(at least) otherwise ambiguous cases.
Jan Beulich [Fri, 31 Mar 2023 06:21:05 +0000 (08:21 +0200)]
x86: process instruction operands for .insn
Deal with register and memory operands; immediate operands will follow
later, as will the handling of EVEX embedded broadcast and EVEX Disp8
scaling.
Note that because we can't really know how to encode their use, %cr8 and
up cannot be used with .insn outside of 64-bit mode. Users would need to
specify an explicit LOCK prefix in combination with %cr0 etc.
Jan Beulich [Fri, 31 Mar 2023 06:20:22 +0000 (08:20 +0200)]
x86: parse special opcode modifiers for .insn
So called "short form" encoding is specified by a trailing "+r", whereas
a possible extension opcode is specified by the usual "/<digit>". Take
these off the expression before handing it to get_absolute_expression().
Note that on targets where / starts a comment, --divide needs passing to
gas in order to make use of the extension opcode functionality.
Jan Beulich [Fri, 31 Mar 2023 06:19:58 +0000 (08:19 +0200)]
x86: parse VEX and alike specifiers for .insn
All encoding spaces can be used this way; there's a certain risk that
the bits presently reserved could be used for other purposes down the
road, but people using .insn are expected to know what they're doing
anyway. Plus this way there's at least _some_ way to have those bits
set.
For now this will only allow operand-less insns to be encoded this way.
Jan Beulich [Fri, 31 Mar 2023 06:15:53 +0000 (08:15 +0200)]
Arm64/ELF: accept relocations against STN_UNDEF
While only a secondary issue there, the testcase of PR gas/27212 exposes
an oversight in relocation handling: Just like e.g. Arm32, which has a
similar comment and a similar check, relocations against STN_UNDEF have
to be permitted to satisfy the ELF spec.
Kevin Buettner [Fri, 10 Mar 2023 22:27:43 +0000 (15:27 -0700)]
PR gdb/30219: Clear sync_quit_force_run in quit_force
PR 30219 shows an internal error due to a "Bad switch" in
print_exception() in gdb/exceptions.c. The switch in question
contains cases for RETURN_QUIT and RETURN_ERROR, but is missing a case
for the recently added RETURN_FORCED_QUIT. This commit adds that case.
Making the above change allows the errant test case to pass, but does
not fix the underlying problem, which I'll describe shortly. Even
though the addition of a case for RETURN_FORCED_QUIT isn't the actual
fix, I still think it's important to add this case so that other
situations which lead to print_exeption() being called won't generate
that "Bad switch" internal error.
In order to understand the underlying problem, please examine
this portion of the backtrace from the bug report:
The real problem is in quit_force; here's the try/catch which
eventually leads to the internal error:
/* Get out of tfind mode, and kill or detach all inferiors. */
try
{
disconnect_tracing ();
for (inferior *inf : all_inferiors ())
kill_or_detach (inf, from_tty);
}
catch (const gdb_exception &ex)
{
exception_print (gdb_stderr, ex);
}
While running the calls in the try-block, a QUIT check is being
performed. This check finds that sync_quit_force_run is (still) set,
causing a gdb_exception_forced_quit to be thrown. The exception
gdb_exception_forced_quit is derived from gdb_exception, causing
exception_print to be called. As shown by the backtrace,
print_exception is then called, leading to the internal error.
The actual fix, also implemented by this commit, is to clear
sync_quit_force_run along with the quit flag. This will allow the
various cleanup code, called by quit_force, to run without triggering
a gdb_exception_forced_quit. (Though, if another SIGTERM is sent to
the gdb process, these flags will be set again and a QUIT check in the
cleanup code will detect it and throw the exception.)
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=30219 Approved-By: Simon Marchi <simon.marchi@efficios.com>
This patch adds the RPRFM (range prefetch) instruction.
It was introduced as part of SME2, but it belongs to the
prefetch hint space and so doesn't require any specific
ISA flags.
The aarch64_rprfmop_array initialiser (deliberately) only
fills in the leading non-null elements.
This patch adds the SVE FDOT, SDOT and UDOT instructions,
which are available when FEAT_SME2 is implemented. The patch
also reorders the existing SVE_Zm3_22_INDEX to keep the
operands numerically sorted.
This patch adds SUNPK and UUNPK, which unpack one register's
worth of elements to two registers' worth, or two registers'
worth to four registers' worth.
- SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two
or four registers.
- SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of
four registers.
These are the first SME2 instructions to have immediate operands.
The patch makes sure that, when parsing SME2 instructions with
immediate operands, the new predicate-as-counter registers are
parsed as registers rather than as #-less immediates.
aarch64: Add the SME2 FP<->int conversion instructions
This patch adds the SME2 versions of the FP<->integer conversion
instructions FCVT* and *CVTF. It also adds FP rounding instructions
FRINT*, which share the same format.
BFDOT, FDOT and USDOT share the same instruction format.
SDOT and UDOT share a different format. SUDOT does not
have the multi vector x multi vector forms, since they
would be redundant with USDOT.
aarch64: Add the SME2 MLALL and MLSLL instructions
SMLALL, SMLSLL, UMLALL and UMLSLL have the same format.
USMLALL and SUMLALL allow the same operand types as those
instructions, except that SUMLALL does not have the multi-vector
x multi-vector forms (which would be redundant with USMLALL).
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding. They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets. As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
aarch64: Add the SME2 maximum/minimum instructions
This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM}
and {S,U}{MAX,MIN}. SQDMULH, SRSHL and URSHL have the same form
as SMAX etc., so the patch adds them too.
Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.
The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.
These are the first instructions to have tied register list
operands, as opposed to tied single registers.
The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.). It means that:
Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
becomes:
Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
aarch64: Add the SME2 predicate-related instructions
Implementation-wise, the main things to note here are:
- the WHILE* instructions have forms that return a pair of predicate
registers. This is the first time that we've had lists of predicate
registers, and they wrap around after register 15 rather than after
register 31.
- the predicate-as-counter WHILE* instructions have a fourth operand
that specifies the vector length. We can treat this as an enumeration,
except that immediate values aren't allowed.
- PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>].
This is the first instance of a vector/predicate index having
no suffix.
aarch64: Add the SME2 multivector LD1 and ST1 instructions
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided. In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.
The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15. Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound. The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound. This in turn required adding
an extra bit to the field.
SME2 defines new MOVA instructions for moving multiple registers
to and from ZA. As with SME, the instructions are also available
through MOV aliases.
One notable feature of these instructions (and many other SME2
instructions) is that some register lists must start at a multiple
of the list's size. The patch uses the general error "start register
out of range" when this constraint isn't met, rather than an error
specifically about multiples. This ensures that the error is
consistent between these simple consecutive lists and later
strided lists, for which the requirements aren't a simple multiple.
aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks. In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.
This patch adds support for these registers and extends some
existing instructions to support them. Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.
Some SME2 instructions operate on a range of consecutive ZA vectors.
This is indicated by syntax such as:
za[<Wv>, <imml>:<immh>]
Like with the earlier vgx2 and vgx4 support, we get better error
messages if the parser allows all ZA indices to have a range.
We can then reject invalid cases during constraint checking.
Many SME2 instructions operate on groups of 2 or 4 ZA vectors.
This is indicated by adding a "vgx2" or "vgx4" group size to the
ZA index. The group size is optional in assembly but preferred
for disassembly.
There is not a binary distinction between mnemonics that have
group sizes and mnemonics that don't, nor between mnemonics that
take vgx2 and mnemonics that take vgx4. We therefore get better
error messages if we allow any ZA index to have a group size
during parsing, and wait until constraint checking to reject
invalid sizes.
A quirk of the way errors are reported means that if an instruction
is wrong both in its qualifiers and its use of a group size, we'll
print suggested alternative instructions that also have an incorrect
group size. But that's a general property that also applies to
things like out-of-range immediates. It's also not obviously the
wrong thing to do. We need to be relatively confident that we're
looking at the right opcode before reporting detailed operand-specific
errors, so doing qualifier checking first seems resonable.
aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array
SME2 adds various new fields that are similar to
AARCH64_OPND_SME_ZA_array, but are distinguished by the size of
their offset fields. This patch adds _off4 to the name of the
field that we already have.
aarch64: Prefer register ranges & support wrapping
Until now, binutils has supported register ranges such
as { v0.4s - v3.4s } as an unofficial shorthand for
{ v0.4s, v1.4s, v2.4s, v3.4s }. The SME2 ISA embraces this form
and makes it the preferred disassembly. It also embraces wrapped
lists such as { z31.s - z2.s }, which is something that binutils
didn't previously allow.
The range form was already binutils's preferred disassembly for 3- and
4-register lists. This patch prefers it for 2-register lists too.
The patch also adds support for wrap-around.
SME2 has instructions that accept strided register lists,
such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this
patch is to extend binutils to support such lists.
The parsing code already had (unused) support for strides of 2.
The idea here is instead to accept all strides during parsing
and reject invalid strides during constraint checking.
The SME2 instructions that accept strided operands also have
non-strided forms. The errors about invalid strides therefore
take a bitmask of acceptable strides, which allows multiple
possibilities to be summed up in a single message.
I've tried to update all code that handles register lists.
Some FLD_imm* suffixes used a counting scheme such as FLD_immN,
FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the
suffix. The latter seems more mnemonic, and was a big help
in doing the SME2 work.
Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious.
Presumably it indicated a 2-bit field, but it actually starts
in bit 22.
In GAS, the vector and predicate registers are identified by
REG_TYPE_VN, REG_TYPE_ZN and REG_TYPE_PN. This "N" is obviously
a placeholder for the register number. However, we don't use that
convention for integer and FP registers, and (more importantly)
SME2 adds "predicate-as-counter" registers that are denoted PN.
This patch therefore drops the "N" suffix from the existing
registers. The main hitch is that Z was also used for the
zero register in things like R_Z, but using ZR seems more
consistent with the SP-based names.
Quite a lot of SME2 instructions have an opcode bit that selects
between 32-bit and 64-bit forms of an instruction, with the 32-bit
forms being part of base SME2 and with the 64-bit forms being part
of an optional extension. It's nevertheless useful to have a single
opcode entry for both forms since (a) that matches the ISA definition
and (b) it tends to improve error reporting.
This patch therefore adds a libopcodes function called
aarch64_cpu_supports_inst_p that tests whether the target
supports a particular instruction. In future it will depend
on internal libopcodes routines.
This patch renames the OP_SME_* macros in aarch64-tbl.h so that
they follow the same scheme as the OP_SVE_* ones. It also uses
OP_SVE_ as the prefix, since there is no real distinction between
the SVE and SME uses of qualifiers: a macro defined for one can
be useful for the other too.
aarch64: Tweak priorities of parsing-related errors
There are three main kinds of error reported during parsing,
in increasing order of priority:
- AARCH64_OPDE_RECOVERABLE (register seen instead of immediate)
- AARCH64_OPDE_SYNTAX_ERROR
- AARCH64_OPDE_FATAL_SYNTAX_ERROR
This priority makes sense when comparing errors reported against the
same operand. But if we get to operand 3 (say) and see a register
instead of an immediate, that's likely to be a better match than
something that fails with a syntax error at operand 1.
The idea of this patch is to prioritise parsing-related errors
based on operand index first, then by error code. Post-parsing
errors still win over parsing errors, and their relative priorities
don't change.
aarch64: Try to report invalid variants against the closest match
If an instruction has invalid qualifiers, GAS would report the
error against the final opcode entry that got to the qualifier-
checking stage. It seems better to report the error against
the opcode entry that had the closest match, just like we
pick the closest match within an opcode entry for the
"did you mean this?" message.
This patch adds the number of invalid operands as an
argument to AARCH64_OPDE_INVALID_VARIANT and then picks the
AARCH64_OPDE_INVALID_VARIANT with the lowest argument.
aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield
AARCH64_OPDE_REG_LIST took a single operand that specified the
expected number of registers. However, there are quite a few
SME2 instructions that have both 2-register forms and (separate)
4-register forms. If the user tries to use a 3-register list,
it isn't obvious which opcode entry they meant. Saying that we
expect 2 registers and saying that we expect 4 registers would
both be wrong.
This patch therefore switches the operand to a bitfield. If a
AARCH64_OPDE_REG_LIST is reported against multiple opcode entries,
the patch ORs up the expected lengths.
This has no user-visible effect yet. A later patch adds more error
strings, alongside tests that use them.
aarch64: Add an operand class for SVE register lists
SVE register lists were classified as SVE_REG, since there had been
no particular reason to separate them out. However, some SME2
instructions have tied register list operands, and so we need to
distinguish registers and register lists when checking whether two
operands match.
Also, the register list operands used a general error message,
even though we already have a dedicated error code for register
lists that are the wrong length.
aarch64: Add an error code for out-of-range registers
libopcodes currently reports out-of-range registers as a general
AARCH64_OPDE_OTHER_ERROR. However, this means that each register
range needs its own hard-coded string, which is a bit cumbersome
if the range is determined programmatically. This patch therefore
adds a dedicated error type for out-of-range errors.
SME2 has many instructions that take a list of SVE registers.
There are often multiple forms, with different forms taking
different numbers of registers.
This means that if, after a successful parse and qualifier match,
we find that the number of registers does not match the opcode entry,
the associated error should have a lower priority/severity than other
errors reported at the same stage. For example, if there are 2-register
and 4-register forms of an instruction, and if the assembly code uses
the 2-register form with an out-of-range value, the out-of-range value
error against the 2-register instruction should have a higher priority
than the "wrong number of registers" error against the 4-register
instruction.
This is tested by the main SME2 patches, but seemed worth splitting out.
aarch64: Rework reporting of failed register checks
There are many opcode table entries that share the same mnemonic.
Trying to parse an invalid assembly line will trigger an error for
each of these entries, but the specific error might vary from one
entry to another, depending on the exact nature of the problem.
GAS has quite an elaborate system for picking the most appropriate
error out of all the failed matches. And in many cases it works well.
However, one of the limitations is that the error is always reported
against a single opcode table entry. If that table entry isn't the
one that the user intended to use, then the error can end up being
overly specific.
This is particularly true if an instruction has a typoed register
name, or uses a type of register that is not accepted by any
opcode table entry. For example, one of the expected error
matches for an attempted SVE2 instruction is:
Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
even though the hypothetical user was presumably attempting to use
the SVE form of ADDP rather than the Advanced SIMD one. There are
many other instances of this in the testsuite.
The problem becomes especially acute with SME2, since many SME2
instructions reuse existing mnemonics. This could lead to us
reporting an SME-related error against a non-SME instruction,
or a non-SME-related error against an SME instruction.
This patch tries to improve things by collecting together all
the register types that an opcode table entry expected for a
given operand. It also records what kind of register was
actually seen, if any. It then tries to summarise all this
in a more directed way, falling back to a generic error if
the combination defies a neat summary.
The patch includes tests for all new messages except REG_TYPE_ZA,
which only triggers with SME2.
To test this, I created an assembly file that contained the cross
product of all known mnemonics and one example from each register
class. I then looked for cases where the new routines fell back on the
generic errors ("expected a register" or "unexpected register type").
I locally added dummy messages for each one until there were no
more hits. The patch adds a specimen instruction to diagnostics.s
for each of these combinations. In each case, the combination didn't
seem like something that could be summarised in a natural way, so the
generic messages seemed better. There's always going to be an element
of personal taste around this kind of thing though.
Adding more register types made 1<<REG_TYPE_MAX exceed the range
of the type, but we don't actually need/want 1<<REG_TYPE_MAX.
aarch64: Try to avoid inappropriate default errors
After parsing a '{' and the first register, parse_typed_reg would
report errors in subsequent registers in the same way as for the
first register. It used set_default_error, which reports errors
of the form "operand N must be X".
The problem is that if there are multiple opcode entries for the
same mnemonic, there could be several matches that lead to a
default error. There's no guarantee that the default error for
the register list is the one that will be chosen.
To take an example from the testsuite:
ext z0.b,{z31.b,z32.b},#0
gave:
operand 2 must be an SVE vector register
with the error being reported against the single-vector version
of ext, even though the operand is clearly a list.
This patch uses set_fatal_syntax_error to bump the priority of the
error once we're sure that the operand is a list of the right type.
aarch64: Improve errors for malformed register lists
parse_typed_reg is used for parsing both bare registers and
registers that occur in lists. If it doesn't see a register,
or sees an unexpected kind of register, it queues a default
error to report the problem. These default errors have the form
"operand N must be an X", where X comes from the operand table.
If there are multiple opcode entries that report default errors,
GAS tries to pick the most appropriate one, using the opcode
table order as a tiebreaker. But this can lead to cases where
a syntax error in a register list is reported against an opcode
that doesn't accept register lists. For example, the unlikely
error:
ext z0.b,{,},#0
is reported as:
operand 2 must be an SVE vector register -- `ext z0.b,{,},#0'
even though operand 2 can be a register list.
If we've parsed the opening '{' of a register list, and then see
something that isn't remotely register-like, it seems better to
report that directly as a syntax error, rather than rely on the
default error. The operand won't be a valid list of anything,
so there's no need to pick a specific Y in "operand N must be
a list of Y".
Integer registers were parsed indirectly through
aarch64_reg_parse_32_64 (and thus aarch64_addr_reg_parse) rather
than directly through parse_reg. This was because we need the
qualifier associated with the register, and the logic to calculate
that was buried in aarch64_addr_reg_parse.
The code that parses FP registers had the same need, but it
open-coded the calculation of the qualifier.
This patch tries to handle both cases in the same way. It is
needed by a later patch that tries to improve the register-related
diagnostics.
parse_address_main currently uses get_reg_expected_msg to
report invalid base and offset registers, but the disadvantage
of doing that is that it isn't immediately clear which register
is wrong (the base or the offset).
A later patch moves away from using get_reg_expected_msg for failed
type checks, but doing that here didn't seem like the best approach.
The patch tries to use more tailored messages instead.
In SME, the vector select register had to be in the range
w12-w15, so it made sense to enforce that during parsing.
However, SME2 adds instructions for which the range is
w8-w11 instead.
This patch therefore moves the range check from the parsing
stage to the constraint-checking stage.
Also, the previous error used a capitalised range W12-W15,
whereas other register range errors used lowercase ranges
like p0-p7. A quick internal poll showed a preference for
the lowercase form, so the patch uses that.
The patch uses "selection register" rather than "vector
select register" so that the terminology extends more
naturally to PSEL.
Now that parse_typed_reg checks the range of tile register numbers
and libopcodes checks the range of vector select offsets, there's
very little difference between the parsing of ZA tile indices,
ZA array indices, and PSEL indices. The main one is that ZA
array indices don't currently allow "za" to be qualified,
but we need to remove that restriction for SME2.
This patch therefore consolidates all three parsers into a single
routine, parameterised by the type of register that they expect.
This patch moves the range checks on ZA vector select offsets from
gas to libopcodes. Doing the checks there means that the error
messages contain the expected range. It also fits in better
with the error severity scheme, which becomes important later.
(This is because out-of-range indices are treated as more severe than
syntax errors, on the basis that parsing must have succeeded if we get
to the point of checking the completed opcode.)
The patch also adds a new check_za_access function for checking
ZA accesses. That's a bit over the top for one offset check, but the
function becomes more complex with later patches.
sme-9-illegal.s checked for an invalid .q suffix using:
psel p1, p15, p3.q[w15]
but this is doubly invalid because it misses the immediate part
of the index. The patch keeps that test but adds another with
a zero index, so that .q is the only thing wrong.
The aarch64-tbl.h change includes neatening up the backslash
positions.
ZA indices have more parts than most operands, so passing these
parts around individually is more awkward than for other operand
types. Things aren't too bad at the moment, but SME2 adds two
further pieces: an offset range and a vector group size.
This patch therefore replaces arguments for the individual pieces
with a single argument for the index as a whole.
A later patch moves the range checking for ZA vector select
offsets from gas to libopcodes. That in turn requires the
immediate field to be big enough to support all parsed values.
This shouldn't be a particularly size-sensitive structure,
so there should be no memory problems with doing this.
za_tile_vector is also used for indexing ZA as a whole, rather than
just for indexing tiles. The former is more common than the latter
in SME2, so this patch generalises the name to "indexed_za".
The patch also names the associated structure, so that later patches
can reuse it during parsing.
We already treat the ZA tiles ZA0-ZA15 as registers. This patch
does the same for ZA itself. parse_sme_zero_mask can then parse
ZA tiles and ZA in the same way, through parsed_type_reg.
One important effect of going through parsed_type_reg (in general)
is that it allows ZA to take qualifiers. This is necessary for many
SME2 instructions.
However, to support existing unqualified uses of ZA, parse_reg_with_qual
needs to treat the qualiier as optional. Hopefully the net effect is
to give better error messages, since now that SME2 makes "za.<T>"
valid in some contexts, it might be natural to use it (incorrectly)
in ZERO too.
While there, the patch also tweaks the error messages for invalid
ZA tiles, to try to make some cases more specific.
For now, parse_sme_za_array just uses parse_reg, rather than
parse_typed_reg/parse_reg_with_qual. A later patch consolidates
the parsing further.
Now that all parsing of ZA tile names goes through parse_typed_reg,
we can check there for out-of-range tile numbers. The other check
performed by parse_sme_zada_operand was to reject .q, but that can
now be done via F_STRICT instead. (.q tiles are valid in other
contexts, so they shouldn't be rejected in parse_typed_reg.)
This patch reuses the general parse_typed_reg for ZA tiles.
This involves adding a way of suppressing the usual treatment
of register indices, since ZA indices look very different from
Advanced SIMD and SVE vector indices.
parse_typed_reg returned a register number and passed the
register type back using a pointer parameter. It seems simpler
to return the register entry instead, since that has both pieces
of information in one place.
The patch also replaces the boolean in_reg_list parameter with
a mask of flags. This hopefully makes calls easier to read
(more self-documenting than "true" or "false"), but more
importantly, it allows a later patch to add a second flag.
This patch just moves vectype_to_qualifier further up, so that
a later patch can call it at an earlier point in the file.
No behavioural change intended.
This patch adds a multi-register type that includes both REG_TYPE_ZATH
and REG_TYPE_ZATV. This slightly simplifies the existing code, but the
main purpose is to enable later patches.
The ZA tile registers were called REG_TYPE_ZA, REG_TYPE_ZAH and
REG_TYPE_ZAV. However, a later patch wants to make plain "za"
a register type too, and REG_TYPE_ZA is the obvious name for that.
This patch therefore adds "T" (tile) to the existing names.
GAS's aarch64_instruction had its own cut-down error record,
but it's better for later patches if it reuses the binutils-wide
aarch64_operand_error instead. The main difference is that
aarch64_operand_error can store arguments to the error while
aarch64_instruction couldn't.
This patch makes all SME instructions use F_STRICT, so that qualifiers
have to be provided explicitly rather than being inferred from other
operands. The main change is to move the qualifier setting from the
operand-level decoders to the opcode level.
This is one step towards consolidating the ZA parsing code and
extending it to handle SME2.
GAS refuses to interpret register names like x0 as unadorned
immediates, due to the obvious potential for confusion with
register operands. (An explicit #x0 is OK.)
For compatibility reasons, we can't extend the set of registers
that GAS rejects for existing instructions. For example:
mov x0, z0
was valid code before SVE was added, so it needs to stay valid
code even when SVE is enabled. But we can make GAS reject newer
registers in newer instructions. The SVE instruction:
and z0.s, z0.s, z0.h
is therefore invalid, rather than z0.h being an immediate.
This patch extends the SVE behaviour to SVE2. The old call
to AARCH64_CPU_HAS_FEATURE was technically the wrong way around,
although it didn't matter in practice for base SVE instructions
since their avariants only set SVE.
In the register-index forms of PRFM, the unallocated prefetch opcodes
24-31 have been reused for the encoding of the new RPRFM instruction.
The PRFM opcode space is now capped at 23 for these forms. The other
forms of PRFM are unaffected.
Most extension flags are named after the associated architectural
FEAT_* flags, but sme-i64 and sme-f64 were exceptions. This patch
adds sme-i16i64 and sme-f64f64 aliases, but keeps the old names too
for compatibility.
Andrew Burgess [Fri, 10 Mar 2023 12:29:58 +0000 (12:29 +0000)]
gdb/python: Add new gdb.unwinder.FrameId class
When writing an unwinder it is necessary to create a new class to act
as a frame-id. This new class is almost certainly just going to set a
'sp' and 'pc' attribute within the instance.
This commit adds a little helper class gdb.unwinder.FrameId that does
this job. Users can make use of this to avoid having to write out
standard boilerplate code any time they write an unwinder.
Of course, if the user wants their FrameId class to be more
complicated in some way, then they can still write their own class,
just like they could before.
I've simplified the example code in the documentation to now use the
new helper class, and I've also made use of this helper within the
testsuite.
Any existing user code will continue to work just as it did before
after this change.
Reviewed-By: Eli Zaretskii <eliz@gnu.org> Reviewed-By: Tom Tromey <tom@tromey.com>
projects / thirdparty / binutils-gdb.git / log
