Turn HARD_REGNO_CALL_PART_CLOBBERED into a target hook
The SVE patches change the size of a machine_mode from a compile-time
constant to a runtime invariant. However, target-specific code can
continue to treat the modes as constant-sized if the target only has
constant-sized modes.
The main snag with this approach is that target-independent code still
uses macros from the target .h file. This patch is one of several that
converts a target macro to a hook.
2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
This patch adds routines for converting a SUBREG_BYTE offset into a
memory address offset. The two only differ for paradoxical subregs,
where SUBREG_BYTE is always 0 but the memory address offset can be
negative.
2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (subreg_memory_offset): Declare.
* emit-rtl.c (subreg_memory_offset): New function.
* expmed.c (store_bit_field_1): Use it.
* expr.c (undefined_operand_subword_p): Likewise.
* simplify-rtx.c (simplify_subreg): Likewise.
jakub [Mon, 4 Sep 2017 08:11:44 +0000 (08:11 +0000)]
PR sanitizer/81981
* gimple-fold.c (gimple_fold_call): Optimize away useless UBSAN_PTR
and UBSAN_BOUNDS internal calls. Clean up IFN_UBSAN_OBJECT_SIZE
handling. Use replace_call_with_value with NULL instead of
gsi_replace, unlink_stmt_vdef and release_defs.
PR82045: Avoid passing machine modes through "..."
PR82045 is about a bootstrap failure on sparc-sun-solaris2.11.
The problem was that we were passing the new machine_mode wrapper
classes through "..." to emit_library_call(_value), which then
read them back as ints instead.
The simplest fix seemed to be replace "..." with an array of
rtx_mode_ts, then provide wrappers for the common cases. This
bulks out rtl.h a bit, but it does make things a bit more typesafe.
2017-09-04 Richard Sandiford <richard.sandiford@linaro.org>
2017-09-01 Michael Meissner <meissner@linux.vnet.ibm.com>
PR libquadmath/81848
* configure.ac (powerpc*-linux*): Use attribute mode KC to create
complex __float128 on PowerPC instead of attribute mode TC.
* quadmath.h (__complex128): Likewise.
* configure: Regenerate.
* math/cbrtq.c (CBRT2): Use __float128 not long double.
(CBRT4): Likewise.
(CBRT2I): Likewise.
(CBRT4I): Likewise.
* math/j0q.c (U0): Likewise.
* math/sqrtq.c (sqrtq): Don't depend on implicit conversion
between __float128, instead explicitly convert the __float128
value to long double because the PowerPC does not allow __float128
and long double in the same expression.
With the testcase in the PR, with all the command line options mentioned
there, a (comparison) instruction becomes dead in fwprop1 but is not
deleted until all the way in rtl_dce.
which doesn't match; but the set of flags is dead, so combine makes the
set of r105 the whole new instruction, which it then places at i3. But
that is wrong, because r105 is used after i2 but before i3! We forget
to check for that in this case.
This patch fixes it.
PR rtl-optimization/82024
* combine.c (try_combine): If the combination result is a PARALLEL,
and we only need to retain the SET in there that would be placed
at I2, check that we can place that at I3 instead, before doing so.
jakub [Fri, 1 Sep 2017 16:49:26 +0000 (16:49 +0000)]
PR target/81766
* config/i386/i386.c (ix86_init_large_pic_reg): Return label instead of void.
(ix86_init_pic_reg): Remember label from ix86_init_large_pic_reg, if non-NULL
and preceded by NOTE_INSN_BASIC_BLOCK, swap the note and label.
Fix excess precision handling of compound assignments (PR c/82071).
PR c/82071 reports how compound assignment operators such as += handle
excess precision inconsistently with the same operation done with a
plain assignment and binary operator.
There were (at least) two problems with how compound assignments
handled excess precision. The EXCESS_PRECISION_EXPR for an argument
with excess precision was removed too early, resulting in
build_binary_op being called with an rhs operand whose type reflected
the evaluation format, so not having sufficient information to achieve
the intended semantics in all cases, and then the code called
c_fully_fold on the results of build_binary_op without allowing for
the possibility of an EXCESS_PRECISION_EXPR as the result, so leading
to double rounding of the result (first to its semantic type, then to
the type of the LHS of the assignment) instead of the intended single
rounding.
This patch fixes those problems by keeping EXCESS_PRECISION_EXPRs
further through build_modify_expr (and build_atomic_assign which it
calls) and only removing them locally where appropriate.
Note that while this patch should achieve *consistency*, that's
consistency with the understanding of C99 semantics that I originally
intended to implement. For the particular case in the testcase, C11
semantics (from N1531) differ from that understanding of C99
semantics, in that an implicit conversion of an integer to floating
point can have excess precision. I intend to implement those C11
semantics separately (conditional on flag_isoc11) (which will also
mean that building conditional expressions can produce a result with
excess precision even when the arguments lack excess precision, where
previously it could not), and not to close the bug until that is also
done.
Tested for x86_64-pc-linux-gnu.
PR c/82071
gcc/c:
* c-typeck.c (build_atomic_assign): Handle argument with excess
precision. Ensure any EXCESS_PRECISION_EXPR is present in
argument passed to build_binary_op and convert_for_assignment but
not for call to c_fully_fold.
(build_modify_expr): Do not remove EXCESS_PRECISION_EXPR early.
Ensure build_binary_op is called with argument with original
semantic type. Avoid calling c_fully_fold with an
EXCESS_PRECISION_EXPR from build_binary_op.
gcc/testsuite:
* gcc.target/i386/excess-precision-7.c: New test.
law [Fri, 1 Sep 2017 16:26:00 +0000 (16:26 +0000)]
* varasm.c (bss_initializer_p): Do not put constants into .bss
(categorize_decl_for_section): Handle bss_initializer_p returning
false when DECL_INITIAL is NULL.
law [Fri, 1 Sep 2017 15:32:15 +0000 (15:32 +0000)]
PR tree-optimization/82052
* tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
Always initialize the returned slot after a hash table miss
when INSERT is true.
PR tree-optimization/82052
* gcc.c-torture/compile/pr82052.c: New test.
Fix profile update in tree-ssa-isolate-paths.c (PR tree-optimization/82059).
2017-09-01 Martin Liska <mliska@suse.cz>
PR tree-optimization/82059
* gimple-ssa-isolate-paths.c (isolate_path): Add profile and
frequency only when an edge is redirected.
2017-09-01 Martin Liska <mliska@suse.cz>
PR tree-optimization/82059
* gcc.dg/tree-ssa/pr82059.c: New test.
* config/arc/arc.c (arc_ifcvt): Remove use of merge_blocks call.
(arc_ccfsm_advance): Fix checking for delay slots.
(arc_reorg): Add rtl dump after each call to arc_ifcvt
* config/arc/arc.md (movqi_insn): Add stores to save constant long
immediates.
(movhi_insn): Update store instruction constraint which are saving
6-bit short immediates.
(movsi_insn): Consider also short scaled load operations.
(zero_extendhisi2_i): Use Usd constraint instead of T.
(extendhisi2_i): Add q constraint.
(arc_clzsi2): Add type and length attributes.
(arc_ctzsi2): Likewise.
* config/arc/constraints.md (Usc): Update constraint, the
assembler can parse two relocations for a single instruction.
We don't want to use anchors for small data: the GP register acts as an anchor in that
case. We also don't want to use them for PC-relative accesses,
where the PC acts as an anchor. TLS symbols require special accesses as well, don't use
anchors for such symbols.
jakub [Fri, 1 Sep 2017 11:25:39 +0000 (11:25 +0000)]
PR c/81887
c-family/
* c-pragma.c (omp_pragmas): Move "ordered" entry from here to ...
(omp_pragmas_simd): ... here.
* c-omp.c (c_finish_omp_ordered): If clauses isn't simd clause alone,
create new clauses list containing just simd clause.
c/
* c-parser.c (c_parser_omp_ordered): Handle -fopenmp-simd.
cp/
* parser.c (cp_parser_omp_ordered): Handle -fopenmp-simd.
fortran/
* parse.c (decode_omp_directive): Use matchs instead of matcho for
end ordered and ordered directives, except for ordered depend. For
-fopenmp-simd and ordered depend, reject the stmt.
* trans-openmp.c (gfc_trans_omp_ordered): For -fopenmp-simd ignore
threads clause and if simd clause isn't present, just translate the
body.
testsuite/
* c-c++-common/gomp/pr81887.c: New test.
* gfortran.dg/gomp/pr81887.f90: New test.
jgreenhalgh [Thu, 31 Aug 2017 16:03:09 +0000 (16:03 +0000)]
[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>
The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.
* config.gcc: Use g.opt for arc.
* config/arc/arc.c (LEGITIMATE_SCALED_ADDRESS_P): Deleted,
functionality moved to ...
(legitimate_scaled_address_p): New function, ...here.
(LEGITIMATE_SMALL_DATA_OFFSET_P): New define.
(LEGITIMATE_SMALL_DATA_ADDRESS_P): Use the above define.
(legitimate_offset_address_p): Delete TARGET_NO_SDATA_SET
condition.
(arc_override_options): Handle G option.
(arc_output_pic_addr_const): Correct function definition.
(arc_legitimate_address_p): Use legitimate_scaled_address_p.
(arc_decl_anon_ns_mem_p): Delete.
(arc_in_small_data_p): Overhaul this function to take into
consideration the value given via G option.
(arc_rewrite_small_data_1): Renamed and corrected old
arc_rewrite_small_data function.
(arc_rewrite_small_data): New function.
(small_data_pattern): Don't use pic_offset_table_rtx.
* config/arc/arc.h (CC1_SPEC): Recognize G option.
* config/arc/simdext.md (movmisalignv2hi): Use
prepare_move_operands function.
(mov*): Likewise.
(movmisalign*): Likewise.
claziss [Thu, 31 Aug 2017 13:52:31 +0000 (13:52 +0000)]
[ARC] Improves and fixes for small data support.
Add alignment check for short load/store instructions used for sdata,
as they request 32-bit aligned short immediate. Use sdata symbol
alignment information and emit scalled loads/stores whenever is
possible. The scalled address will extend the access range for sdata
symbols. Allow 64-bit datum into small data section, if double
load/store instructions are present.
* config/arc/arc-protos.h (compact_sda_memory_operand): Update
prototype.
* config/arc/arc.c (arc_print_operand): Output scalled address for
sdata whenever is possible.
(arc_in_small_data_p): Allow sdata for 64bit datum when double
load/stores are available.
(compact_sda_memory_operand): Check for the alignment required by
code density instructions.
* config/arc/arc.md (movsi_insn): Use newly introduced Us0
constraint.
* config/arc/constraints.md (Usd): Update constraint.
(Us0): New constraint.
(Usc): Update constraint.
rsandifo [Thu, 31 Aug 2017 10:11:41 +0000 (10:11 +0000)]
[AArch64] Tighten address register subreg checks
Previously we allowed subregs of non-GPR modes to be base and index
registers in non-strict mode. In practice such subregs will always
require a reload, so we get better code by disallowing them.
2017-08-31 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_base_register_rtx_p): Only allow
subregs whose inner modes can be stored in GPRs.
(aarch64_classify_index): Likewise.
rsandifo [Thu, 31 Aug 2017 09:52:38 +0000 (09:52 +0000)]
[AArch64] Rename cmp_result iterator
The comparison results provided by the V_cmp_result/v_cmp_result
attribute were simply the corresponding integer vector. We'd also
like to have easy access to the integer vector for SVE, but using
"cmp_result" would be confusing because SVE comparisons return
predicates instead of vectors. This patch therefore renames the
attributes to the more general V_INT_EQUIV/v_int_equiv instead.
As to the capitalisation: there are already many iterators that use
all lowercase vs. all uppercase names to distinguish all lowercase
vs. all uppercase expansions (e.g. fcvt_target and FCVT_TARGET).
It's also the convention used for the built-in mode/MODE/code/CODE/etc.
attributes. IMO those names are easier to read at a glance, rather than
relying on a single letter's difference.
2017-08-22 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
rsandifo [Thu, 31 Aug 2017 09:51:40 +0000 (09:51 +0000)]
[AArch64] Remove use of wider vector modes
The AArch64 port defined x2, x3 and x4 vector modes that were only used
in the rtl for the AdvSIMD LD{2,3,4} patterns. It seems unlikely that
this rtl would have led to any valid simplifications, since the values
involved were unspecs that had a different number of operands from the
non-dreg versions. (The dreg UNSPEC_LD2 had a single operand, while
the qreg one had two operands.)
As it happened, the patterns led to invalid simplifications on big-
endian targets due to a mix-up in the operand order, see Tamar's fix
in r240271.
This patch therefore replaces the rtl patterns with dedicated unspecs.
This allows the x2, x3 and x4 modes to be removed, avoiding a clash
with 256-bit and 512-bit SVE.
2017-08-22 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte
vector modes.
* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete.
* config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG)
(UNSPEC_LD4_DREG): New unspecs.
* config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg_le)
(aarch64_ld2<mode>_dreg_be): Replace with...
(aarch64_ld2<mode>_dreg): ...this pattern and use the new DREG
unspec.
(aarch64_ld3<mode>_dreg_le)
(aarch64_ld3<mode>_dreg_be): Replace with...
(aarch64_ld3<mode>_dreg): ...this pattern and use the new DREG
unspec.
(aarch64_ld4<mode>_dreg_le)
(aarch64_ld4<mode>_dreg_be): Replace with...
(aarch64_ld4<mode>_dreg): ...this pattern and use the new DREG
unspec.
renlin [Thu, 31 Aug 2017 09:18:22 +0000 (09:18 +0000)]
[TESTSUITE]Use memcpy instead of strcpy in testsuite/gcc.dg/memcmp-1.c
strcpy will keep reading and writing memory if the string is not terminated
with null character. In this case, it may visit memory beyond the boundary.
gcc/testsuite/
2017-08-31 Renlin Li <renlin.li@arm.com>
Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
* gcc.dg/memcmp-1.c (test_strncmp): Use memcpy instead of strcpy.
wschmidt [Wed, 30 Aug 2017 20:04:07 +0000 (20:04 +0000)]
[gcc]
2017-08-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/81987
* gimple-ssa-strength-reduction.c (insert_initializers): Don't
insert an initializer in a location not dominated by the stride
definition.
[gcc/testsuite]
2017-08-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/81987
* g++.dg/torture/pr81987.C: New file.
ian [Wed, 30 Aug 2017 18:27:17 +0000 (18:27 +0000)]
* configure.ac: Substitute GOC_FOR_TARGET and GCC_FOR_TARGET.
* Makefile.am (MOSTLYCLEANFILES): Add check-gcc.
(check-gccgo): Create via a temporary file.
(check-gcc): New target.
(CHECK_ENV): Set CC.
(ECHO_ENV): Report CC.
(check-go-tool): Depend on check-gcc.
(check-runtime, check-cgo-test, check-carchive-test): Likewise.
* configure, Makefile.in: Rebuild.
jbeniston [Wed, 30 Aug 2017 16:16:37 +0000 (16:16 +0000)]
* tree-vect-patterns.c (vect_pattern_recog_1): Use VECTOR_TYPE_P instead
of VECTOR_MODE_P check.
* tree-vect-stmts.c (get_vectype_for_scalar_type_and_size): Allow single
element vector types.
rsandifo [Wed, 30 Aug 2017 15:25:38 +0000 (15:25 +0000)]
Add a partial_subreg_p predicate
This patch adds a partial_subreg_p predicate to go alongside
paradoxical_subreg_p.
Like the paradoxical_subreg_p patch, this one replaces some tests that
were based on GET_MODE_SIZE rather than GET_MODE_PRECISION. In each
case the change should be a no-op or an improvement.
The regcprop.c patch prevents some replacements of the 82-bit RFmode
with the 80-bit XFmode on ia64. I don't understand the target details
here particularly well, but from the way the modes are described in
ia64-modes.def, it isn't valid to assume that an XFmode can carry an
RFmode payload. A comparison of the testsuite assembly output for one
target per CPU showed no other differences.
Some of the places changed here are tracking the widest access mode
found for a register. The series tries to standardise on:
if (partial_subreg_p (widest_seen, new_mode))
widest_seen = new_mode;
rather than:
if (paradoxical_subreg_p (new_mode, widest_seen))
widest_seen = new_mode;
Either would have been OK.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
ian [Wed, 30 Aug 2017 14:08:00 +0000 (14:08 +0000)]
* simple-object-xcoff.c (simple_object_xcoff_find_sections):
Improve .go_export csect handling. Don't make assumptions
on containing section or number of auxiliary entries.
marxin [Wed, 30 Aug 2017 12:38:31 +0000 (12:38 +0000)]
Fix IPA ICF with ASM statements (PR inline-asm/82001).
2017-08-30 Martin Liska <mliska@suse.cz>
PR inline-asm/82001
* ipa-icf-gimple.c (func_checker::compare_tree_list_operand):
Rename to ...
(func_checker::compare_asm_inputs_outputs): ... this function.
(func_checker::compare_gimple_asm): Use the function to compare
also ASM constrains.
* ipa-icf-gimple.h: Rename the function.
2017-08-30 Martin Liska <mliska@suse.cz>
PR inline-asm/82001
* gcc.dg/ipa/pr82001.c: New test.
rsandifo [Wed, 30 Aug 2017 11:21:04 +0000 (11:21 +0000)]
[77/77] Add a complex_mode class
This patch adds another machine_mode wrapper for modes that are
known to be COMPLEX_MODE_P. There aren't yet many places that make
use of it, but that might change in future.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* coretypes.h (complex_mode): New type.
* gdbhooks.py (build_pretty_printer): Handle it.
* machmode.h (complex_mode): New class.
(complex_mode::includes_p): New function.
(is_complex_int_mode): Likewise.
(is_complex_float_mode): Likewise.
* genmodes.c (get_mode_class): Handle complex mode classes.
* function.c (expand_function_end): Use is_complex_int_mode.
gcc/go/
* go-lang.c (go_langhook_type_for_mode): Use is_complex_float_mode.
rsandifo [Wed, 30 Aug 2017 11:20:55 +0000 (11:20 +0000)]
[76/77] Add a scalar_mode_pod class
This patch adds a scalar_mode_pod class and uses it to
replace the machine_mode in fixed_value.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* coretypes.h (scalar_mode_pod): New typedef.
* gdbhooks.py (build_pretty_printer): Handle it.
* machmode.h (gt_ggc_mx, gt_pch_nx): New functions.
* fixed-value.h (fixed_value::mode): Change type to scalar_mode_pod.
* fold-const.c (fold_convert_const_int_from_fixed): Use scalar_mode.
* tree-streamer-in.c (unpack_ts_fixed_cst_value_fields): Use
as_a <scalar_mode>.
rsandifo [Wed, 30 Aug 2017 11:20:47 +0000 (11:20 +0000)]
[74/77] Various small scalar_mode changes
This patch uses scalar_mode in a few miscellaneous places:
- Previous patches mean mode_to_vector can take a scalar_mode without
further changes.
- Implicit promotion is limited to scalar types (affects promote_mode
and sdbout_parms)
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* machmode.h (mode_for_vector): Take a scalar_mode instead
of a machine_mode.
* stor-layout.c (mode_for_vector): Likewise.
* explow.c (promote_mode): Use as_a <scalar_mode>.
* sdbout.c (sdbout_parms): Use is_a <scalar_mode>.
rsandifo [Wed, 30 Aug 2017 11:20:11 +0000 (11:20 +0000)]
[70/77] Make expand_fix/float check for scalar modes
The expand_float code:
/* Unsigned integer, and no way to convert directly. Convert as signed,
then unconditionally adjust the result. */
and the expand_fix code:
/* For an unsigned conversion, there is one more way to do it.
If we have a signed conversion, we generate code that compares
the real value to the largest representable positive number. If if
is smaller, the conversion is done normally. Otherwise, subtract
one plus the highest signed number, convert, and add it back.
are restricted to scalars, since the expansion branches on a
comparison of the value. This patch makes that explicit.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* optabs.c (expand_float): Explicitly check for scalars before
using a branching expansion.
(expand_fix): Likewise.
rsandifo [Wed, 30 Aug 2017 11:19:47 +0000 (11:19 +0000)]
[67/77] Use scalar_mode in fixed-value.*
This patch makes the fixed-value.* routines use scalar_mode.
It would be possible to define special classes for these modes, as for
scalar_int_mode and scalar_float_mode, but at the moment nothing would
benefit from them. In particular, there's no use case that would help
select between one class for all fixed-point modes versus one class for
fractional modes and one class for accumulator modes.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* fixed-value.h (fixed_from_double_int): Take a scalar_mode
rather than a machine_mode.
(fixed_from_string): Likewise.
(fixed_convert): Likewise.
(fixed_convert_from_int): Likewise.
(fixed_convert_from_real): Likewise.
(real_convert_from_fixed): Likewise.
* fixed-value.c (fixed_from_double_int): Likewise.
(fixed_from_string): Likewise.
(fixed_convert): Likewise.
(fixed_convert_from_int): Likewise.
(fixed_convert_from_real): Likewise.
(real_convert_from_fixed): Likewise.
* config/avr/avr.c (avr_out_round): Use as_a <scalar_mode>.
rsandifo [Wed, 30 Aug 2017 11:19:39 +0000 (11:19 +0000)]
[66/77] Use scalar_mode for constant integers
This patch treats the mode associated with an integer constant as a
scalar_mode. We can't use the more natural-sounding scalar_int_mode
because we also use (const_int 0) for bounds-checking modes. (It might
be worth adding a bounds-specific code instead, but that's for another
day.)
This exposes a latent bug in simplify_immed_subreg, which for
vectors of CONST_WIDE_INTs would pass the vector mode rather than
the element mode to rtx_mode_t.
I think the:
/* We can get a 0 for an error mark. */
|| GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
in immed_double_const is dead. trunc_int_mode (via gen_int_mode)
would go on to ICE if the mode fitted in a HWI, and surely plenty
of other code would be confused to see a const_int be interpreted
as a vector. We should instead be using CONST0_RTX (mode) if we
need a safe constant for a particular mode.
We didn't try to make these functions take scalar_mode arguments
because in many cases that would be too invasive at this stage.
Maybe it would become feasible in future. Also, the long-term
direction should probably be to add modes to constant integers
rather than have then as VOIDmode odd-ones-out. That would remove
the need for rtx_mode_t and thus remove the question whether they
should use scalar_int_mode, scalar_mode or machine_mode.
The patch also uses scalar_mode for the CONST_DOUBLE handling
in loc_descriptor. In that case the mode can legitimately be
either floating-point or integral.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* emit-rtl.c (immed_double_const): Use is_a <scalar_mode> instead
of separate mode class checks. Do not allow vector modes here.
(immed_wide_int_const): Use as_a <scalar_mode>.
* explow.c (trunc_int_for_mode): Likewise.
* rtl.h (wi::int_traits<rtx_mode_t>::get_precision): Likewise.
(wi::shwi): Likewise.
(wi::min_value): Likewise.
(wi::max_value): Likewise.
* dwarf2out.c (loc_descriptor): Likewise.
* simplify-rtx.c (simplify_immed_subreg): Fix rtx_mode_t argument
for CONST_WIDE_INT.
rsandifo [Wed, 30 Aug 2017 11:19:29 +0000 (11:19 +0000)]
[65/77] Add a SCALAR_TYPE_MODE macro
This patch adds a SCALAR_TYPE_MODE macro, along the same lines as
SCALAR_INT_TYPE_MODE and SCALAR_FLOAT_TYPE_MODE. It also adds
two instances of as_a <scalar_mode> to c_common_type, when converting
an unsigned fixed-point SCALAR_TYPE_MODE to the equivalent signed mode.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/c-family/
* c-lex.c (interpret_fixed): Use SCALAR_TYPE_MODE.
* c-common.c (c_build_vec_perm_expr): Likewise.
gcc/c/
* c-typeck.c (build_binary_op): Use SCALAR_TYPE_MODE.
(c_common_type): Likewise. Use as_a <scalar_mode> when setting
m1 and m2 to the signed equivalent of a fixed-point
SCALAR_TYPE_MODE.
gcc/cp/
* typeck.c (cp_build_binary_op): Use SCALAR_TYPE_MODE.
rsandifo [Wed, 30 Aug 2017 11:18:59 +0000 (11:18 +0000)]
[62/77] Big machine_mode to scalar_int_mode replacement
This patch changes the types of various things from machine_mode
to scalar_int_mode, in cases where (after previous patches)
simply changing the type is enough on its own. The patch does
nothing other than that.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* builtins.h (builtin_strncpy_read_str): Take a scalar_int_mode
instead of a machine_mode.
(builtin_memset_read_str): Likewise.
* builtins.c (c_readstr): Likewise.
(builtin_memcpy_read_str): Likewise.
(builtin_strncpy_read_str): Likewise.
(builtin_memset_read_str): Likewise.
(builtin_memset_gen_str): Likewise.
(expand_builtin_signbit): Use scalar_int_mode for local variables.
* cfgexpand.c (convert_debug_memory_address): Take a scalar_int_mode
instead of a machine_mode.
* combine.c (simplify_if_then_else): Use scalar_int_mode for local
variables.
(make_extraction): Likewise.
(try_widen_shift_mode): Take and return scalar_int_modes instead
of machine_modes.
* config/aarch64/aarch64.c (aarch64_libgcc_cmp_return_mode): Return
a scalar_int_mode instead of a machine_mode.
* config/avr/avr.c (avr_addr_space_address_mode): Likewise.
(avr_addr_space_pointer_mode): Likewise.
* config/cr16/cr16.c (cr16_unwind_word_mode): Likewise.
* config/msp430/msp430.c (msp430_addr_space_pointer_mode): Likewise.
(msp430_unwind_word_mode): Likewise.
* config/spu/spu.c (spu_unwind_word_mode): Likewise.
(spu_addr_space_pointer_mode): Likewise.
(spu_addr_space_address_mode): Likewise.
(spu_libgcc_cmp_return_mode): Likewise.
(spu_libgcc_shift_count_mode): Likewise.
* config/rl78/rl78.c (rl78_addr_space_address_mode): Likewise.
(rl78_addr_space_pointer_mode): Likewise.
(fl78_unwind_word_mode): Likewise.
(rl78_valid_pointer_mode): Take a scalar_int_mode instead of a
machine_mode.
* config/alpha/alpha.c (vms_valid_pointer_mode): Likewise.
* config/ia64/ia64.c (ia64_vms_valid_pointer_mode): Likewise.
* config/mips/mips.c (mips_mode_rep_extended): Likewise.
(mips_valid_pointer_mode): Likewise.
* config/tilegx/tilegx.c (tilegx_mode_rep_extended): Likewise.
* config/ft32/ft32.c (ft32_valid_pointer_mode): Likewise.
(ft32_addr_space_pointer_mode): Return a scalar_int_mode instead
of a machine_mode.
(ft32_addr_space_address_mode): Likewise.
* config/m32c/m32c.c (m32c_valid_pointer_mode): Take a
scalar_int_mode instead of a machine_mode.
(m32c_addr_space_pointer_mode): Return a scalar_int_mode instead
of a machine_mode.
(m32c_addr_space_address_mode): Likewise.
* config/powerpcspe/powerpcspe.c (rs6000_abi_word_mode): Likewise.
(rs6000_eh_return_filter_mode): Likewise.
* config/rs6000/rs6000.c (rs6000_abi_word_mode): Likewise.
(rs6000_eh_return_filter_mode): Likewise.
* config/s390/s390.c (s390_libgcc_cmp_return_mode): Likewise.
(s390_libgcc_shift_count_mode): Likewise.
(s390_unwind_word_mode): Likewise.
(s390_valid_pointer_mode): Take a scalar_int_mode rather than a
machine_mode.
* target.def (mode_rep_extended): Likewise.
(valid_pointer_mode): Likewise.
(addr_space.valid_pointer_mode): Likewise.
(eh_return_filter_mode): Return a scalar_int_mode rather than
a machine_mode.
(libgcc_cmp_return_mode): Likewise.
(libgcc_shift_count_mode): Likewise.
(unwind_word_mode): Likewise.
(addr_space.pointer_mode): Likewise.
(addr_space.address_mode): Likewise.
* doc/tm.texi: Regenerate.
* dojump.c (prefer_and_bit_test): Take a scalar_int_mode rather than
a machine_mode.
(do_jump): Use scalar_int_mode for local variables.
* dwarf2cfi.c (init_return_column_size): Take a scalar_int_mode
rather than a machine_mode.
* dwarf2out.c (convert_descriptor_to_mode): Likewise.
(scompare_loc_descriptor_wide): Likewise.
(scompare_loc_descriptor_narrow): Likewise.
* emit-rtl.c (adjust_address_1): Use scalar_int_mode for local
variables.
* except.c (sjlj_emit_dispatch_table): Likewise.
(expand_builtin_eh_copy_values): Likewise.
* explow.c (convert_memory_address_addr_space_1): Likewise.
Take a scalar_int_mode rather than a machine_mode.
(convert_memory_address_addr_space): Take a scalar_int_mode rather
than a machine_mode.
(memory_address_addr_space): Use scalar_int_mode for local variables.
* expmed.h (expand_mult_highpart_adjust): Take a scalar_int_mode
rather than a machine_mode.
* expmed.c (mask_rtx): Likewise.
(init_expmed_one_conv): Likewise.
(expand_mult_highpart_adjust): Likewise.
(extract_high_half): Likewise.
(expmed_mult_highpart_optab): Likewise.
(expmed_mult_highpart): Likewise.
(expand_smod_pow2): Likewise.
(expand_sdiv_pow2): Likewise.
(emit_store_flag_int): Likewise.
(adjust_bit_field_mem_for_reg): Use scalar_int_mode for local
variables.
(extract_low_bits): Likewise.
* expr.h (by_pieces_constfn): Take a scalar_int_mode rather than
a machine_mode.
* expr.c (pieces_addr::adjust): Likewise.
(can_store_by_pieces): Likewise.
(store_by_pieces): Likewise.
(clear_by_pieces_1): Likewise.
(expand_expr_addr_expr_1): Likewise.
(expand_expr_addr_expr): Use scalar_int_mode for local variables.
(expand_expr_real_1): Likewise.
(try_casesi): Likewise.
* final.c (shorten_branches): Likewise.
* fold-const.c (fold_convert_const_int_from_fixed): Change the
type of "mode" to machine_mode.
* internal-fn.c (expand_arith_overflow_result_store): Take a
scalar_int_mode rather than a machine_mode.
(expand_mul_overflow): Use scalar_int_mode for local variables.
* loop-doloop.c (doloop_modify): Likewise.
(doloop_optimize): Likewise.
* optabs.c (expand_subword_shift): Take a scalar_int_mode rather
than a machine_mode.
(expand_doubleword_shift_condmove): Likewise.
(expand_doubleword_shift): Likewise.
(expand_doubleword_clz): Likewise.
(expand_doubleword_popcount): Likewise.
(expand_doubleword_parity): Likewise.
(expand_absneg_bit): Use scalar_int_mode for local variables.
(prepare_float_lib_cmp): Likewise.
* rtl.h (convert_memory_address_addr_space_1): Take a scalar_int_mode
rather than a machine_mode.
(convert_memory_address_addr_space): Likewise.
(get_mode_bounds): Likewise.
(get_address_mode): Return a scalar_int_mode rather than a
machine_mode.
* rtlanal.c (get_address_mode): Likewise.
* stor-layout.c (get_mode_bounds): Take a scalar_int_mode rather
than a machine_mode.
* targhooks.c (default_mode_rep_extended): Likewise.
(default_valid_pointer_mode): Likewise.
(default_addr_space_valid_pointer_mode): Likewise.
(default_eh_return_filter_mode): Return a scalar_int_mode rather
than a machine_mode.
(default_libgcc_cmp_return_mode): Likewise.
(default_libgcc_shift_count_mode): Likewise.
(default_unwind_word_mode): Likewise.
(default_addr_space_pointer_mode): Likewise.
(default_addr_space_address_mode): Likewise.
* targhooks.h (default_eh_return_filter_mode): Likewise.
(default_libgcc_cmp_return_mode): Likewise.
(default_libgcc_shift_count_mode): Likewise.
(default_unwind_word_mode): Likewise.
(default_addr_space_pointer_mode): Likewise.
(default_addr_space_address_mode): Likewise.
(default_mode_rep_extended): Take a scalar_int_mode rather than
a machine_mode.
(default_valid_pointer_mode): Likewise.
(default_addr_space_valid_pointer_mode): Likewise.
* tree-ssa-address.c (addr_for_mem_ref): Use scalar_int_mode for
local variables.
* tree-ssa-loop-ivopts.c (get_shiftadd_cost): Take a scalar_int_mode
rather than a machine_mode.
* tree-switch-conversion.c (array_value_type): Use scalar_int_mode
for local variables.
* tree-vrp.c (simplify_float_conversion_using_ranges): Likewise.
* var-tracking.c (use_narrower_mode): Take a scalar_int_mode rather
than a machine_mode.
rsandifo [Wed, 30 Aug 2017 11:18:45 +0000 (11:18 +0000)]
[60/77] Pass scalar_int_modes to do_jump_by_parts_*
The callers of do_jump_by_parts_* had already established
that the modes were MODE_INTs, so this patch passes the
modes down as scalar_int_modes.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* dojump.c (do_jump_by_parts_greater_rtx): Change the type of
the mode argument to scalar_int_mode.
(do_jump_by_parts_zero_rtx): Likewise.
(do_jump_by_parts_equality_rtx): Likewise.
(do_jump_by_parts_greater): Take a mode argument.
(do_jump_by_parts_equality): Likewise.
(do_jump_1): Update calls accordingly.
rsandifo [Wed, 30 Aug 2017 11:18:37 +0000 (11:18 +0000)]
[59/77] Add a rtx_jump_table_data::get_data_mode helper
This patch adds a helper function to get the mode of the addresses
or offsets in a jump table. It also changes the final.c code to use
rtx_jump_table_data over rtx or rtx_insn in cases where it needed
to use the new helper. This in turn meant adding a safe_dyn_cast
equivalent of safe_as_a, to cope with null NEXT_INSNs.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* is-a.h (safe_dyn_cast): New function.
* rtl.h (rtx_jump_table_data::get_data_mode): New function.
(jump_table_for_label): Likewise.
* final.c (final_addr_vec_align): Take an rtx_jump_table_data *
instead of an rtx_insn *.
(shorten_branches): Use dyn_cast instead of LABEL_P and
JUMP_TABLE_DATA_P. Use jump_table_for_label and
rtx_jump_table_data::get_data_mode.
(final_scan_insn): Likewise.
rsandifo [Wed, 30 Aug 2017 11:18:12 +0000 (11:18 +0000)]
[56/77] Use the more specific type when two modes are known to be equal
This patch adjusts a couple of cases in which we had established
that two modes were equal and happened to be using the one with the
more general type instead of the one with the more specific type.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.c (expand_expr_real_2): Use word_mode instead of innermode
when the two are known to be equal.
rsandifo [Wed, 30 Aug 2017 11:18:02 +0000 (11:18 +0000)]
[55/77] Use scalar_int_mode in simplify_const_unary_operation
The main scalar integer block in simplify_const_unary_operation
had the condition:
if (CONST_SCALAR_INT_P (op) && width > 0)
where "width > 0" was a roundabout way of testing != VOIDmode.
This patch replaces it with a check for a scalar_int_mode instead.
It also uses the number of bits in the input rather than the output
mode to determine the result of a "count ... bits in zero" operation.
(At the momemnt these modes have to be the same, but it still seems
conceptually wrong to use the number of bits in the output mode.)
The handling of float->integer ops also checked "width > 0",
but this was redundant with the earlier check for MODE_INT.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* simplify-rtx.c (simplify_const_unary_operation): Use
is_a <scalar_int_mode> instead of checking for a nonzero
precision. Forcibly convert op_mode to a scalar_int_mode
in that case. More clearly differentiate the operand and
result modes and use the former when deciding what the value
of a count-bits operation should be. Use is_int_mode instead
of checking for a MODE_INT. Remove redundant check for whether
this mode has a zero precision.
rsandifo [Wed, 30 Aug 2017 11:17:54 +0000 (11:17 +0000)]
[54/77] Add explicit int checks for alternative optab implementations
expand_unop can expand narrow clz, clrsb, ctz, bswap, parity and
ffs operations using optabs for wider modes. These expansions
apply only to scalar integer modes (and not for example to vectors),
so the patch adds explicit checks for that.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* optabs.c (widen_leading): Change the type of the mode argument
to scalar_int_mode. Use opt_scalar_int_mode for the mode iterator.
(widen_bswap): Likewise.
(expand_parity): Likewise.
(expand_ctz): Change the type of the mode argument to scalar_int_mode.
(expand_ffs): Likewise.
(epand_unop): Check for scalar integer modes before calling the
above routines.
rsandifo [Wed, 30 Aug 2017 11:17:45 +0000 (11:17 +0000)]
[53/77] Pass a mode to const_scalar_mask_from_tree
The caller of const_scalar_mask_from_tree has proven that
the mode is a MODE_INT, so this patch passes it down as a
scalar_int_mode. It also expands the comment a little.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
rsandifo [Wed, 30 Aug 2017 11:17:37 +0000 (11:17 +0000)]
[52/77] Use scalar_int_mode in extract/store_bit_field
After a certain point, extract_bit_field and store_bit_field
ensure that they're dealing with integer modes or BLKmode MEMs.
This patch uses scalar_int_mode and opt_scalar_int_mode for
those parts.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expmed.c (store_bit_field_using_insv): Add op0_mode and
value_mode arguments. Use scalar_int_mode internally.
(store_bit_field_1): Rename the new integer mode from imode
to op0_mode and use it instead of GET_MODE (op0). Update calls
to store_split_bit_field, store_bit_field_using_insv and
store_fixed_bit_field.
(store_fixed_bit_field): Add op0_mode and value_mode arguments.
Use scalar_int_mode internally. Use a bit count rather than a mode
when calculating the largest bit size for get_best_mode.
Update calls to store_split_bit_field and store_fixed_bit_field_1.
(store_fixed_bit_field_1): Add mode and value_mode arguments.
Remove assertion that OP0 has a scalar integer mode.
(store_split_bit_field): Add op0_mode and value_mode arguments.
Update calls to extract_fixed_bit_field.
(extract_bit_field_using_extv): Add an op0_mode argument.
Use scalar_int_mode internally.
(extract_bit_field_1): Rename the new integer mode from imode to
op0_mode and use it instead of GET_MODE (op0). Update calls to
extract_split_bit_field, extract_bit_field_using_extv and
extract_fixed_bit_field.
(extract_fixed_bit_field): Add an op0_mode argument. Update calls
to extract_split_bit_field and extract_fixed_bit_field_1.
(extract_fixed_bit_field_1): Add a mode argument. Remove assertion
that OP0 has a scalar integer mode. Use as_a <scalar_int_mode>
on the target mode.
(extract_split_bit_field): Add an op0_mode argument. Update call
to extract_fixed_bit_field.
rsandifo [Wed, 30 Aug 2017 11:17:29 +0000 (11:17 +0000)]
[51/77] Use opt_scalar_int_mode when iterating over integer modes
This patch uses opt_scalar_int_mode rather than machine_mode
when iterating over scalar_int_modes, in cases where that helps
with future patches. (Using machine_mode is still OK in places
that don't really care about the mode being a scalar integer.)
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* cse.c (cse_insn): Use opt_scalar_int_mode for the mode iterator.
* explow.c (hard_function_value): Likewise.
* expmed.c (extract_fixed_bit_field_1): Likewise. Move the
convert_to_mode call outside the loop.
* expr.c (alignment_for_piecewise_move): Use opt_scalar_int_mode
for the mode iterator. Require the mode specified by max_pieces
to exist.
(emit_block_move_via_movmem): Use opt_scalar_int_mode for the
mode iterator.
(copy_blkmode_to_reg): Likewise.
(set_storage_via_setmem): Likewise.
* optabs.c (prepare_cmp_insn): Likewise.
* rtlanal.c (init_num_sign_bit_copies_in_rep): Likewise.
* stor-layout.c (finish_bitfield_representative): Likewise.
gcc/fortran/
* trans-types.c (gfc_init_kinds): Use opt_scalar_int_mode for
the mode iterator.
rsandifo [Wed, 30 Aug 2017 11:17:20 +0000 (11:17 +0000)]
[50/77] Add helper routines for SUBREG_PROMOTED_VAR_P subregs
When subregs contain promoted values, as indicated by
SUBREG_PROMOTED_VAR_P, both the unpromoted (outer) and
promoted (inner) values are known to be scalar integers.
This patch adds helper routines that get the modes as
scalar_int_modes.
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (subreg_unpromoted_mode, subreg_promoted_mode): New functions.
* expr.c (convert_move): Use them.
(convert_modes): Likewise.
(store_expr_with_bounds): Likewise.
rsandifo [Wed, 30 Aug 2017 11:17:12 +0000 (11:17 +0000)]
[49/77] Simplify nonzero/num_sign_bits hooks
The two implementations of the reg_nonzero_bits and reg_num_sign_bits
hooks ignored the "known_x", "known_mode" and "known_ret" arguments,
so this patch removes them. It adds a new scalar_int_mode parameter
that specifies the mode of "x". (This mode might be different from
"mode", which is the mode in which "x" is used.)
2017-08-30 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (rtl_hooks::reg_nonzero_bits): Add a scalar_int_mode
parameter for the mode of "x". Remove the "known_x", "known_mode"
and "known_ret" arguments. Change the type of the mode argument
to scalar_int_mode.
(rtl_hooks:reg_num_sign_bit_copies): Likewise.
* combine.c (reg_nonzero_bits_for_combine): Update accordingly.
(reg_num_sign_bit_copies_for_combine): Likewise.
* rtlanal.c (nonzero_bits1): Likewise.
(num_sign_bit_copies1): Likewise.
* rtlhooks-def.h (reg_nonzero_bits_general): Likewise.
(reg_num_sign_bit_copies_general): Likewise.
* rtlhooks.c (reg_num_sign_bit_copies_general): Likewise.
(reg_nonzero_bits_general): Likewise.
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