Andreas Färber [Fri, 7 Mar 2014 21:42:08 +0000 (22:42 +0100)]
xenfb: Fix graphic_console_init() build failure
In commit 5643706a095044d75df1c0588aac553a595b972b (console: add head
to index to qemu consoles.) graphic_console_init() was extended to take
an additional argument, but xenfb was not updated accordingly. Fix it.
Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Don Slutz <dslutz@verizon.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394228528-31625-1-git-send-email-afaerber@suse.de
Peter Maydell [Fri, 7 Mar 2014 18:29:32 +0000 (18:29 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/pull-input-4' into staging
Input handling rewrite.
SDL2 support.
# gpg: Signature made Wed 05 Mar 2014 11:16:08 GMT using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>"
* remotes/kraxel/tags/pull-input-4: (38 commits)
ui/sdl2 : initial port to SDL 2.0 (v2.0)
console: add QemuUIInfo
console: add head to index to qemu consoles.
input: remove index_from_keycode (no users)
input: move do_mouse_set to new core
input: move qmp_query_mice to new core
input: add input_mouse_mode tracepoint
input: move mouse mode notifier to new core
input-legacy: remove kbd_mouse_event
input-legacy: remove kbd_mouse_is_absolute
input-legacy: remove kbd_mouse_has_absolute
input-legacy: remove kbd_put_keycode
input: trace events
input: mouse: switch cocoa ui to new core
input: keyboard: switch cocoa ui to new core
input: mouse: switch monitor to new core
input: mouse: switch spice ui to new core
input: mouse: switch vnc ui to new core
input: mouse: switch sdl ui to new core
input: mouse: switch gtk ui to new core
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 7 Mar 2014 16:36:37 +0000 (16:36 +0000)]
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2014-03-05
This pull request includes:
- VSX emulation support
- book3s pr/hv selection
- some bug fixes
- qdev stable numbering
- eTSEC emulation
# gpg: Signature made Wed 05 Mar 2014 02:14:19 GMT using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found
* remotes/agraf/tags/signed-ppc-for-upstream: (130 commits)
target-ppc: spapr: e500: fix to use cpu_dt_id
target-ppc: add PowerPCCPU::cpu_dt_id
target-ppc: Introduce hypervisor call H_GET_TCE
target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab
target-ppc: Change the hpte store API
target-ppc: Fix page table lookup with kvm enabled
target-ppc: Fix htab_mask calculation
target-ppc: Use Additional Temporary in stqcx Case
target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL
PPC: sPAPR: Only use getpagesize() when we run with kvm
target-ppc/translate.c: Use ULL suffix for 64 bit constants
spapr-vlan: flush queue whenever can_receive can go from false to true
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
target-ppc: Altivec 2.07: AES Instructions
target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
target-ppc: Altivec 2.07: Doubleword Compares
target-ppc: Altivec 2.07: vbpermq Instruction
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 26 Feb 2014 21:53:30 +0000 (21:53 +0000)]
configure: Always build with -fno-common
MacOSX doesn't pull .o files from .a archives if the symbol that it
requires is one which the .o file defines as a common symbol.
(Common symbols are those declared without "extern"; the linker
will merge together common symbols with the same name, so
redeclaring the same variable in two compilation units results in
them referring to the same symbol rather than a compilation error).
This MacOSX difference from traditional linker behaviour means that
"make check" produces link errors:
Undefined symbols for architecture x86_64:
"_cur_mon", referenced from:
_error_vprintf in libqemuutil.a(qemu-error.o)
_error_printf in libqemuutil.a(qemu-error.o)
_error_printf_unless_qmp in libqemuutil.a(qemu-error.o)
_error_print_loc in libqemuutil.a(qemu-error.o)
_error_report in libqemuutil.a(qemu-error.o)
ld: symbol(s) not found for architecture x86_64
in this case because "cur_mon" is a common symbol in
libqemustub.a(mon-set-error.o).
In QEMU we don't make any use at all of the common symbol
functionality, so we can avoid this problem entirely simply
by compiling with -fno-common. Enable this option for all
builds, not just MacOSX, so that if we ever inadvertently
introduce multiple definitions of some variable that will
be immediately spotted as a build error rather than only
breaking the MacOSX build.
Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1393451610-24617-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Tue, 25 Feb 2014 18:27:49 +0000 (18:27 +0000)]
configure: Make C++ test work with --enable-werror
gcc's C++ compiler complains about being passed some -W options
which make sense for C but not for C++. This means we mustn't try
a C++ compile with QEMU_CFLAGS, but only with a filtered version
that removes the offending options. This filtering was already being
done for uses of C++ in the build itself, but was omitted for the
"does C++ work?" configure test. This only showed up when doing
builds which explicitly enabled -Werror with --enable-werror,
because the "do the compilers work" tests were mistakenly placed
above the "default werror based on whether compiling from git" code.
Another error in this category is that clang warns if you ask it to
compile C++ code from a file named "foo.c". Further, because we
were running do_cc in a subshell in the condition part of an "if",
the error_exit inside do_compiler wouldn't terminate configure and
we would plunge on regardless. Fix this complex of errors:
1. Move the default-werror code up so that there are no invocations
of compile_object and friends between it and the point where we
set $werror explicitly based on the --enable-werror command line
option.
2. Provide a mechanism for filtering QEMU_CFLAGS to create
QEMU_CXXFLAGS, and use it for the test we run here.
3. Provide a do_cxx function to run a test with the C++ compiler
rather than doing cute tricks with subshells and do_cc.
4. Use a new temporary file TMPCXX for the C++ program fragment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1393352869-22257-1-git-send-email-peter.maydell@linaro.org Tested-by: Andreas Färber <afaerber@suse.de>
Dave Airlie [Tue, 10 Dec 2013 04:05:51 +0000 (14:05 +1000)]
ui/sdl2 : initial port to SDL 2.0 (v2.0)
I've ported the SDL1.2 code over, and rewritten it to use the SDL2 interface.
The biggest changes were in the input handling, where SDL2 has done a major
overhaul, and I've had to include a generated translation file to get from
SDL2 codes back to qemu compatible ones. I'm still not sure how the keyboard
layout code works in qemu, so there may be further work if someone can point
me a test case that works with SDL1.2 and doesn't with SDL2.
Some SDL env vars we used to set are no longer used by SDL2,
Windows, OSX support is untested,
I don't think we can link to SDL1.2 and SDL2 at the same time, so I felt
using --with-sdlabi=2.0 to select the new code should be fine, like how
gtk does it.
v1.1: fix keys in text console
v1.2: fix shutdown, cleanups a bit of code, support ARGB cursor
v2.0: merge the SDL multihead patch into this, g_new the number of consoles
needed, wrap DCL inside per-console structure.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes & improvements by kraxel:
* baum build fix
* remove text console logic
* adapt to new input core
* codestyle fixups
Gerd Hoffmann [Wed, 27 Nov 2013 16:41:40 +0000 (17:41 +0100)]
input: mouse: switch legacy handlers to new core
legacy mouse event handlers are registered in the new core,
so they receive events submitted to the new input core.
legacy kbd_mouse_event() continues to use the old code paths.
So new-core event handlers wouldn't see events submitted via
kbd_mouse_event.
This leads to the constrain that we we must transition all
kbd_mouse_event() users first to keep things working. But
that is easier to handle than translating legacy mouse events
into new-core mouse events ;)
Gerd Hoffmann [Thu, 28 Nov 2013 10:29:33 +0000 (11:29 +0100)]
input: mouse: add graphic_rotate support
Transform absolute mouse events according to graphic_rotate.
Legacy input code does it for both absolute and relative events,
but the logic is broken for relative coordinates, so this is
most likely not used anyway.
Gerd Hoffmann [Wed, 27 Nov 2013 10:59:25 +0000 (11:59 +0100)]
input: keyboard: switch legacy handlers to new core
legacy kbd event handlers are registered in the new core,
so they receive events from the new input core code.
keycode -> scancode translation needed here.
legacy kbd_put_keycode() sends events to the new core.
scancode -> keycode translation needed here.
So with this patch the new input core is fully functional
for keyboard events. New + legacy interfaces can be mixed
in any way.
Gerd Hoffmann [Wed, 27 Nov 2013 08:08:40 +0000 (09:08 +0100)]
input: qapi: define event types
Define input event types, using qapi. So we get nicely autogenerated
types for our input events. And when it comes to qmp support some day
things will be a lot easier.
Types are modeled after the linux input layer. There are separate
event types for each value. There is a sync to indicate the end
of a event group.
Mouse events are split into motion events (one for each axis) and
button events, which are grouped by sync.
Keyboard events are using the existing KeyValue type.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com>
Cornelia Huck [Wed, 6 Feb 2013 09:31:37 +0000 (10:31 +0100)]
s390x/virtio-ccw: Adapter interrupt support.
Handle the new CCW_CMD_SET_IND_ADAPTER command enabling adapter interrupts
on guest request. When active, host->guest notifications will be handled
via global_indicator -> queue indicators instead of queue indicators +
subchannel I/O interrupt. Indicators for virtqueues may be present at an
offset.
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
This makes use of @cpu_dt_id and related API in:
1. emulated XICS hypercall handlers as they receive fixed CPU indexes;
2. XICS-KVM to enable in-kernel XICS on right CPU;
3. device-tree renderer.
This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor
can accept command-line CPU indexes again.
This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment
KVM CPU id and device tree ID are calculated using the same algorithm.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Normally CPUState::cpu_index is used to pick the right CPU for various
operations. However default consecutive numbering does not always work
for POWERPC.
These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX
and used to call KVM VCPU's ioctls. In order to achieve this,
kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies
cpu_index by the number of threads per core.
This approach has disadvantages such as:
1. NUMA configuration stays broken after the fixup;
2. CPU-targeted commands from the QEMU Monitor do not work properly as
CPU indexes have been fixed and there is no clear way for the user to
know what the new CPU indexes are.
This introduces a @cpu_dt_id field in the CPUPPCState struct which
is initialized from @cpu_index by default and can be fixed later
to meet the device tree requirements.
This adds an API to handle @cpu_dt_id.
This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id
is calculated in ppc_cpu_realize().
This will be used later in machine code.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Laurent Dufour [Fri, 21 Feb 2014 09:29:06 +0000 (10:29 +0100)]
target-ppc: Introduce hypervisor call H_GET_TCE
This patch introduces the hypervisor call H_GET_TCE which is basically the
reverse of H_PUT_TCE, as defined in the Power Architecture Platform
Requirements (PAPR).
The hcall H_GET_TCE is required by the kdump kernel which is calling it to
retrieve the TCE set up by the panicing kernel.
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab
This support updating htab managed by the hypervisor. Currently we don't have
any user for this feature. This actually bring the store_hpte interface
in-line with the load_hpte one. We may want to use this when we want to
emulate henter hcall in qemu for HV kvm.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ folded fix for the "warn_unused_result" build break in
kvmppc_hash64_write_pte(), Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Fix page table lookup with kvm enabled
With kvm enabled, we store the hash page table information in the hypervisor.
Use ioctl to read the htab contents. Without this we get the below error when
trying to read the guest address
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ fixes for 32 bit build (casts!), ldq_phys() API change,
Greg Kurz <gkurz@linux.vnet.ibm.com ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. We check for external htab and if
found true, we don't need to update sdr1
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ fixed pte group offset computation in ppc_hash64_htab_lookup() that
caused TCG to fail, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 24 Feb 2014 14:16:16 +0000 (08:16 -0600)]
target-ppc: Use Additional Temporary in stqcx Case
Per Alex Graf's suggestion, the recently added case to gen_conditional_store
for stqcx should use an additional temporary when accessing the second
doubleword. This avoids the mutation of the EA argument to the function,
which is counter intuitive.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
spapr-vlan: flush queue whenever can_receive can go from false to true
When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.
This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device status which now is "can
receive". The patch basically does the same thing as e8b4c68 does.
Suggested-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
Note that the implementation of vncipher deviates from the RTL in
ISA V2.07. However it does match the verbal description in the
third paragraph. The RTL will be fixed in ISA V2.07B. The
implementation here has been tested against actual P8 hardware.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:09 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts
Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register. What is desired is:
mask = (1 << (3 + log2(sizeof(element)))) - 1
but what is implemented is:
mask = (1 << (3 + (sizeof(element)/2))) - 1
This produces correct answers when "element" is uint8_t, uint16_t or uint_32t. But
it breaks down when element is uint64_t.
This patch corrects the situation. Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.
Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:01 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:00 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.
This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type. This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:57 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc
bit. QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes.
This patch introduces a generator macro that injects an auxiliary handler
which decodes both bits 21 and 31 and invokes one of four standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* flags are supported.
This patch also introduces a macro to insert two entries into the opcode
table -- one for bit 21 equal to 0 and one for bit 21 equal to 1.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:56 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions
This patch adds a macro to insert an entry into the opcode table for Altivec
Power ISA Version 2.07 instructions. The macro is similar to the GEN_VXFORM macro
except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than
PPC_ALTIVEC.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:55 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:53 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Update AVR Structure
This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:59 +0000 (11:26 -0600)]
target-ppc: Store Quadword
This patch adds support for the Store Quadword instruction in user mode. Prior
to Power ISA 2.07, stq was legal only in privileged mode. Support for Little
Endian mode is also new in ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:58 +0000 (11:26 -0600)]
target-ppc: Load Quadword
This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07. Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Little Endian
mode.
Note that this patch also adds the PPC_64BX flag to the Power8 model,
which enables the lq instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:54 +0000 (11:26 -0600)]
target-ppc: Add Target Address SPR (TAR) to Power8
This patch adds support for the Target Address Register (TAR) to the Power8
model.
Because supported SPRs are typically identified in an init_proc_*()
function and because the Power8 model is currently just using the
init_proc_POWER7() function, a new init_proc_POWER8() function
is added and plugged into the P8 model.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:25:09 +0000 (11:25 -0600)]
target-ppc: Fix xxpermdi When T==A or T==B
The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR. This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.
Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 6 Feb 2014 15:08:15 +0000 (16:08 +0100)]
qdev: Keep global allocation counter per bus
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
If we now spawn a device that connects to a ide.0 the last created
bus gets the device, with the first created bus inaccessible to the
command line.
After some discussion on IRC we concluded that the best quick fix way
forward for this is to make automated bus-class type based allocation
count a global counter. That's what this patch implements. With this
we instead get
dev: macio-ide, id ""
bus: ide.1
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
on the example mentioned above.
This also means that if you did -device ...,bus=ide.0 you got a device
on the first bus (the last created one) before this patch and get that
device on the second one (the first created one) now. Breaks
migration unless you change bus=ide.0 to bus=ide.1 on the destination.
This is intended and makes the bus enumeration work as expected.
As per review request follows a list of otherwise affected boards and
the reasoning for the conclusion that they are ok:
target machine bus id times
------ ------- ------ -----
aarch64 n800 i2c-bus.0 2
aarch64 n810 i2c-bus.0 2
arm n800 i2c-bus.0 2
arm n810 i2c-bus.0 2
-> Devices are only created explicitly on one of the two buses, using
s->mpu->i2c[0], so no change to the guest.
aarch64 vexpress-a15 virtio-mmio-bus.0 4
aarch64 vexpress-a9 virtio-mmio-bus.0 4
aarch64 virt virtio-mmio-bus.0 32
arm vexpress-a15 virtio-mmio-bus.0 4
arm vexpress-a9 virtio-mmio-bus.0 4
arm virt virtio-mmio-bus.0 32
-> Makes -device bus= work for all virtio-mmio buses. Breaks
migration. Workaround for migration from old to new: specify
virtio-mmio-bus.4 or .32 respectively rather than .0 on the
destination.
-> Makes -device bus= work for all IDE buses. Breaks migration.
Workaround for migration from old to new: specify ide.1 rather than
ide.0 on the destination.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Andreas Faerber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
projects / thirdparty / qemu.git / log
