Jonathan Wakely [Tue, 15 May 2018 12:07:09 +0000 (13:07 +0100)]
PR libstdc++/84159 fix appending strings to paths
The path::operator/=(const Source&) and path::append overloads were
still following the semantics of the Filesystem TS not C++17. Only
the path::operator/=(const path&) overload was correct.
This change adds more tests for path::operator/=(const path&) and adds
new tests to verify that the other append operations have equivalent
behaviour.
PR libstdc++/84159
* include/bits/fs_path.h (path::operator/=, path::append): Construct
temporary path before calling _M_append.
(path::_M_append): Change parameter to path and implement C++17
semantics.
* testsuite/27_io/filesystem/path/append/path.cc: Add helper function
and more examples from the standard.
* testsuite/27_io/filesystem/path/append/source.cc: New.
* testsuite/27_io/filesystem/path/decompose/filename.cc: Add comment.
* testsuite/27_io/filesystem/path/nonmember/append.cc: New.
* tree-ssa-dse.c (dse_classify_store): Remove use_stmt parameter,
add by_clobber_p one. Change algorithm to collect all defs
representing uses we need to walk and try reducing them to
a single one before failing.
(dse_dom_walker::dse_optimize_stmt): Adjust.
Mark Wielaard [Tue, 15 May 2018 08:37:46 +0000 (08:37 +0000)]
DWARF: Use DW_OP_addrx and DW_OP_constx for DWARF5.
For older DWARF and -gsplit-dwarf we want to emit DW_OP_GNU_addr_index
and DW_OP_GNU_const_index, but for DWARF5 we should use DW_OP_addrx
and DW_OP_constx.
gcc/ChangeLog:
* dwarf2out.c (dwarf_OP): Handle DW_OP_addrx and DW_OP_constx.
(size_of_loc_descr): Likewise.
(output_loc_operands): Likewise.
(output_loc_operands_raw): Likewise.
(dw_addr_op): Use dwarf_OP () for DW_OP_constx and DW_OP_addrx.
(resolve_addr_in_expr): Handle DW_OP_addrx and DW_OP_constx.
(hash_loc_operands): Likewise.
(compare_loc_operands): Likewise.
Mark Wielaard [Tue, 15 May 2018 08:34:29 +0000 (08:34 +0000)]
DWARF calculate the number of indexed addresses.
The length in the .debug_addr unit header was calculated using the number
of elements in the addr_index_table. This is wrong because the entries in
the table are refcounted and only those with a refcount > 0 are actually
put in the index. Add a helper function count_index_addrs to get the
correct number of addresses in the index.
gcc/ChangeLog:
* dwarf2out.c (count_index_addrs): New function.
(dwarf2out_finish): Use count_index_addrs to calculate addrs_length.
Jason Merrill [Mon, 14 May 2018 20:08:11 +0000 (16:08 -0400)]
Handle TYPE_HAS_LATE_RETURN_TYPE like ref-qualifier and eh spec.
* tree.c (build_cp_fntype_variant): New.
(build_ref_qualified_type, build_exception_variant)
(strip_typedefs, cxx_copy_lang_qualifiers): Use it.
(cxx_type_hash_eq, cp_check_qualified_type): Check
TYPE_HAS_LATE_RETURN_TYPE.
(cp_build_type_attribute_variant): Check cxx_type_hash_eq.
(cp_build_qualified_type_real): No need to preserve C++ qualifiers.
* class.c (build_clone): Use cxx_copy_lang_qualifiers.
(adjust_clone_args): Likewise.
* decl.c (grokfndecl): Add late_return_type_p parameter. Use
build_cp_fntype_variant.
(grokdeclarator): Pass late_return_type_p to grokfndecl.
(check_function_type): Use cxx_copy_lang_qualifiers.
(static_fn_type): Use cxx_copy_lang_qualifiers.
* decl2.c (build_memfn_type, maybe_retrofit_in_chrg)
(cp_reconstruct_complex_type, coerce_new_type, coerce_delete_type)
(change_return_type): Use cxx_copy_lang_qualifiers.
* mangle.c (write_type): Use cxx_copy_lang_qualifiers.
* parser.c (cp_parser_lambda_declarator_opt): Represent an explicit
return type on the declarator like a normal trailing return type.
* pt.c (tsubst_function_type): Use build_cp_fntype_variant.
(copy_default_args_to_explicit_spec): Use cxx_copy_lang_qualifiers.
* typeck.c (merge_types): Use build_cp_fntype_variant.
Jonathan Wakely [Mon, 14 May 2018 18:57:45 +0000 (19:57 +0100)]
PR libstdc++/81256 fix exception handling in basic_filebuf::close
PR libstdc++/81256
* include/bits/fstream.tcc (basic_filebuf::close): Do not swallow
exceptions from _M_terminate_output().
* include/std/fstream (basic_filebuf::~basic_filebuf): Swallow any
exceptions from close().
* testsuite/27_io/basic_filebuf/close/81256.cc: New.
Kyrylo Tkachov [Mon, 14 May 2018 16:29:13 +0000 (16:29 +0000)]
[AArch64] Add combine pattern to fuse AESE/AESMC instructions
When the AESE,AESD and AESMC, AESMC instructions are generated through the appropriate arm_neon.h intrinsics
we really want to keep them together when the AESE feeds into an AESMC and fusion is supported by the target CPU.
We have macro-fusion hooks and scheduling model forwarding paths defined to facilitate that.
It is, however, not always enough.
This patch adds another mechanism for doing that.
When we can detect during combine that the required dependency is exists (AESE -> AESMC, AESD -> AESIMC)
just keep them together with a combine pattern throughout the rest of compilation.
We won't ever want to split them.
The testcases generate 4 AESE(D) instructions in a block followed by 4 AES(I)MC instructions that
consume the corresponding results and it also adds a bunch of computations in-between so that the
AESE and AESMC instructions are not trivially back-to-back, thus exercising the compiler's ability
to bring them together.
With this patch all 4 pairs are fused whereas before a couple of fusions would be missed due to intervening
arithmetic and memory instructions.
* config/aarch64/aarch64-simd.md (*aarch64_crypto_aese_fused):
New pattern.
(aarch64_crypto_aesd_fused): Likewise.
* gcc.target/aarch64/crypto-fuse-1.c: New test.
* gcc.target/aarch64/crypto-fuse-2.c: Likewise.
Wilco Dijkstra [Mon, 14 May 2018 16:10:19 +0000 (16:10 +0000)]
Remove remaining uses of * in patterns
Remove the remaining uses of '*' from aarch64.md.
Using '*' in alternatives is typically incorrect as it tells the register
allocator to ignore those alternatives. Also add a missing '?' so we
prefer a floating point register for same-size int<->fp conversions.
gcc/
* config/aarch64/aarch64.md (mov<mode>): Remove '*' in alternatives.
(movsi_aarch64): Likewise.
(load_pairsi): Likewise.
(load_pairdi): Likewise.
(store_pairsi): Likewise.
(store_pairdi): Likewise.
(load_pairsf): Likewise.
(load_pairdf): Likewise.
(store_pairsf): Likewise.
(store_pairdf): Likewise.
(zero_extend): Likewise.
(trunc): Swap alternatives.
(fcvt_target): Add '?' to prefer w over r.
Jakub Jelinek [Mon, 14 May 2018 15:53:58 +0000 (17:53 +0200)]
re PR target/85756 (wrong code at -Os on x86-64-linux-gnu in 32-bit mode)
PR target/85756
* config/i386/i386.md: Disallow non-commutative arithmetics in
last twpeephole for mem {+,-,&,|,^}= x; mem != 0 after cmpelim
optimization. Use COMMUTATIVE_ARITH_P test rather than != MINUS
in the peephole2 before it.
Jonathan Wakely [Mon, 14 May 2018 14:27:54 +0000 (15:27 +0100)]
PR libstdc++/82966 fix swapping of node handles
PR libstdc++/82966
* include/bits/node_handle.h (_Node_handle_common::_M_swap): Use value
instead of type.
* testsuite/23_containers/set/modifiers/node_swap.cc: New.
Paul Thomas [Sun, 13 May 2018 17:01:16 +0000 (17:01 +0000)]
re PR fortran/85742 (sizeof allocatable arrays returning wrong value)
2018-05-13 Paul Thomas <pault@gcc.gnu.org>
PR fortran/85742
* trans-types.c (gfc_get_dtype_rank_type): Reorder evaluation
of 'size'. If the element type is a pointer use the size of the
TREE_TYPE of the type, unless it is VOID_TYPE. In this latter
case, set the size to zero.
2018-05-13 Paul Thomas <pault@gcc.gnu.org>
PR fortran/85742
* gfortran.dg/assumed_type_9.f90 : New test.
Michael Meissner [Fri, 11 May 2018 22:47:03 +0000 (22:47 +0000)]
rs6000.md (mov<mode>_softfloat, FMOVE32): Reformat alternatives and attributes so it is easier to identify which...
2018-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (mov<mode>_softfloat, FMOVE32):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.
(mov<mode>_hardfloat32, FMOVE64): Likewise.
(mov<mode>_softfloat32, FMOVE64): Likewise.
(mov<mode>_hardfloat64, FMOVE64): Likewise.
(mov<mode>_softfloat64, FMOVE64): Likewise.
Kelvin Nilsen [Fri, 11 May 2018 16:53:38 +0000 (16:53 +0000)]
extend.texi (PowerPC Built-in Functions): Rename this subsection.
gcc/ChangeLog:
2018-05-11 Kelvin Nilsen <kelvin@gcc.gnu.org>
* doc/extend.texi (PowerPC Built-in Functions): Rename this
subsection.
(Basic PowerPC Built-in Functions): The new name of the
subsection previously known as "PowerPC Built-in Functions".
(Basic PowerPC Built-in Functions Available on all Configurations):
New subsubsection.
(Basic PowerPC Built-in Functions Available on ISA 2.05): Likewise.
(Basic PowerPC Built-in Functions Available on ISA 2.06): Likewise.
(Basic PowerPC Built-in Functions Available on ISA 2.07): Likewise.
(Basic PowerPC Built-in Functions Available on ISA 3.0): Likewise.
Richard Earnshaw [Fri, 11 May 2018 13:29:41 +0000 (13:29 +0000)]
[arm] PR target/85733 Restore be8 linking behaviour for ARMv6-M and products deriving from its capabilities
My patch last year to automate passing the be8 flag to the linker had
a nasty flaw in that I forgot entirely that the ARMv6-M architecture
did not derive its capabilities directly from the ARMv6 capability
list, but was a new group of capabilities (since it needs to leave out
the ARM -- notm -- feature bit). The feature list defined was thus
missing the be8 bit. Furthermore, any product derived from that
feature group consequently lacked the be8 feature as well and this
included all ARMv7 and ARMv8 parts.
Richard Earnshaw [Fri, 11 May 2018 09:28:10 +0000 (09:28 +0000)]
[arm] PR target/85606 prefer armv6s-m for armv6-m parts
When Arm introduced ARMv6-M there were two variants, ARMv6-M and
ARMv6S-M. The two differed only in support for the SVC instruction.
Later on SVC was then made a mandatory part of ARMv6-M and the
ARMv6S-M name was dropped. GCC and GAS, however still recognize both
names and at least some versions of GAS still distinguish between the
two.
To address this, this patch changes the architecture for the ARMv6-m
cortex parts (m0, m0plus, m1 and the variants will small multiply
units) to use the ARMv6S-M name in conjunction with the assembler.
This avoids problems with them rejecting code that was previously
accepted with older versions of GCC where we did not pass an explicit
architecture string through to the compiler when using -mcpu on the
command line.
PR target/85606
* config/arm/arm-cpus.in: Add comment that ARMv6-m and ARMv6S-m are now
equivalent.
(cortex-m0): Use armv6s-m isa.
(cortex-m0plus): Likewise.
(cortex-m1): Likewise.
(cortex-m0.small-multiply): Likewise.
(cortex-m0plus.small-multiply): Likewise.
(cortex-m1.small-multiply): Likewise.
Jakub Jelinek [Fri, 11 May 2018 07:42:50 +0000 (09:42 +0200)]
re PR c/85696 (OpenMP with variably modified and default(none) won't compile)
PR c/85696
* c-omp.c (c_omp_predetermined_sharing): Return
OMP_CLAUSE_DEFAULT_SHARED for artificial vars with integral type.
* cp-tree.h (cxx_omp_predetermined_sharing_1): New prototype.
* cp-gimplify.c (cxx_omp_predetermined_sharing): New wrapper around
cxx_omp_predetermined_sharing_1. Rename old function to ...
(cxx_omp_predetermined_sharing_1): ... this.
* semantics.c (finish_omp_clauses): Use cxx_omp_predetermined_sharing_1
instead of cxx_omp_predetermined_sharing.
Michael Meissner [Thu, 10 May 2018 22:46:21 +0000 (22:46 +0000)]
rs6000.c (mode_supports_dq_form): Rename mode_supports_vsx_dform_quad to mode_supports_dq_form.
2018-05-10 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (mode_supports_dq_form): Rename
mode_supports_vsx_dform_quad to mode_supports_dq_form.
(mode_supports_vsx_dform_quad): Likewise.
(mode_supports_vmx_dform): Move these functions to be next to the
other mode_supports functions.
(mode_supports_dq_form): Likewise.
(quad_address_p): Change calls of mode_supports_vsx_dform_quad to
mode_supports_dq_form.
(reg_offset_addressing_ok_p): Likewise.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_secondary_reload_inner): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Likewise.
Jonathan Wakely [Thu, 10 May 2018 19:13:42 +0000 (20:13 +0100)]
Document Dual ABI for std::ios_base::failure
* doc/xml/faq.xml: Link to C++17 status. Add note to outdated answer.
* doc/xml/manual/debug_mode.xml: Add array and forward_list to list
of C++11 containers with Debug Mode support.
* doc/xml/manual/using.xml: Document Dual ABI for ios_base::failure.
* doc/html/*: Regenerate.
Jakub Jelinek [Thu, 10 May 2018 17:40:28 +0000 (19:40 +0200)]
re PR c++/85662 ("error: non-constant condition for static assertion" from __builtin_offsetof in C++)
PR c++/85662
* c-common.h (fold_offsetof_1): Removed.
(fold_offsetof): Add TYPE argument defaulted to size_type_node and
CTX argument defaulted to ERROR_MARK.
* c-common.c (fold_offsetof_1): Renamed to ...
(fold_offsetof): ... this. Remove wrapper function. Add TYPE
argument, convert the pointer constant to TYPE and use size_binop
with PLUS_EXPR instead of fold_build_pointer_plus if type is not
a pointer type. Adjust recursive calls.
* c-fold.c (c_fully_fold_internal): Use fold_offsetof rather than
fold_offsetof_1, pass TREE_TYPE (expr) as TYPE to it and drop the
fold_convert_loc.
* c-typeck.c (build_unary_op): Use fold_offsetof rather than
fold_offsetof_1, pass argtype as TYPE to it and drop the
fold_convert_loc.
* cp-gimplify.c (cp_fold): Use fold_offsetof rather than
fold_offsetof_1, pass TREE_TYPE (x) as TYPE to it and drop the
fold_convert.
Jakub Jelinek [Thu, 10 May 2018 07:38:24 +0000 (09:38 +0200)]
re PR tree-optimization/85699 (gcc.dg/nextafter-2.c fail)
PR tree-optimization/85699
* gcc.dg/nextafter-1.c (NO_LONG_DOUBLE): Define if not defined. Use
!NO_LONG_DOUBLE instead of __LDBL_MANT_DIG__ != 106.
* gcc.dg/nextafter-2.c: Include stdlib.h. For glibc < 2.24 define
NO_LONG_DOUBLE to 1 before including nextafter-1.c.
Eric Botcazou [Thu, 10 May 2018 07:36:38 +0000 (07:36 +0000)]
re PR c++/85400 (invalid Local Dynamic TLS relaxation for symbol defined in method)
PR c++/85400
cp/
* decl2.c (adjust_var_decl_tls_model): New static function.
(comdat_linkage): Call it on a variable.
(maybe_make_one_only): Likewise.
c-family/
* c-attribs.c (handle_visibility_attribute): Do not set no_add_attrs.
go/build, cmd/go: update to match recent changes to gc
Several recent changes to the gc version of cmd/go improve the
gofrontend support. These changes are partially copies of existing
gofrontend differences, and partially new code. This CL makes the
gofrontend match the upstream code.
The changes included here come from:
https://golang.org/cl/111575
https://golang.org/cl/111595
https://golang.org/cl/111635
https://golang.org/cl/111636
For the record, the following recent gc changes are based on code
already present in the gofrontend repo:
https://golang.org/cl/110915
https://golang.org/cl/111615
For the record, a gc change, partially based on earlier gofrontend
work, also with new gc code, was already copied to gofrontend repo in
CL 111099:
https://golang.org/cl/111097
This moves the generated list of standard library packages from
cmd/go/internal/load to go/build.
Paolo Carlini [Wed, 9 May 2018 16:19:09 +0000 (16:19 +0000)]
re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)
/cp
2018-05-09 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/85713
Revert:
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/84588
* parser.c (cp_parser_parameter_declaration_list): When the
entire parameter-declaration-list is erroneous maybe call
abort_fully_implicit_template.
/testsuite
2018-05-09 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/85713
Revert:
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com>
Paolo Carlini [Wed, 9 May 2018 16:17:36 +0000 (16:17 +0000)]
re PR c++/85713 (ICE in dependent_type_p, at cp/pt.c:24582 on valid code)
/cp
2018-05-09 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/85713
Revert:
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/84588
* parser.c (cp_parser_parameter_declaration_list): When the
entire parameter-declaration-list is erroneous maybe call
abort_fully_implicit_template.
/testsuite
2018-05-09 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/85713
Revert:
2018-05-08 Paolo Carlini <paolo.carlini@oracle.com>
Jonathan Wakely [Wed, 9 May 2018 13:28:11 +0000 (14:28 +0100)]
Make std::function tolerate semantically non-CopyConstructible objects
To satisfy the CopyConstructible requirement a callable object stored in
a std::function must behave the same when copied from a const or
non-const source. If copying a non-const object doesn't produce an
equivalent copy then the behaviour is undefined. But we can make our
std::function more tolerant of such objects by ensuring we always copy
from a const lvalue.
Additionally use an if constexpr statement in the _M_get_pointer
function to avoid unnecessary instantiations in the discarded branch.
* include/bits/std_function.h (_Base_manager::_M_get_pointer):
Use constexpr if in C++17 mode.
(_Base_manager::_M_clone(_Any_data&, const _Any_data&, true_type)):
Copy from const object.
* testsuite/20_util/function/cons/non_copyconstructible.cc: New.
Richard Biener [Wed, 9 May 2018 13:04:00 +0000 (13:04 +0000)]
tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost vector.
2018-05-09 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_bb_slp_scalar_cost): Fill a cost
vector.
(vect_bb_vectorization_profitable_p): Adjust. Compute
actual scalar cost using the cost vector and the add_stmt_cost
machinery.
rs6000: Give an argument to every REG_CFA_REGISTER (PR85645)
The one for the prologue mflr did not have any value set, which means
use the SET that is in the insn pattern. This works fine, except when
some late pass decides to replace the SET_SRC -- this changes the
meaning of the REG_CFA_REGISTER! Such passes should not do these
things, but let's be more explicit here, for extra robustness. It
could be argued that this defaulting is a design misfeature (it does
not save much space either, etc.)
PR rtl-optimization/85645
* config/rs6000/rs6000.c (rs6000_emit_prologue_components): Put a SET
in the REG_CFA_REGISTER note for LR, don't leave it empty.
In the testcase for PR85645 we do a pretty dumb placement of the
prologue/epilogue for the LR component: we place an epilogue for LR
before a control flow split where one of the branches clobbers LR
eventually, and the other does not. The branch that does clobber it
will need a prologue again some time later. Because saving and
restoring LR is a two step process---it needs to be moved via a GPR---
the backend emits CFI directives so that we get correct unwind
information. But both regcprop and regrename do not properly handle
such CFI directives leading to ICEs.
Now, neither of the two branches needs to have LR restored at all,
because both of the branches end up in an infinite loop.
This patch makes spread_component return a boolean saying if anything
was changed, and if so, it is called again. This obviously is finite
(there is a finite number of basic blocks, each with a finite number
of components, and spread_components can only assign more components
to a block, never less). I also instrumented the code, and on a
bootstrap+regtest spread_components made changes a maximum of two
times. Interestingly though it made changes on two iterations in
a third of the cases it did anything at all!
PR rtl-optimization/85645
* shrink-wrap.c (spread_components): Return a boolean saying if
anything was changed.
(try_shrink_wrapping_separate): Iterate spread_components until
nothing changes anymore.
regrename: Don't rename the dest of a REG_CFA_REGISTER (PR85645)
We should never change the destination of a REG_CFA_REGISTER, just
like for insns with a REG_CFA_RESTORE, because we need to have the
same control flow information on all branches that join. It is very
doubtful that renaming the scratch registers used for prologue/epilogue
will help anything either.
PR rtl-optimization/85645
* regrename.c (build_def_use): Also kill the chains that include the
destination of a REG_CFA_REGISTER note.
Changing a SET that has a REG_CFA_REGISTER note is wrong if we are
changing the SET_DEST, or if the REG_CFA_REGISTER has nil as its
argument, and maybe some other cases. It's never really useful to
propagate into such an instruction, so let's just bail whenever we
see such a note.
PR rtl-optimization/85645
* regcprop.c (copyprop_hardreg_forward_1): Don't propagate into an
insn that has a REG_CFA_REGISTER note.
We build up the input to IFN_STORE_LANES one vector at a time.
In RTL, each of these vector assignments becomes a write to
subregs of the form (subreg:VEC (reg:AGGR R)), where R is the
eventual input to the store lanes instruction. The problem is
that RTL isn't very good at tracking liveness when things are
initialised piecemeal by subregs, so R tends to end up being
live on all paths from the entry block to the store. This in
turn leads to unnecessary spilling around calls, as well as to
excess register pressure in vector loops.
This patch adds gimple clobbers to indicate the liveness of the
IFN_STORE_LANES variable and makes sure that gimple clobbers are
expanded to rtl clobbers where useful. For consistency it also
uses clobbers to mark the point at which an IFN_LOAD_LANES
variable is no longer needed.
2018-05-08 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* cfgexpand.c (expand_clobber): New function.
(expand_gimple_stmt_1): Use it.
* tree-vect-stmts.c (vect_clobber_variable): New function,
split out from...
(vectorizable_simd_clone_call): ...here.
(vectorizable_store): Emit a clobber either side of an
IFN_STORE_LANES sequence.
(vectorizable_load): Emit a clobber after an IFN_LOAD_LANES sequence.
gcc/testsuite/
* gcc.target/aarch64/store_lane_spill_1.c: New test.
* gcc.target/aarch64/sve/store_lane_spill_1.c: Likewise.
projects / thirdparty / gcc.git / log
