wilco [Mon, 16 May 2016 12:52:22 +0000 (12:52 +0000)]
Some patterns are using '%w2' for immediate operands, which means that a zero
immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an
immediate operand into a register operand but may emit illegal instructions
from legal RTL (eg. ORR x0, SP, xzr rather than ORR x0, SP, 0).
* config/aarch64/aarch64.md
(add<mode>3_compareC_cconly_imm): Remove use of %w.
(add<mode>3_compareC_imm): Likewise.
(<optab>si3_uxtw): Split into register and immediate variants.
(andsi3_compare0_uxtw): Likewise.
(and<mode>3_compare0): Likewise.
(and<mode>3nr_compare0): Likewise.
(stack_protect_test_<mode>): Don't use %x for memory operands.
ebotcazou [Mon, 16 May 2016 11:16:42 +0000 (11:16 +0000)]
* freeze.adb (Freeze_Array_Type): Call Addressable predicate instead
of testing for individual sizes.
(Freeze_Entity): Rework implementation of pragma Implicit_Packing for
array types, in particular test for suitable sizes upfront and do not
mimic the processing that will be redone later in Freeze_Array_Type.
ebotcazou [Mon, 16 May 2016 11:08:53 +0000 (11:08 +0000)]
* doc/gnat_rm/implementation_defined_attributes.rst
(Scalar_Storage_Order): Adjust restriction for packed array types.
* einfo.ads (Is_Bit_Packed_Array): Adjust description.
(Is_Packed): Likewise.
(Is_Packed_Array_Impl_Type): Likewise.
(Packed_Array_Impl_Type): Likewise.
* exp_ch4.adb (Expand_N_Indexed_Component): Do not do anything special
if the prefix is not a packed array implemented specially.
* exp_ch6.adb (Expand_Actuals): Expand indexed components only for
bit-packed array types.
* exp_pakd.adb (Install_PAT): Set Is_Packed_Array_Impl_Type flag on
the PAT before analyzing its declaration.
(Create_Packed_Array_Impl_Type): Remove redundant statements.
* freeze.adb (Check_Component_Storage_Order): Reject packed array
components only if they are bit packed.
(Freeze_Array_Type): Fix logic detecting bit packing and do not bit
pack for composite types whose size is multiple of a byte.
Create the implementation type for packed array types only when it is
needed, i.e. bit packing or packing because of holes in index types.
Make sure the Has_Non_Standard_Rep and Is_Packed flags agree.
* gcc-interface/gigi.h (make_packable_type): Add MAX_ALIGN parameter.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Signed_Integer_Subtype>:
Call maybe_pad_type instead of building the padding type manually.
(gnat_to_gnu_entity) <E_Array_Subtype>: Do not assert that
Packed_Array_Impl_Type is present for packed arrays.
(gnat_to_gnu_component_type): Also handle known alignment for packed
types by passing it to make_packable_type.
* gcc-interface/utils.c (make_packable_type): Add MAX_ALIGN parameter
and deal with it in the array case. Adjust recursive call. Simplify
computation of new size and cap the alignment to BIGGEST_ALIGNMENT.
wilco [Mon, 16 May 2016 11:01:36 +0000 (11:01 +0000)]
This patch fixes the attributes of integer immediate shifts which were
incorrectly modelled as register controlled shifts. Also change EXTR
attribute to being a rotate.
* gcc/config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3):
Split integer shifts into shift_reg and bfm.
(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
(ror<mode>3_insn): Likewise.
(<optab>si3_insn_uxtw): Likewise.
(<optab><mode>3_insn): Change to rotate_imm.
(extr<mode>5_insn_alt): Likewise.
(extrsi5_insn_uxtw): Likewise.
(extrsi5_insn_uxtw_alt): Likewise.
mwahab [Mon, 16 May 2016 10:22:25 +0000 (10:22 +0000)]
Remove TARGET_INVALID_PARAMETER_TYPE and TARGET_INVALID_RETURN_TYPE hooks.
c/
2016-05-16 Matthew Wahab <matthew.wahab@arm.com>
* c-decl.c (grokdeclarator): Remove errmsg and use of
targetm.invalid_return_type.
(grokparms): Remove errmsg and use of
targetm.invalid_parameter_type.
cp/
2016-05-16 Matthew Wahab <matthew.wahab@arm.com>
* decl.c (grokdeclarator): Remove errmsg and use of
targetm.invalid_return_type.
(grokparms): Remove errmsg and use of
targetm.invalid_parameter_type.
gcc/
2016-05-16 Matthew Wahab <matthew.wahab@arm.com>
ebotcazou [Mon, 16 May 2016 10:14:19 +0000 (10:14 +0000)]
* exp_util.adb (Remove_Side_Effects): Also make a constant if we need
to capture the value for a small not by-reference record type.
* freeze.ads (Check_Compile_Time_Size): Adjust comment.
* freeze.adb (Set_Small_Size): Likewise. Accept a size in the range
of 33 .. 64 bits.
(Check_Compile_Time_Size): Merge scalar and access type cases. Change
variable name in array type case. For the computation of the packed
size, deal with record components and remove redundant test.
(Freeze_Array_Type): Also adjust packing status when the size of the
component type is in the range 33 .. 64 bits.
* doc/gnat_rm/representation_clauses_and_pragmas.rst: Turn primitive
into elementary type throughout. Minor tweaks.
(Alignment Clauses): Document actual alignment of packed array types.
(Pragma Pack for Arrays): List only the 3 main cases and adjust. Add
"simple" to the record case. Document effect on non packable types.
(Pragma Pack for Records): Likewise. Add record case and adjust.
hubicka [Mon, 16 May 2016 10:10:28 +0000 (10:10 +0000)]
* ipa-inline-analysis.c (compute_inline_parameters): Be more reailistic
on estimating thunk bodies; do not set inline_failed to CIF_THUNK for
calls from thunk.
* ipa-inline-transform.c (inline_call): When inlining into thunk produce
gimple body.
(preserve_function_body_p): No need to preserve function body
* cif-codes.def (CIF_THUNK): Remove.
* cgraphclones.c (duplicate_thunk_for_node): Thunks calls are inlinable.
* g++.dg/ipa/ivinline-7.C: Do not xfail.
* g++.dg/ipa/ivinline-9.C: Do not xfail.
ebotcazou [Mon, 16 May 2016 08:55:12 +0000 (08:55 +0000)]
gnattools/
* configure.ac: Add ACX_NONCANONICAL_HOST.
* configure: Regenerate.
* Makefile.in: Replace host_alias with host_noncanonical.
(gnattools-cross): Do not rename the tools.
gcc/
* configure.ac: Add ACX_NONCANONICAL_HOST.
* configure: Regenerate.
* Makefile.in: Set host_noncanonical.
gcc/ada
* gcc-interface/Make-lang.in (GNATMAKE_FOR_HOST): In the canadian
cross case, use host_noncanonical instead of host as prefix.
(GNATBIND_FOR_HOST): Likewise.
(GNATLINK_FOR_HOST): Likewise.
(GNATLS_FOR_HOST): Likewise.
uros [Sat, 14 May 2016 13:22:45 +0000 (13:22 +0000)]
PR target/71097
* config/i386/i386.md (*movtf_internal): Before register allocation,
do not allow FP constants for CM_MEDIUM memory model, allow only
standard FP constants for CM_LARGE and CM_LARGE_PIC models.
(*movxf_internal): Ditto.
(*movdf_internal): Ditto.
(*movsf_internal): Ditto.
segher [Fri, 13 May 2016 23:01:40 +0000 (23:01 +0000)]
combine: Don't call extract_left_shift with count < 0 (PR67483)
If the compiled program does a shift by a negative amount, combine will
happily work with that, but it shouldn't then do an undefined operation
in GCC itself. This patch fixes the first case mentioned in the bug
report (I haven't been able to reproduce the second case, on trunk at
least).
jsm28 [Fri, 13 May 2016 21:35:39 +0000 (21:35 +0000)]
Implement C11 DR#423 resolution (ignore function return type qualifiers).
The resolution of C11 DR#423, apart from doing things with the types
of expressions cast to qualified types which are only in standard
terms observable with _Generic and which agree with how GCC has
implemented _Generic all along, also specifies that qualifiers are
discarded from function return types: "derived-declarator-type-list
function returning T" becomes "derived-declarator-type-list function
returning the unqualified version of T" in the rules giving types for
function declarators. This means that declarations of a function with
both qualified and unqualified return types are now compatible,
similar to how different declarations can vary in whether a function
argument is declared with a qualifier or unqualified type.
This patch implements this resolution. Since the motivation for the
change was _Generic, the resolution is restricted to C11 mode; there's
no reason to consider there to be a defect in this regard in older
standard versions. Some less-obvious issues are handled as follows:
* As usual, and as with function arguments, _Atomic is not considered
a qualifier for this purpose; that is, function declarations must
agree regarding whether the return type is atomic.
* By 6.9.1#2, a function definition cannot return qualified void. But
with this change, specifying "const void" in the declaration
produces the type "function returning void", which is perfectly
valid, so "const void f (void) {}" is no longer an error.
* The application to restrict is less clear. The way I am
interpreting it in this patch is that "unqualified version of T" is
not valid if T is not valid, as in the case where T is a
restrict-qualified version of a type that cannot be restrict
qualified (non-pointer, or pointer-to-function). But it's possible
to argue the other way from the wording.
Bootstrapped with no regressions on x86_64-pc-linux-gnu.
gcc/c:
* c-decl.c (grokdeclarator): For C11, discard qualifiers on
function return type.
gcc/testsuite:
* gcc.dg/qual-return-5.c, gcc.dg/qual-return-6.c: New tests.
* gcc.dg/call-diag-2.c, gcc.dg/qual-return-2.c ,
gcc.dg/qual-return-3.c, gcc.dg/qual-return-4.c: Use -std=gnu99.
ian [Fri, 13 May 2016 20:42:36 +0000 (20:42 +0000)]
escape: Implement the discovery phase.
Implements the discovery phase according the SCC algorithm used in
gc/esc.go. Traverse all functions to find components that are either
trivial or recursive. The discovered function groups will be analyzed
from the bottom-up to allow for an inter-procedural analysis.
jason [Fri, 13 May 2016 19:18:35 +0000 (19:18 +0000)]
Fix type-dependence and the current instantiation.
PR c++/10200
PR c++/69753
* pt.c (tsubst_decl): Use uses_template_parms.
(instantiate_template_1): Handle non-dependent calls in templates.
(value_dependent_expression_p): Handle BASELINK, FUNCTION_DECL.
(type_dependent_expression_p): Only consider innermost template args.
(dependent_template_arg_p): Check enclosing class of a template here.
(dependent_template_p): Not here.
(type_dependent_object_expression_p): New.
* typeck.c (finish_class_member_access_expr): Use it.
* parser.c (cp_parser_postfix_expression): Use it.
(cp_parser_postfix_dot_deref_expression): Use it. Use comptypes
to detect the current instantiation.
(cp_parser_lookup_name): Really implement DR 141.
* search.c (lookup_field_r): Prefer a dependent using-declaration.
(any_dependent_bases_p): Split out from...
* name-lookup.c (do_class_using_decl): ...here.
* call.c (build_new_method_call_1): Use it.
* semantics.c (finish_call_expr): 'this' doesn't make a call dependent.
* tree.c (non_static_member_function_p): Remove.
* typeck2.c (build_x_arrow): Use dependent_scope_p.
ienkovich [Fri, 13 May 2016 09:55:58 +0000 (09:55 +0000)]
gcc/
* cse.c (rest_of_handle_cse): Use cleanup_cfg
returned value cse_cfg_altered computation.
(rest_of_handle_cse2): Likewise.
(rest_of_handle_cse_after_global_opts): Likewise.
ramana [Fri, 13 May 2016 09:23:28 +0000 (09:23 +0000)]
Set TARGET_OMIT_STRUCT_RETURN_REG to true
The reason this caught my eye on aarch64 is because
the return value register (x0) is not identical to the register in which
the hidden parameter for AArch64 is set (x8). Thus setting this to true
seems to be quite reasonable and shaves off 100 odd mov x0, x8's from
cc1 in a bootstrap build.
I don't expect this to make a huge impact on performance but as they
say every little counts. The AAPCS64 is quite explicit about not
requiring that the contents of x8 be kept live.
Bootstrapped and regression tested on aarch64.
Ok to apply ?
Ramana
gcc/
* config/aarch64/aarch64.c (TARGET_OMIT_STRUCT_RETURN_REG): Set to
true.
uros [Thu, 12 May 2016 18:34:54 +0000 (18:34 +0000)]
* config/i386/i386.md (*call_got_x32): Change operand 0 to
DImode before it is passed to ix86_output_call_operand.
(*call_value_got_x32): Ditto for operand 1.
mpolacek [Thu, 12 May 2016 15:28:08 +0000 (15:28 +0000)]
PR c/70756
* c-common.c (pointer_int_sum): Call size_in_bytes_loc instead of
size_in_bytes and pass LOC to it.
* c-decl.c (build_compound_literal): Pass LOC down to
c_incomplete_type_error.
* c-tree.h (require_complete_type): Adjust declaration.
(c_incomplete_type_error): Likewise.
* c-typeck.c (require_complete_type): Add location parameter, pass it
down to c_incomplete_type_error.
(c_incomplete_type_error): Add location parameter, pass it down to
error_at.
(build_component_ref): Pass location down to c_incomplete_type_error.
(default_conversion): Pass location down to require_complete_type.
(build_array_ref): Likewise.
(build_function_call_vec): Likewise.
(convert_arguments): Likewise.
(build_unary_op): Likewise.
(build_c_cast): Likewise.
(build_modify_expr): Likewise.
(convert_for_assignment): Likewise.
(c_finish_omp_clauses): Likewise.
* call.c (build_new_op_1): Pass LOC to cp_build_modify_expr.
* cp-tree.h (cp_build_modify_expr): Update declaration.
(cxx_incomplete_type_error, cxx_incomplete_type_diagnostic): New inline
overloads.
* cp-ubsan.c (cp_ubsan_dfs_initialize_vtbl_ptrs): Pass INPUT_LOCATION to
cp_build_modify_expr.
* decl2.c (set_guard): Likewise.
(handle_tls_init): Likewise.
* init.c (perform_member_init): Likewise.
(expand_virtual_init): Likewise.
(build_new_1): Likewise.
(build_vec_delete_1): Likewise.
(get_temp_regvar): Likewise.
(build_vec_init): Likewise.
* method.c (do_build_copy_assign): Likewise.
(assignable_expr): Likewise.
* semantics.c (finish_omp_for): Likewise.
* typeck.c (cp_build_binary_op): Pass LOCATION to pointer_diff and
cp_pointer_int_sum.
(cp_pointer_int_sum): Add location parameter. Pass it down to
pointer_int_sum.
(pointer_diff): Add location parameter. Use it.
(build_modify_expr): Pass location down to cp_build_modify_expr.
(cp_build_modify_expr): Add location parameter. Use it.
(build_x_modify_expr): Pass location down to cp_build_modify_expr.
* typeck2.c (cxx_incomplete_type_diagnostic,
cxx_incomplete_type_error): Add location parameter.
* langhooks-def.h (lhd_incomplete_type_error): Adjust declaration.
* langhooks.c (lhd_incomplete_type_error): Add location parameter.
* langhooks.h (incomplete_type_error): Likewise.
* tree.c (size_in_bytes_loc): Renamed from size_in_bytes. Add location
parameter, pass it down to incomplete_type_error.
* tree.h (size_in_bytes): New inline overload.
(size_in_bytes_loc): Renamed from size_in_bytes.
* c-c++-common/pr70756-2.c: New test.
* c-c++-common/pr70756.c: New test.
rguenth [Thu, 12 May 2016 13:46:26 +0000 (13:46 +0000)]
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71059
* tree-ssa-pre.c (phi_translate_1): Fully fold translated
nary before looking up or entering the expression into the VN
hashes.
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): Fix comment typo.
Make sure to re-use NARYs without result as inserted by
phi-translation.
rguenth [Thu, 12 May 2016 13:05:13 +0000 (13:05 +0000)]
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71062
* tree-ssa-alias.h (struct pt_solution): Add vars_contains_restrict
field.
* tree-ssa-structalias.c (set_uids_in_ptset): Set vars_contains_restrict
if the var is a restrict tag.
* tree-ssa-alias.c (ptrs_compare_unequal): If vars_contains_restrict
do not disambiguate pointers against it.
(dump_points_to_solution): Re-structure and adjust for new
vars_contains_restrict flag.
* gimple-pretty-print.c (pp_points_to_solution): Likewise.
ktkachov [Thu, 12 May 2016 09:56:46 +0000 (09:56 +0000)]
[ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt handlers
PR target/70830
* config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction
when popping the PC and within an interrupt handler routine.
Add missing tab to output of "ldmfd".
(output_return_instruction): Output LDMFD with SP update rather
than POP when returning from interrupt handler.
* gcc.target/arm/interrupt-1.c: Change dg-compile to dg-assemble.
Add -save-temps to dg-options.
Scan for ldmfd rather than pop instruction.
* gcc.target/arm/interrupt-2.c: Likewise.
* gcc.target/arm/pr70830.c: New test.
jakub [Thu, 12 May 2016 08:35:20 +0000 (08:35 +0000)]
* config/i386/i386.md (isa): Add x64_avx512dq, enable if
TARGET_64BIT && TARGET_AVX512DQ.
* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
(*vec_extractv4si_zext): Add avx512dq alternative.
(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
use v instead of x constraint in other alternatives where possible.
* gcc.target/i386/avx512bw-vpextr-1.c: New test.
* gcc.target/i386/avx512dq-vpextr-1.c: New test.
jakub [Thu, 12 May 2016 08:34:11 +0000 (08:34 +0000)]
* config/i386/sse.md (pinsr_evex_isa): New mode attr.
(<sse2p4_1>_pinsr<ssemodesuffix>): Add 2 alternatives with
v constraints instead of x and <pinsr_evex_isa> isa attribute.
* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
* gcc.target/i386/avx512vl-vpinsr-1.c: New test.
jakub [Thu, 12 May 2016 08:33:14 +0000 (08:33 +0000)]
PR target/71019
* config/i386/sse.md (<sse2_avx2>_packssdw<mask_name>,
<sse4_1_avx2>_packusdw<mask_name>): Make sure EVEX encoded insn
is not emitted unless TARGET_AVX512BW.
(<sse2_avx2>_packuswb<mask_name>, <sse2_avx2>_packsswb<mask_name>):
Likewise. For TARGET_AVX512BW, use "=v" constraint instead of "=x"
for the result operand.
* gcc.target/i386/avx512vl-pack-1.c: New test.
* gcc.target/i386/avx512vl-pack-2.c: New test.
* gcc.target/i386/avx512bw-pack-2.c: New test.
jakub [Thu, 12 May 2016 08:30:25 +0000 (08:30 +0000)]
* config/i386/constraints.md (Yv): New constraint.
* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
* config/i386/i386.md (avx512fvecmode): New mode attr.
(*pushtf): Use v constraint instead of x.
(*movtf_internal): Likewise. For TARGET_AVX512VL and
xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
(*absneg<mode>2): Use Yv constraint instead of x constraint.
(*absnegtf2_sse): Likewise.
(copysign<mode>3_const, copysign<mode>3_var): Likewise.
* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
avx512f alternatives.
(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.
* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.
rguenth [Thu, 12 May 2016 07:29:33 +0000 (07:29 +0000)]
2016-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/71060
* tree-data-ref.c (initialize_data_dependence_relation): Do not
require exact match of DR_BASE_OBJECT but only matching address and
type.
meissner [Wed, 11 May 2016 18:38:10 +0000 (18:38 +0000)]
[gcc]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (quad_memory_operand): Move most of
the code into quad_address_p and call it to share code with
vsx_quad_dform_memory_operand.
(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
d-form support.
* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
bit instead of being a separate word. Split -mpower9-dform into
two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
for the register class supporting 128-bit quad word memory
offsets.
(mode_supports_vsx_dform_quad): Helper function to return if the
register class uses quad word memory offsets.
(rs6000_debug_addr_mask): Add support for quad word memory
offsets.
(rs6000_debug_reg_global): Always print if we are using LRA or
not.
(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
instructions are enabled, set up the appropriate addr_masks for
128-bit types.
(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
-mpower9-dform-scalar, instead of -mpower9-dform.
(rs6000_option_override_internal): Split -mpower9-dform into two
switches, -mpower9-dform-scalar and -mpower9-dform-vector. The
-mpower9-dform switch sets or clears both. If we are not using
the LRA register allocator, do not enable -mpower9-dform-vector by
default. If we are using LRA, enable -mpower9-dform-vector and
-mvsx-timode if it is appropriate. Issue a warning if either
-mpower9-dform-vector or -mvsx-timode are explicitly used without
enabling LRA.
(quad_address_offset_p): New helper function to return if the
offset is legal for quad word memory instructions.
(quad_address_p): New function to determin if GPR or vector
register quad word memory addresses are legal.
(mem_operand_gpr): Validate quad word address offsets.
(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
d-form (register + offset) instructions.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Add more debug statements for
-mdebug=addr.
(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
d-form instructions. Distinguish different cases in debug
output. (rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
d-form instructions.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
instructions. If ISA 3.0 is available, generate lxvx/stxvx instead
of the ISA 2.06 indexed memory instructions.
(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
use them to save/restore the saved vector registers instead of
using Altivec instructions.
(rs6000_emit_epilogue): Likewise.
(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
(rs6000_opt_masks): Split -mpower9-dform into
-mpower9-dform-scalar and -mpower9-dform-vector.
(rs6000_print_options_internal): Print -mno-<switch> if <switch>
was not selected.
* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
ISA 3.0 vector indexed memory instructions, and fold the code into
the normal mov<mode> patterns.
(p9_vecstore_<mode>): Likewise.
(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
instructions.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
* config/rs6000/constraints.md (wO constraint): New constraint for
ISA 3.0 vector d-form support.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
-mpower9-dform-scalar instead of -mpower9-dform. Add note not to
include -mpower9-dform-vector until we switch over to LRA.
(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two.
switches, -mpower9-dform-scalar and -mpower9-dform-vector.
* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
for -mpower9-dform and -mlra.
* doc/md.texi (wO constraint): Document wO constraint.
[gcc/testsuite]
2016-05-11 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
support.
* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
warning when using -mvsx-timode.
* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
* gcc.target/powerpc/dform-2.c: Likewise.
* gcc.target/powerpc/pr68805.c: Likewise.
rguenth [Wed, 11 May 2016 14:04:32 +0000 (14:04 +0000)]
2016-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/71055
* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
sth with precision not equal to access size verify we don't chop
off bits.
rguenth [Wed, 11 May 2016 10:24:11 +0000 (10:24 +0000)]
2016-05-11 Richard Biener <rguenther@suse.de>
PR middle-end/71002
* alias.c (reference_alias_ptr_type): Preserve alias-set zero
if the langhook insists on it.
* fold-const.c (make_bit_field_ref): Add arg for the original
reference and preserve its alias-set.
(decode_field_reference): Take exp by reference and adjust it
to the original memory reference.
(optimize_bit_field_compare): Adjust callers.
(fold_truth_andor_1): Likewise.
* gimplify.c (gimplify_expr): Adjust in-SSA form test.
amodra [Wed, 11 May 2016 02:09:38 +0000 (02:09 +0000)]
[RS6000] complex long double ABI_V4 fix
Revision 235794 regressed compat/scalar-by-value-6 for powerpc-linux
-m32 due to accidentally changing the ABI. By another historical
accident, complex long double is stupidly passed in gprs for -m32.
* config/rs6000/rs6000.c (is_complex_IBM_long_double,
abi_v4_pass_in_fpr): New functions.
(rs6000_function_arg_boundary): Exclude complex IBM long double
from 64-bit alignment when ABI_V4.
(rs6000_function_arg, rs6000_function_arg_advance_1,
rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.
segher [Tue, 10 May 2016 23:31:27 +0000 (23:31 +0000)]
cfgcleanup: Handle a branch with just a return in both arms (PR71028)
If we have a conditional jump that has only a return in both the branch
path and the fallthrough path, and the return on the branch path can not
be made a conditional return, we will try to make a conditional return
from the fallthrough path, and that does not work because we then try
to redirect the (new) jump in the fallthrough block to the original
dest in the branch path, which is the exit block.
For the testcase on ARM we end up in this situation because before the
jump2 pass there are some other insns in the return blocks as well, but
the same insns in both, so those are moved above the conditional jump.
Only later (in the ce3 pass) are the conditional jump and two returns
melded into one return, so we need to handle this strange case here.
PR rtl-optimization/71028
* cfgcleanup.c (try_optimize_cfg): Do not flip a conditional
jump with just a return in the fallthrough block if the branch
block contains just a returns as well.
projects / thirdparty / gcc.git / log
