All the DC_FP_START/END should be used before call anything from DML2,
for this reason, the use of those guards inside DML it is not correct.
This commit removes two unnecessary DC_FP_START/END from a dml2
function.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 13 May 2024 23:31:10 +0000 (19:31 -0400)]
drm/amd/display: Use DCN 410 includes for DCN401
DCN401 is using DCN 320 headers, which does not have all the right
registers for DCN401. This commit just replace DCN320 includes with the
one from DCN410.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Most of the DML code is generated, and it is necessary to update some
parts of it from time to time. This commit brings the latest generated
code for DML 2.1.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Fri, 26 Apr 2024 16:17:26 +0000 (12:17 -0400)]
drm/amd/display: Enable ISHARP support for DCN401
[Why]
Enable sharpener support for DCN401
[How]
- Removed memcmp check that was preventing ISHARP from being enabled.
- Add missing ISHARP register defines, masks, and writes.
- Add programming of Blur and Scale coefficients.
- Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel
- format
- Only enable ISHARP for YUV420
- Add disabling of ISHARP
- Add debug flags and registry keys for debugging ISHARP.
- Set default to medium level
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Mon, 27 May 2024 07:40:38 +0000 (15:40 +0800)]
drm/amdgpu: fix typo in amdgpu_ras_aca_sysfs_read() function
fix typo "info.ue_count" in amdgpu_ras_aca_sysfs_read() function.
Fixes: 865d3397630b ("drm/amdgpu: add aca deferred error type support") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Thu, 23 May 2024 09:14:45 +0000 (17:14 +0800)]
drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 May 2024 20:50:39 +0000 (16:50 -0400)]
drm/amdgpu: drop MES 10.1 support v3
It was an enablement vehicle for MES 11 and was never
productized. Remove it.
v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h
Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 15 May 2024 15:25:49 +0000 (11:25 -0400)]
drm/amdgpu: Adjust logic in amdgpu_device_partner_bandwidth()
Use current speed/width on devices which don't support
dynamic PCIe switching.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289 Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Enable colorspace property for MST connectors
MST colorspace property support was disabled due to a series of warnings
that came up when the device was plugged in since the properties weren't
made at device creation. Create the properties in advance instead.
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: 69a959610229 ("drm/amd/display: Temporary Disable MST DP Colorspace Property"). Reported-and-tested-by: Tyler Schneider <tyler.schneider@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/display: Fix null pointer dereference in dc_stream_program_cursor_position
The fix involves adding a null check for 'stream' at the beginning of
the function. If 'stream' is NULL, the function immediately returns
false. This ensures that 'stream' is not NULL when we dereference it to
access 'ctx' in 'dc = stream->ctx->dc;' the function.
Fixes the below:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:398 dc_stream_program_cursor_position()
error: we previously assumed 'stream' could be null (see line 397)
Fixes: f63f86b5affc ("drm/amd/display: Separate setting and programming of cursor") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Pass errors from amdgpu_dm_init() up
Errors in amdgpu_dm_init() are silently ignored and dm_hw_init()
will succeed. However often these are fatal errors and it would
be better to pass them up.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sunil Khatri [Tue, 7 May 2024 05:38:34 +0000 (11:08 +0530)]
drm/amdgpu: rename the ip_dump to ip_dump_core
Rename the memory pointer from ip_dump to ip_dump_core
to make it specific to core registers and rest other
registers to be dumped in their respective memories.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Sat, 11 May 2024 06:39:34 +0000 (14:39 +0800)]
drm/amdgpu - optimize rlc spm cntl
v1
- driver MMIO read the register to check whether write is required
- if write is required, sriov full time to use rlcg, otherwise use KIQ
v2
- include gfx v11 sriov runtime case
Signed-off-by: Jane Jian <Jane.Jian@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Refactor construct_phy function in dc/link/link_factory.c
This commit modifies the construct_phy function to handle the case where
`bios->integrated_info` is NULL and to address a compiler warning about
a large stack allocation.
Upon examination, it was found that the local `integrated_info`
structure was just used to copy values which is large and was being
declared directly on the stack which could potentially lead to
performance issues. This commit changes the code to use
`bios->integrated_info` directly, which avoids the need for a large
stack allocation.
The function now checks if `bios->integrated_info` is NULL before
entering a for loop that uses it. If `bios->integrated_info` is NULL,
the function skips the for loop and continues executing the rest of the
code. This ensures that the function behaves correctly when
`bios->integrated_info` is NULL and improves compatibility with dGPUs.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c: In function ‘construct_phy’:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:743:1: warning: the frame size of 1056 bytes is larger than 1024 bytes [-Wframe-larger-than=]
Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Jerry Zuo <jerry.zuo@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Li Ma [Mon, 20 May 2024 10:43:55 +0000 (18:43 +0800)]
drm/amdgpu/atomfirmware: add intergrated info v2.3 table
[Why]
The vram width value is 0.
Because the integratedsysteminfo table in VBIOS has updated to 2.3.
[How]
Driver needs a new intergrated info v2.3 table too.
Then the vram width value will be correct.
Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix snprintf usage in amdgpu_gfx_kiq_init_ring
This commit fixes a format truncation issue arosed by the snprintf
function potentially writing more characters into the ring->name buffer
than it can hold, in the amdgpu_gfx_kiq_init_ring function
The issue occurred because the '%d' format specifier could write between
1 and 10 bytes into a region of size between 0 and 8, depending on the
values of xcc_id, ring->me, ring->pipe, and ring->queue. The snprintf
function could output between 12 and 41 bytes into a destination of size
16, leading to potential truncation.
To resolve this, the snprintf line was modified to use the '%hhu' format
specifier for xcc_id, ring->me, ring->pipe, and ring->queue. The '%hhu'
specifier is used for unsigned char variables and ensures that these
values are printed as unsigned decimal integers.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_kiq_init_ring’:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:61: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size between 0 and 8 [-Wformat-truncation=]
332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d",
| ^~
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:50: note: directive argument in the range [0, 2147483647]
332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d",
| ^~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:9: note: ‘snprintf’ output between 12 and 41 bytes into a destination of size 16
332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
333 | xcc_id, ring->me, ring->pipe, ring->queue);
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Fixes: 345a36c4f1ba ("drm/amdgpu: prefer snprintf over sprintf") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
'hqd_registers' used to be used in a member of the 'bonaire_mqd'
struct. 'bonaire_mqd' was removed by
commit 486d807cd9a9 ("drm/amdgpu: remove duplicate definition of cik_mqd")
It's now unused.
Remove 'hqd_registers' as well.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Skvortsov [Sun, 19 May 2024 14:39:43 +0000 (10:39 -0400)]
drm/amdgpu: Queue KFD reset workitem in VF FED
The guest recovery sequence is buggy in Fatal Error when both
FLR & KFD reset workitems are queued at the same time. In addition,
FLR guest recovery sequence is out of order when PF/VF communication
breaks due to a GPU fatal error
As a temporary work around, perform a KFD style reset (Initiate reset
request from the guest) inside the pf2vf thread on FED.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Skvortsov [Sun, 19 May 2024 14:34:18 +0000 (10:34 -0400)]
drm/amdgpu: Extend KIQ reg polling wait for VF
Runtime KIQ interface to read/write registers in VF may take longer
than expected for BM environment. Extend the timeout.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 13 May 2024 00:21:53 +0000 (20:21 -0400)]
drm/amd/display: 3.2.286
This version pairs with DMUB FW Release 0.0.218.0 for dcn314/315/316, dcn35/351, dcn401
and brings along the following:
- Fix powerpc compilation
- Fix TBT+TypeC Daisy-chain lightup
- Fix ODM combine setup
- Fix OTC underflow on dcn35
- Fix DVI config for dcn401
- Add ips status info to debugfs
- Add 3DLUT DMA load trigger
- Modify clock programming to support DPM
- Disable dcn401 idle optimizations
Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Tue, 14 May 2024 16:27:08 +0000 (12:27 -0400)]
drm/amd/display: Fix POWERPC_64 compilation
[Why]
Compilation errors while compiling without CONFIG_DRM_AMD_DC_FP:
"undefined reference to `dc_bandwidth_in_kbps_from_timing'"
[How]
Fix Makefile to move dsc files out of DC_FP guard.
Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cruise [Sat, 11 May 2024 06:42:14 +0000 (14:42 +0800)]
drm/amd/display: Not fallback if link BW is smaller than req BW
[Why]
When the link BW is smaller than the request BW,
the DP LT just kept running and fallback to lower link config.
DP LT just aborted if is_hpd_pending bit is high.
But is_hpd_pending bit indicates a new HPD event received.
It doesn't mean the HPD is low.
[How]
Abort the DP LT if the link BW is smaller than the request BW.
Remove checking is_hpd_pending bit in DP LT.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Cruise <cruise.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY&HOW]
At the time of block sequence construction, the exact reference DPP/DISP clock is
not yet known, so the clock should be passed by reference to the DTO programming
function.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 10 May 2024 19:44:57 +0000 (15:44 -0400)]
drm/amd/display: Fix ODM + underscan case with cursor
[Description]
There is a corner case where we're in an ODM config that
has recout.x != 0. In these scenarios we have to take into
account the extra offset in the ODM adjustment for cursor.
Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Fri, 10 May 2024 15:25:55 +0000 (11:25 -0400)]
drm/amd/display: fix a typo which causes an incorrect ODM combine setup
[why]
A recent change for ODM combine refactor contains a typo which causes ODM
combine mode programmed incorrectly.
Reviewed-by: George Shen <george.shen@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Disable idle optimization for each atomic commit is unnecessary,
and can lead to a potential race condition.
[How]
Remove idle optimization check from amdgpu_dm_atomic_commit_tail()
Fixes: 196107eb1e15 ("drm/amd/display: Add IPS checks before dcn register access") Cc: stable@vger.kernel.org Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix pipe addition logic in calc_blocks_to_ungate DCN35
[Why]
Missing check for when there is new pipe configuration but both cur_pipe
and new_pipe are both populated causing update_state of DSC for that
instance not being updated correctly.
This causes some display mode changes to cause underflow since DSCCLK
is still gated when the display requires DSC.
[How]
Added another condition in the new pipe addition branch that checks if
there is a new pipe configuration and if it is not the same as cur_pipe.
cur_pipe does not necessarily have to be NULL to go in this branch.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Tue, 7 May 2024 20:04:50 +0000 (16:04 -0400)]
drm/amd/display: Add ips status info to debugfs
[Why]
For debugging and testing purposes.
[How]
If IPS is supported create ips_status debugfs entry.
Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Mon, 6 May 2024 19:34:55 +0000 (15:34 -0400)]
drm/amd/display: Clear shared dmub firmware state on init
[Why]
Reset the shared dmub firmware region on dmub hw init to start with
known state.
[How]
Memset the shared region to 0 in dmub_hw_init().
Suggested-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Fri, 3 May 2024 23:08:04 +0000 (19:08 -0400)]
drm/amd/display: Add 3DLUT DMA load trigger
[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.
Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DML 2.1 allocates two types of memory in its ctx structure but does not
destroy them, causing memory leak whenever DML 2.1 instance is created
and destroyed.
[How]
Deallocate two instances of allocated memory whenever DML 2.1 is
destroyed.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Mon, 13 May 2024 14:54:54 +0000 (08:54 -0600)]
drm/amd/display: Add missing DML2 var helpers
Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Wed, 24 Apr 2024 12:37:04 +0000 (08:37 -0400)]
drm/amd/display: enable EASF support for DCN40
[Why]
Enable adaptive scaler support for DCN401
[How]
- Enable build flag for SPL
- Set prefer_easf flag to true
- Apply light linear scaling policy based on transfer function and pixel
format. Choose between linear or non-linear scaling
- Set matrix_mode based on pixel format
- Disable ring estimator
- Add missing EASF register defines, masks, and writes
- Disable EASF if scale ratio or number of taps is unsupported and when
bypassing the scaler
- Add debug flags and registry keys for debugging SPL and EASF
- Add support for Visual Confirm with EASF
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chris Park [Tue, 2 Apr 2024 06:06:00 +0000 (02:06 -0400)]
drm/amd/display: Use the correct TMDS function to avoid DVI issues
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The function that commits planes calls the same set of functions twice,
and in the case of the FAMs utilization, it is not desired to call the
dmub, hwss_build and hwss_execute. This commit just removes the
unnecessary calls to those functions.
Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Tue, 11 Apr 2023 00:00:46 +0000 (20:00 -0400)]
drm/amd/display: Move DSC functions from dc.c to dc_dsc.c
Move dsc functions from dc.c to dc_dsc.c.
Co-developed-by: George Shen <george.shen@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Mon, 4 Mar 2024 13:25:27 +0000 (18:55 +0530)]
drm/amd/pm: Remove legacy interface for xgmi plpd
Replace the legacy interface with amdgpu_dpm_set_pm_policy to set XGMI
PLPD mode. Also, xgmi_plpd_policy sysfs node is not used by any client.
Remove that as well.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Wed, 21 Feb 2024 09:24:49 +0000 (14:54 +0530)]
drm/amd/pm: Add support for DPM policies
Add support to set/get information about different DPM policies. The
support is only available on SOCs which use swsmu architecture.
A DPM policy type may be defined with different levels. For example, a
policy may be defined to select Pstate preference and then later a
pstate preference may be chosen.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Mon, 6 May 2024 16:59:57 +0000 (17:59 +0100)]
drm/amdgpu: Describe all object placements in debugfs
Accurately show all placements when describing objects in debugfs, instead
of bunching them up under the 'CPU' placement.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Cc: Christian König <christian.koenig@amd.com> Cc: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Mon, 6 May 2024 16:59:56 +0000 (17:59 +0100)]
drm/amdgpu: Reduce mem_type to domain double indirection
All apart from AMDGPU_GEM_DOMAIN_GTT memory domains map 1:1 to TTM
placements. And the former be either AMDGPU_PL_PREEMPT or TTM_PL_TT,
depending on AMDGPU_GEM_CREATE_PREEMPTIBLE.
Simplify a few places in the code which convert the TTM placement into
a domain by checking against the current placement directly.
In the conversion AMDGPU_PL_PREEMPT either does not have to be handled
because amdgpu_mem_type_to_domain() cannot return that value anyway.
v2:
* Remove AMDGPU_PL_PREEMPT handling.
v3:
* Rebase.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Christian König <christian.koenig@amd.com> # v1 Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> # v2 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tvrtko Ursulin [Mon, 6 May 2024 16:59:55 +0000 (17:59 +0100)]
drm/amdgpu: Add amdgpu_bo_is_vm_bo helper
Help code readability by replacing a bunch of:
bo->tbo.base.resv == vm->root.bo->tbo.base.resv
With:
amdgpu_vm_is_bo_always_valid(vm, bo)
No functional changes.
v2:
* Rename helper and move to amdgpu_vm. (Christian)
v3:
* Use Christian's kerneldoc.
v4:
* Fixed logic inversion in amdgpu_vm_bo_get_memory.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Cc: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Remove duplicate check for *is_queue_unmap in sdma_v7_0_ring_set_wptr
This commit removes a duplicate check for *is_queue_unmap in the
sdma_v7_0_ring_set_wptr function. The check at line 171 was considered
dead code because at this point in the code, we already know that
*is_queue_unmap is false due to the check at line 161.
By removing this unnecessary check, improves the readability of the
code
Fixes the below:
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c:171 sdma_v7_0_ring_set_wptr()
warn: duplicate check '*is_queue_unmap' (previous on line 161)
Tim Van Patten [Thu, 16 May 2024 17:57:25 +0000 (11:57 -0600)]
drm/amdgpu: Remove GC HW IP 9.3.0 from noretry=1
The following commit updated gmc->noretry from 0 to 1 for GC HW IP
9.3.0:
commit 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1")
This causes the device to hang when a page fault occurs, until the
device is rebooted. Instead, revert back to gmc->noretry=0 so the device
is still responsive.
Fixes: 5f3854f1f4e2 ("drm/amdgpu: add more cases to noretry=1") Signed-off-by: Tim Van Patten <timvp@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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