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13 months agoMerge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu...
Richard Henderson [Thu, 25 Apr 2024 15:07:45 +0000 (08:07 -0700)] 
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Implement FEAT_NMI and NMI support in the GICv3
 * hw/dma: avoid apparent overflow in soc_dma_set_request
 * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
 * Add ResetType argument to Resettable hold and exit phase methods
 * Add RESET_TYPE_SNAPSHOT_LOAD ResetType
 * Implement STM32L4x5 USART

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# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits)
  tests/qtest: Add tests for the STM32L4x5 USART
  hw/arm: Add the USART to the stm32l4x5 SoC
  hw/char/stm32l4x5_usart: Add options for serial parameters setting
  hw/char/stm32l4x5_usart: Enable serial read and write
  hw/char: Implement STM32L4x5 USART skeleton
  reset: Add RESET_TYPE_SNAPSHOT_LOAD
  docs/devel/reset: Update to new API for hold and exit phase methods
  hw, target: Add ResetType argument to hold and exit phase methods
  scripts/coccinelle: New script to add ResetType to hold and exit phases
  allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset
  hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr
  linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
  hw/dma: avoid apparent overflow in soc_dma_set_request
  hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI
  target/arm: Add FEAT_NMI to max
  hw/intc/arm_gicv3: Report the VINMI interrupt
  hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()
  hw/intc/arm_gicv3: Implement NMI interrupt priority
  hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
  hw/intc/arm_gicv3: Add NMI handling CPU interface registers
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoMerge tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu into staging
Richard Henderson [Thu, 25 Apr 2024 15:06:33 +0000 (08:06 -0700)] 
Merge tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu into staging

* Update OpenBSD CI image to 7.5
* Update/remove Ubuntu 20.04 CI jobs
* Update (most) CentOS 8 CI jobs to CentOS 9
* Some clean-ups and improvements to travis.yml
* Minor test fixes
* s390x header clean-ups
* Doc updates

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# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]

* tag 'pull-request-2024-04-25' of https://gitlab.com/thuth/qemu:
  target/s390x: Remove KVM stubs in cpu_models.h
  tests/unit: Remove debug statements in test-nested-aio-poll.c
  docs/devel: fix minor typo in submitting-a-patch.rst
  hw/s390x: Include missing 'cpu.h' header
  tests: Update our CI to use CentOS Stream 9 instead of 8
  tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update
  tests/lcitool/libvirt-ci: Update to the latest master branch
  tests: Remove Ubuntu 20.04 container
  .travis.yml: Do some more testing with Clang
  .travis.yml: Update the jobs to Ubuntu 22.04
  .travis.yml: Remove the unused UNRELIABLE environment variable
  Revert ".travis.yml: Cache Avocado cache"
  tests/vm: update openbsd image to 7.5
  docs: i386: pc: Update maximum CPU numbers for PC Q35
  tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`
  MAINTAINERS: update email of Peter Lieven

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/s390x: Remove KVM stubs in cpu_models.h
Philippe Mathieu-Daudé [Fri, 19 Apr 2024 09:06:31 +0000 (11:06 +0200)] 
target/s390x: Remove KVM stubs in cpu_models.h

Since the calls are elided when KVM is not available,
we can remove the stubs (which are never compiled).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240419090631.48055-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/unit: Remove debug statements in test-nested-aio-poll.c
Philippe Mathieu-Daudé [Mon, 22 Apr 2024 11:22:46 +0000 (13:22 +0200)] 
tests/unit: Remove debug statements in test-nested-aio-poll.c

We have been running this test for almost a year; it
is safe to remove its debug statements, which clutter
CI jobs output:

  ▶  88/100 /nested-aio-poll                      OK
  io_read 0x16bb26158
  io_poll_true 0x16bb26158
  > io_poll_ready
  io_read 0x16bb26164
  < io_poll_ready
  io_poll_true 0x16bb26158
  io_poll_false 0x16bb26164
  > io_poll_ready
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_poll_false 0x16bb26164
  io_read 0x16bb26164
  < io_poll_ready
  88/100 qemu:unit / test-nested-aio-poll        OK

Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-ID: <20240422112246.83812-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agodocs/devel: fix minor typo in submitting-a-patch.rst
Manos Pitsidianakis [Mon, 22 Apr 2024 12:41:28 +0000 (15:41 +0300)] 
docs/devel: fix minor typo in submitting-a-patch.rst

s/Resolved:/Resolves:/

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-ID: <20240422124128.4034482-1-manos.pitsidianakis@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agohw/s390x: Include missing 'cpu.h' header
Philippe Mathieu-Daudé [Fri, 22 Mar 2024 16:28:22 +0000 (17:28 +0100)] 
hw/s390x: Include missing 'cpu.h' header

"cpu.h" is implicitly included. Include it explicitly to
avoid the following error when refactoring headers:

  hw/s390x/s390-stattrib.c:86:40: error: use of undeclared identifier 'TARGET_PAGE_SIZE'
      len = sac->peek_stattr(sas, addr / TARGET_PAGE_SIZE, buflen, vals);
                                         ^
  hw/s390x/s390-stattrib.c:94:58: error: use of undeclared identifier 'TARGET_PAGE_MASK'
                     addr / TARGET_PAGE_SIZE, len, addr & ~TARGET_PAGE_MASK);
                                                         ^
  hw/s390x/s390-stattrib.c:224:40: error: use of undeclared identifier 'TARGET_PAGE_BITS'
          qemu_put_be64(f, (start_gfn << TARGET_PAGE_BITS) | STATTR_FLAG_MORE);
                                         ^
  In file included from hw/s390x/s390-virtio-ccw.c:17:
  hw/s390x/s390-virtio-hcall.h:22:27: error: unknown type name 'CPUS390XState'
  int s390_virtio_hypercall(CPUS390XState *env);
                            ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Eric Farman <farman@linux.ibm.com>
Message-ID: <20240322162822.7391-1-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/qtest: Add tests for the STM32L4x5 USART
Arnaud Minier [Fri, 29 Mar 2024 17:44:02 +0000 (18:44 +0100)] 
tests/qtest: Add tests for the STM32L4x5 USART

Test:
- read/write from/to the usart registers
- send/receive a character/string over the serial port

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr
[PMM: fix checkpatch nits, remove commented out code]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/arm: Add the USART to the stm32l4x5 SoC
Arnaud Minier [Fri, 29 Mar 2024 17:44:01 +0000 (18:44 +0100)] 
hw/arm: Add the USART to the stm32l4x5 SoC

Add the USART to the SoC and connect it to the other implemented devices.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr
[PMM: fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/char/stm32l4x5_usart: Add options for serial parameters setting
Arnaud Minier [Fri, 29 Mar 2024 17:44:00 +0000 (18:44 +0100)] 
hw/char/stm32l4x5_usart: Add options for serial parameters setting

Add a function to change the settings of the
serial connection.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/char/stm32l4x5_usart: Enable serial read and write
Arnaud Minier [Fri, 29 Mar 2024 17:43:59 +0000 (18:43 +0100)] 
hw/char/stm32l4x5_usart: Enable serial read and write

Implement the ability to read and write characters to the
usart using the serial port.

The character transmission is based on the
cmsdk-apb-uart implementation.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr
[PMM: fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/char: Implement STM32L4x5 USART skeleton
Arnaud Minier [Fri, 29 Mar 2024 17:43:58 +0000 (18:43 +0100)] 
hw/char: Implement STM32L4x5 USART skeleton

Add the basic infrastructure (register read/write, type...)
to implement the STM32L4x5 USART.

Also create different types for the USART, UART and LPUART
of the STM32L4x5 to deduplicate code and enable the
implementation of different behaviors depending on the type.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr
[PMM: update to new reset hold method signature;
 fixed a few checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agoreset: Add RESET_TYPE_SNAPSHOT_LOAD
Peter Maydell [Fri, 12 Apr 2024 16:08:09 +0000 (17:08 +0100)] 
reset: Add RESET_TYPE_SNAPSHOT_LOAD

Some devices and machines need to handle the reset before a vmsave
snapshot is loaded differently -- the main user is the handling of
RNG seed information, which does not want to put a new RNG seed into
a ROM blob when we are doing a snapshot load.

Currently this kind of reset handling is supported only for:
 * TYPE_MACHINE reset methods, which take a ShutdownCause argument
 * reset functions registered with qemu_register_reset_nosnapshotload

To allow a three-phase-reset device to also distinguish "snapshot
load" reset from the normal kind, add a new ResetType
RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore
the reset type, so we don't need to update any device code.

Add the enum type, and make qemu_devices_reset() use the
right reset type for the ShutdownCause it is passed. This
allows us to get rid of the device_reset_reason global we
were using to implement qemu_register_reset_nosnapshotload().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org

13 months agodocs/devel/reset: Update to new API for hold and exit phase methods
Peter Maydell [Fri, 12 Apr 2024 16:08:08 +0000 (17:08 +0100)] 
docs/devel/reset: Update to new API for hold and exit phase methods

Update the reset documentation's example code to match the new API
for the hold and exit phase method APIs where they take a ResetType
argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-6-peter.maydell@linaro.org

13 months agohw, target: Add ResetType argument to hold and exit phase methods
Peter Maydell [Fri, 12 Apr 2024 16:08:07 +0000 (17:08 +0100)] 
hw, target: Add ResetType argument to hold and exit phase methods

We pass a ResetType argument to the Resettable class enter
phase method, but we don't pass it to hold and exit, even though
the callsites have it readily available. This means that if
a device cared about the ResetType it would need to record it
in the enter phase method to use later on. Pass the type to
all three of the phase methods to avoid having to do that.

Commit created with

  for dir in hw target include; do \
      spatch --macro-file scripts/cocci-macro-file.h \
             --sp-file scripts/coccinelle/reset-type.cocci \
             --keep-comments --smpl-spacing --in-place \
             --include-headers --dir $dir; done

and no manual edits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org

13 months agoscripts/coccinelle: New script to add ResetType to hold and exit phases
Peter Maydell [Fri, 12 Apr 2024 16:08:06 +0000 (17:08 +0100)] 
scripts/coccinelle: New script to add ResetType to hold and exit phases

We pass a ResetType argument to the Resettable class enter phase
method, but we don't pass it to hold and exit, even though the
callsites have it readily available.  This means that if a device
cared about the ResetType it would need to record it in the enter
phase method to use later on.  We should pass the type to all three
of the phase methods to avoid having to do that.

This coccinelle script adds the ResetType argument to the hold and
exit phases of the Resettable interface.

The first part of the script (rules holdfn_assigned, holdfn_defined,
exitfn_assigned, exitfn_defined) update implementations of the
interface within device models, both to change the signature of their
method implementations and to pass on the reset type when they invoke
reset on some other device.

The second part of the script is various special cases:
 * method callsites in resettable_phase_hold(), resettable_phase_exit()
   and device_phases_reset()
 * updating the typedefs for the methods
 * isl_pmbus_vr.c has some code where one device's reset method directly
   calls the implementation of a different device's method

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-4-peter.maydell@linaro.org

13 months agoallwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset
Peter Maydell [Fri, 12 Apr 2024 16:08:05 +0000 (17:08 +0100)] 
allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset

Rather than directly calling the device's implementation of its 'hold'
reset phase, call device_cold_reset(). This means we don't have to
adjust this callsite when we add another argument to the function
signature for the hold and exit reset methods.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-3-peter.maydell@linaro.org

13 months agohw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr
Peter Maydell [Fri, 12 Apr 2024 16:08:04 +0000 (17:08 +0100)] 
hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr

The npcm7xx_clk and npcm7xx_gcr device reset methods look at
the ResetType argument and only handle RESET_TYPE_COLD,
producing a warning if another reset type is passed. This
is different from how every other three-phase-reset method
we have works, and makes it difficult to add new reset types.

A better pattern is "assume that any reset type you don't know
about should be handled like RESET_TYPE_COLD"; switch these
devices to do that. Then adding a new reset type will only
need to touch those devices where its behaviour really needs
to be different from the standard cold reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org

13 months agolinux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
Peter Maydell [Thu, 11 Apr 2024 11:53:13 +0000 (12:53 +0100)] 
linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code

Ever since the bFLT format support was added in 2006, there has been
a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT
which is supposedly for shared library support.  This is not enabled
and it's not possible to enable it, because if you do you'll run into
the "#error needs checking" in the calc_reloc() function.

Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of
an "#error code needs checking" in load_flat_file().

This code is obviously unfinished and has never been used; nobody in
the intervening 18 years has complained about this or fixed it, so
just delete the dead code.  If anybody ever wants the feature they
can always pull it out of git, or (perhaps better) write it from
scratch based on the current Linux bFLT loader rather than the one of
18 years ago.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240411115313.680433-1-peter.maydell@linaro.org

13 months agohw/dma: avoid apparent overflow in soc_dma_set_request
Anastasia Belova [Tue, 9 Apr 2024 11:53:01 +0000 (14:53 +0300)] 
hw/dma: avoid apparent overflow in soc_dma_set_request

In soc_dma_set_request() we try to set a bit in a uint64_t, but we
do it with "1 << ch->num", which can't set any bits past 31;
any use for a channel number of 32 or more would fail due to
integer overflow.

This doesn't happen in practice for our current use of this code,
because the worst case is when we call soc_dma_init() with an
argument of 32 for the number of channels, and QEMU builds with
-fwrapv so the shift into the sign bit is well-defined. However,
it's obviously not the intended behaviour of the code.

Add casts to force the shift to be done as 64-bit arithmetic,
allowing up to 64 channels.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
Message-id: 20240409115301.21829-1-abelova@astralinux.ru
[PMM: Edit commit message to clarify that this doesn't actually
 bite us in our current usage of this code.]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI
Jinjie Ruan [Fri, 19 Apr 2024 13:33:06 +0000 (14:33 +0100)] 
hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI

If the CPU implements FEAT_NMI, then turn on the NMI support in the
GICv3 too.  It's permitted to have a configuration with FEAT_NMI in
the CPU (and thus NMI support in the CPU interfaces too) but no NMI
support in the distributor and redistributor, but this isn't a very
useful setup as it's close to having no NMI support at all.

We don't need to gate the enabling of NMI in the GIC behind a
machine version property, because none of our current CPUs
implement FEAT_NMI, and '-cpu max' is not something we maintain
migration compatibility across versions for. So we can always
enable the GIC NMI support when the CPU has it.

Neither hvf nor KVM support NMI in the GIC yet, so we don't enable
it unless we're using TCG.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com
[PMM: Update comment and commit message]
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Add FEAT_NMI to max
Jinjie Ruan [Fri, 19 Apr 2024 13:33:06 +0000 (14:33 +0100)] 
target/arm: Add FEAT_NMI to max

Enable FEAT_NMI on the 'max' CPU.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Report the VINMI interrupt
Jinjie Ruan [Fri, 19 Apr 2024 13:33:05 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Report the VINMI interrupt

In vCPU Interface, if the vIRQ has the non-maskable property, report
vINMI to the corresponding vPE.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()
Jinjie Ruan [Fri, 19 Apr 2024 13:33:05 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()

In CPU Interface, if the IRQ has the non-maskable property, report NMI to
the corresponding PE.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Implement NMI interrupt priority
Jinjie Ruan [Fri, 19 Apr 2024 13:33:05 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Implement NMI interrupt priority

If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is
higher than 0x80, otherwise it is higher than 0x0. And save the interrupt
non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR
and GICD can deliver NMI, it is both necessary to check whether the pending
irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
Peter Maydell [Fri, 19 Apr 2024 13:36:33 +0000 (14:36 +0100)] 
hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()

Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.

If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
should be set or clear according to the Non-maskable property. And the RPR
priority should also update the NMI bit according to the APR priority NMI bit.

By the way, add gicv3_icv_nmiar1_read trace event.

If the hpp irq is a NMI, the icv iar read should return 1022 and trap for
NMI again

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: use cs->nmi_support instead of cs->gic->nmi_support]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Add NMI handling CPU interface registers
Peter Maydell [Fri, 19 Apr 2024 13:36:00 +0000 (14:36 +0100)] 
hw/intc/arm_gicv3: Add NMI handling CPU interface registers

Add the NMIAR CPU interface registers which deal with acknowledging NMI.

When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid has non-maskable property. And for
ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have
non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1
register.

And the APR and RPR has NMI bits which should be handled correctly.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Separate out whether cpuif supports NMI from whether the
 GIC proper (IRI) supports NMI]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Implement GICD_INMIR
Jinjie Ruan [Fri, 19 Apr 2024 13:33:03 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Implement GICD_INMIR

Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3_redist: Implement GICR_INMIR0
Jinjie Ruan [Fri, 19 Apr 2024 13:33:02 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3_redist: Implement GICR_INMIR0

Add GICR_INMIR0 register and support access GICR_INMIR0.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Add irq non-maskable property
Jinjie Ruan [Fri, 19 Apr 2024 13:33:02 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Add irq non-maskable property

A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
non-maskable property in PendingIrq and GICR/GICD. Since add new device
state, it also needs to be migrated, so also save NMI info in
vmstate_gicv3_cpu and vmstate_gicv3.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3
Jinjie Ruan [Fri, 19 Apr 2024 13:33:01 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3

So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it
an error to try to set has-nmi=true for the KVM GICv3.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Add has-nmi property to GICv3 device
Jinjie Ruan [Fri, 19 Apr 2024 13:33:01 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Add has-nmi property to GICv3 device

Add a property has-nmi to the GICv3 device, and use this to set
the NMI bit in the GICD_TYPER register. This isn't visible to
guests yet because the property defaults to false and we won't
set it in the board code until we've landed all of the changes
needed to implement FEAT_GICV3_NMI.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
Jinjie Ruan [Fri, 19 Apr 2024 13:33:01 +0000 (14:33 +0100)] 
target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()

According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the
GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority)
come from the hcrx_el2.HCRX_VFNMI bit.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU
Jinjie Ruan [Fri, 19 Apr 2024 13:33:00 +0000 (14:33 +0100)] 
hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU

Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it
is not GICv2.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agohw/intc/arm_gicv3: Add external IRQ lines for NMI
Jinjie Ruan [Fri, 19 Apr 2024 13:33:00 +0000 (14:33 +0100)] 
hw/intc/arm_gicv3: Add external IRQ lines for NMI

Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Handle PSTATE.ALLINT on taking an exception
Jinjie Ruan [Fri, 19 Apr 2024 13:32:59 +0000 (14:32 +0100)] 
target/arm: Handle PSTATE.ALLINT on taking an exception

Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
SCTLR_ELx.SPINTMASK bit.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI
Jinjie Ruan [Fri, 19 Apr 2024 13:32:59 +0000 (14:32 +0100)] 
target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI

Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Add support for NMI in arm_phys_excp_target_el()
Jinjie Ruan [Fri, 19 Apr 2024 13:32:58 +0000 (14:32 +0100)] 
target/arm: Add support for NMI in arm_phys_excp_target_el()

According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Add support for Non-maskable Interrupt
Jinjie Ruan [Fri, 19 Apr 2024 13:32:58 +0000 (14:32 +0100)] 
target/arm: Add support for Non-maskable Interrupt

This only implements the external delivery method via the GICv3.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Support MSR access to ALLINT
Jinjie Ruan [Fri, 19 Apr 2024 13:32:57 +0000 (14:32 +0100)] 
target/arm: Support MSR access to ALLINT

Support ALLINT msr access as follow:
mrs <xt>, ALLINT // read allint
msr ALLINT, <xt> // write allint with imm

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Implement ALLINT MSR (immediate)
Jinjie Ruan [Fri, 19 Apr 2024 13:32:57 +0000 (14:32 +0100)] 
target/arm: Implement ALLINT MSR (immediate)

Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
unconditional write to pc and use raise_exception_ra to unwind.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Add support for FEAT_NMI, Non-maskable Interrupt
Jinjie Ruan [Fri, 19 Apr 2024 13:32:57 +0000 (14:32 +0100)] 
target/arm: Add support for FEAT_NMI, Non-maskable Interrupt

Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
ARMv8.8-A and ARM v9.3-A.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Add PSTATE.ALLINT
Jinjie Ruan [Fri, 19 Apr 2024 13:32:56 +0000 (14:32 +0100)] 
target/arm: Add PSTATE.ALLINT

When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked. As Richard suggested, place
ALLINT bit in PSTATE in env->pstate.

In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which
treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to
PSTATE regardless of whether this is an illegal exception return or not. So
handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit
path of the exception_return helper. With the change, exception entry and
return are automatically handled.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotarget/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI
Jinjie Ruan [Fri, 19 Apr 2024 13:32:56 +0000 (14:32 +0100)] 
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI

FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
HCRX_EL2.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13 months agotests: Update our CI to use CentOS Stream 9 instead of 8
Thomas Huth [Thu, 18 Apr 2024 10:10:47 +0000 (12:10 +0200)] 
tests: Update our CI to use CentOS Stream 9 instead of 8

RHEL 9 (and thus also the derivatives) have been available since two
years now, so according to QEMU's support policy, we can drop the active
support for the previous major version 8 now.

Another reason for doing this is that Centos Stream 8 will go EOL soon:

https://blog.centos.org/2023/04/end-dates-are-coming-for-centos-stream-8-and-centos-linux-7/

  "After May 31, 2024, CentOS Stream 8 will be archived
   and no further updates will be provided."

Thus upgrade our CentOS Stream container to major version 9 now.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-5-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/docker/dockerfiles: Run lcitool-refresh after the lcitool update
Thomas Huth [Thu, 18 Apr 2024 10:10:46 +0000 (12:10 +0200)] 
tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update

This update adds the removing of the EXTERNALLY-MANAGED marker files
that has been added to the lcitool recently.

Quoting Daniel:
"For those who don't know, python now commonly blocks the ability to
run 'pip install' outside of a venv. This generally makes sense for
a precious installation environment. Our containers are disposable
though, so a venv has no benefit. Removing the 'EXTERNALLY-MANAGED'
allows the historical arbitrary use of 'pip' outside a venv.
lcitool just does this unconditionally given the containers are
not precious."

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/lcitool/libvirt-ci: Update to the latest master branch
Thomas Huth [Thu, 18 Apr 2024 10:10:45 +0000 (12:10 +0200)] 
tests/lcitool/libvirt-ci: Update to the latest master branch

We need the latest fixes for the lcitool to be able to properly
update our CentOS docker file to CentOS Stream 9.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests: Remove Ubuntu 20.04 container
Thomas Huth [Thu, 18 Apr 2024 10:10:44 +0000 (12:10 +0200)] 
tests: Remove Ubuntu 20.04 container

Since Ubuntu 22.04 has now been available for more than two years, we
can stop actively supporting the previous LTS version of Ubuntu now.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240418101056.302103-2-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months ago.travis.yml: Do some more testing with Clang
Thomas Huth [Wed, 20 Mar 2024 10:41:44 +0000 (11:41 +0100)] 
.travis.yml: Do some more testing with Clang

We are doing a lot of cross-compilation tests with GCC in the gitlab-CI
already, so we could get some more test coverage by using Clang in the
Travis-CI instead. Thus let's switch two additional jobs to use Clang
for compilation.

Message-ID: <20240320104144.823425-7-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months ago.travis.yml: Update the jobs to Ubuntu 22.04
Thomas Huth [Thu, 18 Apr 2024 10:10:48 +0000 (12:10 +0200)] 
.travis.yml: Update the jobs to Ubuntu 22.04

According to our support policy, we'll soon drop our official support
for Ubuntu 20.04 ("Focal Fossa") in QEMU. Thus we should update the
Travis jobs now to a newer release (Ubuntu 22.04 - "Jammy Jellyfish")
for future testing. Since all jobs are using this release now, we
can drop the entries from the individual jobs and use the global
setting again.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-ID: <20240418101056.302103-6-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months ago.travis.yml: Remove the unused UNRELIABLE environment variable
Thomas Huth [Wed, 20 Mar 2024 10:41:43 +0000 (11:41 +0100)] 
.travis.yml: Remove the unused UNRELIABLE environment variable

This variable was used to allow jobs to fail without spoiling the
overall result. But the required "allow_failures:" hunk has been
accidentally removed in commit 9d03f5abed ("travis.yml: Remove the
"Release tarball" job"), and it was anyway only useful while we
still had the x86 jobs here around that were our main CI jobs.
Thus let's simply remove this useless variable now.

Message-ID: <20240320104144.823425-6-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agoRevert ".travis.yml: Cache Avocado cache"
Thomas Huth [Wed, 20 Mar 2024 10:41:41 +0000 (11:41 +0100)] 
Revert ".travis.yml: Cache Avocado cache"

This reverts commit c1073e44b46490133e16420e1784dec7bcd4e030.

The Avocado tests have been removed from Travis a long time ago with
commit c5008c76ee ("gitlab: add acceptance testing to system builds"),
so we don't need to cache the avocado files here anymore.

Message-ID: <20240320104144.823425-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/vm: update openbsd image to 7.5
Brad Smith [Wed, 10 Apr 2024 12:17:26 +0000 (08:17 -0400)] 
tests/vm: update openbsd image to 7.5

tests/vm: update openbsd to release 7.5

Signed-off-by: Brad Smith <brad@comstyle.com>
Message-ID: <ZhaDVpNjq_ZifvPT@humpty.home.comstyle.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agodocs: i386: pc: Update maximum CPU numbers for PC Q35
Zhao Liu [Fri, 12 Apr 2024 08:53:58 +0000 (16:53 +0800)] 
docs: i386: pc: Update maximum CPU numbers for PC Q35

Commit e4e98c7eebfa ("pc: q35: Bump max_cpus to 4096 vcpus") increases
the supported CPUs for PC Q35 machine.

Update maximum CPU numbers for PC Q35 in the document.

Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Message-ID: <20240412085358.731560-1-zhao1.liu@linux.intel.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agotests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`
Inès Varhol [Sun, 14 Apr 2024 17:28:21 +0000 (19:28 +0200)] 
tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`

The messages for assertions using hexadecimal numbers will be
easier to understand with `g_assert_cmphex`.

Cases changed : "cmpuint.*0x", "cmpuint.*<<"

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Ninad Palsule <ninad@linux.ibm.com>
Message-ID: <20240414173349.31194-1-ines.varhol@telecom-paris.fr>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agoMAINTAINERS: update email of Peter Lieven
Peter Lieven [Thu, 5 Jan 2023 09:50:39 +0000 (10:50 +0100)] 
MAINTAINERS: update email of Peter Lieven

I will leave KAMP in the next days. Update email to stay reachable.

Signed-off-by: Peter Lieven <pl@kamp.de>
Message-ID: <20230105095039.182718-1-pl@kamp.de>
Signed-off-by: Thomas Huth <thuth@redhat.com>
13 months agoMerge tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu into staging
Richard Henderson [Wed, 24 Apr 2024 22:51:49 +0000 (15:51 -0700)] 
Merge tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu into staging

meson: Make DEBUG_REMAP a meson option
target/m68k: Support semihosting on non-ColdFire targets
linux-user: do_setsockopt cleanups
linux-user: Add FITRIM ioctl

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* tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu:
  target/m68k: Support semihosting on non-ColdFire targets
  target/m68k: Perform the semihosting test during translate
  target/m68k: Pass semihosting arg to exit
  linux-user: Add FITRIM ioctl
  linux-user: do_setsockopt: eliminate goto in switch for SO_SNDTIMEO
  linux-user: do_setsockopt: make ip_mreq_source local to the place where it is used
  linux-user: do_setsockopt: make ip_mreq local to the place it is used and inline target_to_host_ip_mreq()
  linux-user: do_setsockopt: fix SOL_ALG.ALG_SET_KEY
  meson: Make DEBUG_REMAP a meson option

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/m68k: Support semihosting on non-ColdFire targets
Keith Packard [Tue, 3 Oct 2023 22:26:06 +0000 (15:26 -0700)] 
target/m68k: Support semihosting on non-ColdFire targets

According to the m68k semihosting spec:

"The instruction used to trigger a semihosting request depends on the
 m68k processor variant.  On ColdFire, "halt" is used; on other processors
 (which don't implement "halt"), "bkpt #0" may be used."

Add support for non-CodeFire processors by matching BKPT #0 instructions.

Signed-off-by: Keith Packard <keithp@keithp.com>
[rth: Use semihosting_test()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/m68k: Perform the semihosting test during translate
Richard Henderson [Tue, 3 Oct 2023 22:15:24 +0000 (15:15 -0700)] 
target/m68k: Perform the semihosting test during translate

Replace EXCP_HALT_INSN by EXCP_SEMIHOSTING.  Perform the pre-
and post-insn tests during translate, leaving only the actual
semihosting operation for the exception.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agotarget/m68k: Pass semihosting arg to exit
Keith Packard [Wed, 2 Aug 2023 16:19:12 +0000 (09:19 -0700)] 
target/m68k: Pass semihosting arg to exit

Instead of using d0 (the semihost function number), use d1 (the
provide exit status).

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230802161914.395443-2-keithp@keithp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: Add FITRIM ioctl
Michael Vogt [Wed, 3 Apr 2024 09:20:49 +0000 (11:20 +0200)] 
linux-user: Add FITRIM ioctl

Tiny patch to add the missing FITRIM ioctl.

Signed-off-by: Michael Vogt <mvogt@redhat.com>
Message-Id: <20240403092048.16023-2-michael.vogt@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: do_setsockopt: eliminate goto in switch for SO_SNDTIMEO
Michael Tokarev [Sun, 31 Mar 2024 10:07:37 +0000 (13:07 +0300)] 
linux-user: do_setsockopt: eliminate goto in switch for SO_SNDTIMEO

There's identical code for SO_SNDTIMEO and SO_RCVTIMEO, currently
implemented using an ugly goto into another switch case.  Eliminate
that using arithmetic if, making code flow more natural.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240331100737.2724186-5-mjt@tls.msk.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: do_setsockopt: make ip_mreq_source local to the place where it is used
Michael Tokarev [Sun, 31 Mar 2024 10:07:36 +0000 (13:07 +0300)] 
linux-user: do_setsockopt: make ip_mreq_source local to the place where it is used

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240331100737.2724186-4-mjt@tls.msk.ru>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: do_setsockopt: make ip_mreq local to the place it is used and inline...
Michael Tokarev [Sun, 31 Mar 2024 10:07:35 +0000 (13:07 +0300)] 
linux-user: do_setsockopt: make ip_mreq local to the place it is used and inline target_to_host_ip_mreq()

ip_mreq is declared at the beginning of do_setsockopt(), while
it is used in only one place.  Move its declaration to that very
place and replace pointer to alloca()-allocated memory with the
structure itself.

target_to_host_ip_mreq() is used only once, inline it.

This change also properly handles TARGET_EFAULT when the address
is wrong.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240331100737.2724186-3-mjt@tls.msk.ru>
[rth: Fix braces, adjust optlen to match host structure size]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agolinux-user: do_setsockopt: fix SOL_ALG.ALG_SET_KEY
Michael Tokarev [Sun, 31 Mar 2024 10:07:34 +0000 (13:07 +0300)] 
linux-user: do_setsockopt: fix SOL_ALG.ALG_SET_KEY

This setsockopt accepts zero-lengh optlen (current qemu implementation
does not allow this).  Also, there's no need to make a copy of the key,
it is enough to use lock_user() (which accepts zero length already).

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2197
Fixes: f31dddd2fc "linux-user: Add support for setsockopt() option SOL_ALG"
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20240331100737.2724186-2-mjt@tls.msk.ru>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agomeson: Make DEBUG_REMAP a meson option
Ilya Leoshkevich [Tue, 12 Mar 2024 00:23:30 +0000 (01:23 +0100)] 
meson: Make DEBUG_REMAP a meson option

Currently DEBUG_REMAP is a macro that needs to be manually #defined to
be activated, which makes it hard to have separate build directories
dedicated to testing the code with it. Promote it to a meson option.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20240312002402.14344-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoMerge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging
Richard Henderson [Wed, 24 Apr 2024 18:49:57 +0000 (11:49 -0700)] 
Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging

Removal of deprecated code

- Remove the Nios II target and hardware
- Remove pvrdma device and rdmacm-mux helper
- Remove GlusterFS RDMA protocol handling
- Update Sriram Yagnaraman mail address

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# gpg: Signature made Wed 24 Apr 2024 07:12:22 AM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'housekeeping-20240424' of https://github.com/philmd/qemu:
  block/gluster: Remove deprecated RDMA protocol handling
  hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper
  hw/timer: Remove the ALTERA_TIMER model
  target/nios2: Remove the deprecated Nios II target
  MAINTAINERS: Update Sriram Yagnaraman mail address

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoMerge tag 'pull-qapi-2024-04-24' of https://repo.or.cz/qemu/armbru into staging
Richard Henderson [Wed, 24 Apr 2024 16:23:33 +0000 (09:23 -0700)] 
Merge tag 'pull-qapi-2024-04-24' of https://repo.or.cz/qemu/armbru into staging

QAPI patches patches for 2024-04-24

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# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [undefined]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
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# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* tag 'pull-qapi-2024-04-24' of https://repo.or.cz/qemu/armbru: (25 commits)
  qapi: Dumb down QAPISchema.lookup_entity()
  qapi: Tighten check whether implicit object type already exists
  qapi/schema: remove unnecessary asserts
  qapi/schema: turn on mypy strictness
  qapi/schema: add type hints
  qapi/parser.py: assert member.info is present in connect_member
  qapi/parser: demote QAPIExpression to Dict[str, Any]
  qapi/schema: assert inner type of QAPISchemaVariants in check_clash()
  qapi/schema: fix typing for QAPISchemaVariants.tag_member
  qapi/schema: Don't initialize "members" with `None`
  qapi/schema: add _check_complete flag
  qapi/schema: assert info is present when necessary
  qapi/schema: fix QAPISchemaArrayType.check's call to resolve_type
  qapi: Assert built-in types exist
  qapi/schema: assert resolve_type has 'info' and 'what' args on error
  qapi/schema: add type narrowing to lookup_type()
  qapi/schema: adjust type narrowing for mypy's benefit
  qapi/schema: make c_type() and json_type() abstract methods
  qapi/schema: declare type for QAPISchemaArrayType.element_type
  qapi/schema: declare type for QAPISchemaObjectTypeMember.type
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoMerge tag 'pull-error-2024-04-24' of https://repo.or.cz/qemu/armbru into staging
Richard Henderson [Wed, 24 Apr 2024 16:22:42 +0000 (09:22 -0700)] 
Merge tag 'pull-error-2024-04-24' of https://repo.or.cz/qemu/armbru into staging

Error reporting patches for 2024-04-24

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# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [undefined]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'pull-error-2024-04-24' of https://repo.or.cz/qemu/armbru:
  qapi: Inline and remove QERR_PROPERTY_VALUE_BAD definition
  qapi: Inline and remove QERR_MIGRATION_ACTIVE definition
  qapi: Correct error message for 'vcpu_dirty_limit' parameter
  qapi: Inline and remove QERR_INVALID_PARAMETER_TYPE definition
  qapi: Inline QERR_INVALID_PARAMETER_TYPE definition (constant value)
  qapi: Inline and remove QERR_INVALID_PARAMETER definition
  qapi: Inline and remove QERR_DEVICE_NO_HOTPLUG definition
  qapi: Inline and remove QERR_DEVICE_HAS_NO_MEDIUM definition
  qapi: Inline and remove QERR_BUS_NO_HOTPLUG definition
  error: Drop superfluous #include "qapi/qmp/qerror.h"

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13 months agoblock/gluster: Remove deprecated RDMA protocol handling
Philippe Mathieu-Daudé [Thu, 28 Mar 2024 12:41:10 +0000 (13:41 +0100)] 
block/gluster: Remove deprecated RDMA protocol handling

GlusterFS+RDMA has been deprecated 8 years ago in commit
0552ff2465 ("block/gluster: deprecate rdma support"):

  gluster volfile server fetch happens through unix and/or tcp,
  it doesn't support volfile fetch over rdma. The rdma code may
  actually mislead, so to make sure things do not break, for now
  we fallback to tcp when requested for rdma, with a warning.

  If you are wondering how this worked all these days, its the
  gluster libgfapi code which handles anything other than unix
  transport as socket/tcp, sad but true.

Besides, the whole RDMA subsystem was deprecated in commit
e9a54265f5 ("hw/rdma: Deprecate the pvrdma device and the rdma
subsystem") released in v8.2.

Cc: Prasanna Kumar Kalever <prasanna.kalever@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20240328130255.52257-4-philmd@linaro.org>

13 months agohw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper
Philippe Mathieu-Daudé [Thu, 28 Mar 2024 11:53:00 +0000 (12:53 +0100)] 
hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper

The whole RDMA subsystem was deprecated in commit e9a54265f5
("hw/rdma: Deprecate the pvrdma device and the rdma subsystem")
released in v8.2.

Remove:
 - PVRDMA device
 - generated vmw_pvrdma/ directory from linux-headers
 - rdmacm-mux tool from contrib/

Cc: Yuval Shaia <yuval.shaia.ml@gmail.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20240328130255.52257-2-philmd@linaro.org>

13 months agohw/timer: Remove the ALTERA_TIMER model
Philippe Mathieu-Daudé [Wed, 27 Mar 2024 14:22:20 +0000 (15:22 +0100)] 
hw/timer: Remove the ALTERA_TIMER model

The ALTERA_TIMER was only used by Nios II machines,
which have been removed. Since it has no direct user,
remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240327144806.11319-4-philmd@linaro.org>

13 months agotarget/nios2: Remove the deprecated Nios II target
Philippe Mathieu-Daudé [Wed, 27 Mar 2024 11:10:58 +0000 (12:10 +0100)] 
target/nios2: Remove the deprecated Nios II target

The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").

Remove:
- Buildsys / CI infra
- User emulation
- System emulation (10m50-ghrd & nios2-generic-nommu machines)
- Tests

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Message-Id: <20240327144806.11319-3-philmd@linaro.org>

13 months agoMAINTAINERS: Update Sriram Yagnaraman mail address
Sriram Yagnaraman [Wed, 28 Feb 2024 08:06:25 +0000 (09:06 +0100)] 
MAINTAINERS: Update Sriram Yagnaraman mail address

Due to company policies, I have changed my mail address. Updating
MAINTAINERS and .mailmap to show my latest mail address.

Signed-off-by: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
Message-ID: <20240228080625.2412372-1-sriram.yagnaraman@ericsson.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13 months agoqapi: Dumb down QAPISchema.lookup_entity()
Markus Armbruster [Fri, 15 Mar 2024 15:23:01 +0000 (16:23 +0100)] 
qapi: Dumb down QAPISchema.lookup_entity()

QAPISchema.lookup_entity() takes an optional type argument, a subtype
of QAPISchemaDefinition, and returns that type or None.  Callers can
use this to save themselves an isinstance() test.

The only remaining user of this convenience feature is .lookup_type().
But we don't actually save anything anymore there: we still need the
isinstance() to help mypy over the hump.

Drop the .lookup_entity() argument, and adjust .lookup_type().

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-26-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
[Commit message typo fixed]

13 months agoqapi: Tighten check whether implicit object type already exists
Markus Armbruster [Fri, 15 Mar 2024 15:23:00 +0000 (16:23 +0100)] 
qapi: Tighten check whether implicit object type already exists

Entities with names starting with q_obj_ are implicit object types.
Therefore, QAPISchema._make_implicit_object_type()'s .lookup_entity()
can only return a QAPISchemaObjectType.  Assert that.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-25-armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: John Snow <jsnow@redhat.com>
13 months agoqapi/schema: remove unnecessary asserts
John Snow [Fri, 15 Mar 2024 15:22:59 +0000 (16:22 +0100)] 
qapi/schema: remove unnecessary asserts

With strict typing enabled, these runtime statements aren't necessary
anymore; we can prove them statically.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-24-armbru@redhat.com>

13 months agoqapi/schema: turn on mypy strictness
John Snow [Fri, 15 Mar 2024 15:22:58 +0000 (16:22 +0100)] 
qapi/schema: turn on mypy strictness

This patch can be rolled in with the previous one once the series is
ready for merge, but for work-in-progress' sake, it's separate here.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-23-armbru@redhat.com>

13 months agoqapi/schema: add type hints
John Snow [Fri, 15 Mar 2024 15:22:57 +0000 (16:22 +0100)] 
qapi/schema: add type hints

This patch only adds type hints, which aren't utilized at runtime and
don't change the behavior of this module in any way.

In a scant few locations, type hints are removed where no longer
necessary due to inference power from typing all of the rest of
creation; and any type hints that no longer need string quotes are
changed.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-22-armbru@redhat.com>

13 months agoqapi/parser.py: assert member.info is present in connect_member
John Snow [Fri, 15 Mar 2024 15:22:56 +0000 (16:22 +0100)] 
qapi/parser.py: assert member.info is present in connect_member

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-21-armbru@redhat.com>

13 months agoqapi/parser: demote QAPIExpression to Dict[str, Any]
John Snow [Fri, 15 Mar 2024 15:22:55 +0000 (16:22 +0100)] 
qapi/parser: demote QAPIExpression to Dict[str, Any]

Dict[str, object] is a stricter type, but with the way that code is
currently arranged, it is infeasible to enforce this strictness.

In particular, although expr.py's entire raison d'être is normalization
and type-checking of QAPI Expressions, that type information is not
"remembered" in any meaningful way by mypy because each individual
expression is not downcast to a specific expression type that holds all
the details of each expression's unique form.

As a result, all of the code in schema.py that deals with actually
creating type-safe specialized structures has no guarantee (myopically)
that the data it is being passed is correct.

There are two ways to solve this:

(1) Re-assert that the incoming data is in the shape we expect it to be, or
(2) Disable type checking for this data.

(1) is appealing to my sense of strictness, but I gotta concede that it
is asinine to re-check the shape of a QAPIExpression in schema.py when
expr.py has just completed that work at length. The duplication of code
and the nightmare thought of needing to update both locations if and
when we change the shape of these structures makes me extremely
reluctant to go down this route.

(2) allows us the chance to miss updating types in the case that types
are updated in expr.py, but it *is* an awful lot simpler and,
importantly, gets us closer to type checking schema.py *at
all*. Something is better than nothing, I'd argue.

So, do the simpler dumber thing and worry about future strictness
improvements later.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-20-armbru@redhat.com>

13 months agoqapi/schema: assert inner type of QAPISchemaVariants in check_clash()
John Snow [Fri, 15 Mar 2024 15:22:54 +0000 (16:22 +0100)] 
qapi/schema: assert inner type of QAPISchemaVariants in check_clash()

QAPISchemaVariant's "variants" field is typed as
List[QAPISchemaVariant], where the typing for QAPISchemaVariant allows
its type field to be any QAPISchemaType.

However, QAPISchemaVariant expects that all of its variants contain the
narrower QAPISchemaObjectType. This relationship is enforced at runtime
in QAPISchemaVariants.check(). This relationship is not embedded in the
type system though, so QAPISchemaVariants.check_clash() needs to
re-assert this property in order to call
QAPISchemaVariant.type.check_clash().

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-19-armbru@redhat.com>

13 months agoqapi/schema: fix typing for QAPISchemaVariants.tag_member
John Snow [Fri, 15 Mar 2024 15:22:53 +0000 (16:22 +0100)] 
qapi/schema: fix typing for QAPISchemaVariants.tag_member

There are two related changes here:

(1) We need to perform type narrowing for resolving the type of
    tag_member during check(), and

(2) tag_member is a delayed initialization field, but we can hide it
    behind a property that raises an Exception if it's called too
    early. This simplifies the typing in quite a few places and avoids
    needing to assert that the "tag_member is not None" at a dozen
    callsites, which can be confusing and suggest the wrong thing to a
    drive-by contributor.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-18-armbru@redhat.com>

13 months agoqapi/schema: Don't initialize "members" with `None`
John Snow [Fri, 15 Mar 2024 15:22:52 +0000 (16:22 +0100)] 
qapi/schema: Don't initialize "members" with `None`

Declare, but don't initialize the "members" field with type
List[QAPISchemaObjectTypeMember].

This simplifies the typing from what would otherwise be
Optional[List[T]] to merely List[T]. This removes the need to add
assertions to several callsites that this value is not None - which it
never will be after the delayed initialization in check() anyway.

The type declaration without initialization trick will cause accidental
uses of this field prior to full initialization to raise an
AttributeError.

(Note that it is valid to have an empty members list, see the internal
q_empty object as an example. For this reason, we cannot use the empty
list as a replacement test for full initialization and instead rely on
the _checked/_check_complete fields.)

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-17-armbru@redhat.com>

13 months agoqapi/schema: add _check_complete flag
John Snow [Fri, 15 Mar 2024 15:22:51 +0000 (16:22 +0100)] 
qapi/schema: add _check_complete flag

Instead of using the None value for the members field, use a dedicated
flag to detect recursive misconfigurations.

This is intended to assist with subsequent patches that seek to remove
the "None" value from the members field (which can never hold that value
after the final call to check()) in order to simplify the static typing
of that field; avoiding the need of assertions littered at many
callsites to eliminate the possibility of the None value.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-16-armbru@redhat.com>

13 months agoqapi/schema: assert info is present when necessary
John Snow [Fri, 15 Mar 2024 15:22:50 +0000 (16:22 +0100)] 
qapi/schema: assert info is present when necessary

QAPISchemaInfo arguments can often be None because built-in definitions
don't have such information.  The type hint can only be
Optional[QAPISchemaInfo] then.  But, mypy gets upset about all the
places where we exploit that it can't actually be None there.  Add
assertions that will help mypy over the hump, to enable adding type
hints in a forthcoming commit.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-15-armbru@redhat.com>

13 months agoqapi/schema: fix QAPISchemaArrayType.check's call to resolve_type
John Snow [Fri, 15 Mar 2024 15:22:49 +0000 (16:22 +0100)] 
qapi/schema: fix QAPISchemaArrayType.check's call to resolve_type

Adjust the expression at the callsite to work around mypy's weak type
introspection that believes this expression can resolve to
QAPISourceInfo; it cannot.

(Fundamentally: self.info only resolves to false in a boolean expression
when it is None; therefore this expression may only ever produce
Optional[str]. mypy does not know that 'info', when it is a
QAPISourceInfo object, cannot ever be false.)

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-14-armbru@redhat.com>

13 months agoqapi: Assert built-in types exist
Markus Armbruster [Fri, 15 Mar 2024 15:22:48 +0000 (16:22 +0100)] 
qapi: Assert built-in types exist

QAPISchema.lookup_type('FOO') returns a QAPISchemaType when type 'FOO'
exists, else None.  It won't return None for built-in types like
'int'.

Since mypy can't see that, it'll complain that we assign the
Optional[QAPISchemaType] returned by .lookup_type() to QAPISchemaType
variables.

Add assertions to help it over the hump.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-13-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
13 months agoqapi/schema: assert resolve_type has 'info' and 'what' args on error
John Snow [Fri, 15 Mar 2024 15:22:47 +0000 (16:22 +0100)] 
qapi/schema: assert resolve_type has 'info' and 'what' args on error

resolve_type() is generally used to resolve configuration-provided type
names into type objects, and generally requires valid 'info' and 'what'
parameters.

In some cases, such as with QAPISchemaArrayType.check(), resolve_type
may be used to resolve built-in types and as such will not have an
'info' argument, but also must not fail in this scenario.

Use an assertion to sate mypy that we will indeed have 'info' and 'what'
parameters for the error pathway in resolve_type.

Note: there are only three callsites to resolve_type at present where
"info" is perceived by mypy to be possibly None:

    1) QAPISchemaArrayType.check()
    2) QAPISchemaObjectTypeMember.check()
    3) QAPISchemaEvent.check()

    Of those three, only the first actually ever passes None; the other two
    are limited by their base class initializers which accept info=None, but
    neither subclass actually use a None value in practice, currently.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-12-armbru@redhat.com>

13 months agoqapi/schema: add type narrowing to lookup_type()
John Snow [Fri, 15 Mar 2024 15:22:46 +0000 (16:22 +0100)] 
qapi/schema: add type narrowing to lookup_type()

This function is a bit hard to type as-is; mypy needs some assertions to
assist with the type narrowing.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-11-armbru@redhat.com>

13 months agoqapi/schema: adjust type narrowing for mypy's benefit
John Snow [Fri, 15 Mar 2024 15:22:45 +0000 (16:22 +0100)] 
qapi/schema: adjust type narrowing for mypy's benefit

We already take care to perform some type narrowing for arg_type and
ret_type, but not in a way where mypy can utilize the result once we add
type hints, e.g.:

qapi/schema.py:833: error: Incompatible types in assignment (expression
has type "QAPISchemaType", variable has type
"Optional[QAPISchemaObjectType]") [assignment]

qapi/schema.py:893: error: Incompatible types in assignment (expression
has type "QAPISchemaType", variable has type
"Optional[QAPISchemaObjectType]") [assignment]

A simple change to use a temporary variable helps the medicine go down.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-10-armbru@redhat.com>

13 months agoqapi/schema: make c_type() and json_type() abstract methods
John Snow [Fri, 15 Mar 2024 15:22:44 +0000 (16:22 +0100)] 
qapi/schema: make c_type() and json_type() abstract methods

These methods should always return a str, it's only the default abstract
implementation that doesn't. They can be marked "abstract", which
requires subclasses to override the method with the proper return type.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-9-armbru@redhat.com>

13 months agoqapi/schema: declare type for QAPISchemaArrayType.element_type
John Snow [Fri, 15 Mar 2024 15:22:43 +0000 (16:22 +0100)] 
qapi/schema: declare type for QAPISchemaArrayType.element_type

A QAPISchemaArrayType's element type gets resolved only during .check().
We have QAPISchemaArrayType.__init__() initialize self.element_type =
None, and .check() assign the actual type.  Using .element_type before
.check() is wrong, and hopefully crashes due to the value being None.
Works.

However, it makes for awkward typing.  With .element_type:
Optional[QAPISchemaType], mypy is of course unable to see that it's None
before .check(), and a QAPISchemaType after.  To help it over the hump,
we'd have to assert self.element_type is not None before all the (valid)
uses.  The assertion catches invalid uses, but only at run time; mypy
can't flag them.

Instead, declare .element_type in .__init__() as QAPISchemaType
*without* initializing it.  Using .element_type before .check() now
certainly crashes, which is an improvement.  Mypy still can't flag
invalid uses, but that's okay.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-8-armbru@redhat.com>

13 months agoqapi/schema: declare type for QAPISchemaObjectTypeMember.type
John Snow [Fri, 15 Mar 2024 15:22:42 +0000 (16:22 +0100)] 
qapi/schema: declare type for QAPISchemaObjectTypeMember.type

A QAPISchemaObjectTypeMember's type gets resolved only during .check().
We have QAPISchemaObjectTypeMember.__init__() initialize self.type =
None, and .check() assign the actual type.  Using .type before .check()
is wrong, and hopefully crashes due to the value being None.  Works.

However, it makes for awkward typing.  With .type:
Optional[QAPISchemaType], mypy is of course unable to see that it's None
before .check(), and a QAPISchemaType after.  To help it over the hump,
we'd have to assert self.type is not None before all the (valid) uses.
The assertion catches invalid uses, but only at run time; mypy can't
flag them.

Instead, declare .type in .__init__() as QAPISchemaType *without*
initializing it.  Using .type before .check() now certainly crashes,
which is an improvement.  Mypy still can't flag invalid uses, but that's
okay.

Addresses typing errors such as these:

qapi/schema.py:657: error: "None" has no attribute "alternate_qtype"  [attr-defined]
qapi/schema.py:662: error: "None" has no attribute "describe"  [attr-defined]

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-7-armbru@redhat.com>

13 months agoqapi: create QAPISchemaDefinition
John Snow [Fri, 15 Mar 2024 15:22:41 +0000 (16:22 +0100)] 
qapi: create QAPISchemaDefinition

Include entities don't have names, but we generally expect "entities" to
have names. Reclassify all entities with names as *definitions*, leaving
the nameless include entities as QAPISchemaEntity instances.

This is primarily to help simplify typing around expectations of what
callers expect for properties of an "entity".

Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-6-armbru@redhat.com>

13 months agoqapi/schema: add pylint suppressions
John Snow [Fri, 15 Mar 2024 15:22:40 +0000 (16:22 +0100)] 
qapi/schema: add pylint suppressions

With this patch, pylint is happy with the file, so enable it in the
configuration.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-5-armbru@redhat.com>

13 months agoqapi: sort pylint suppressions
John Snow [Fri, 15 Mar 2024 15:22:39 +0000 (16:22 +0100)] 
qapi: sort pylint suppressions

Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-4-armbru@redhat.com>

13 months agoqapi/parser: shush up pylint
John Snow [Fri, 15 Mar 2024 15:22:38 +0000 (16:22 +0100)] 
qapi/parser: shush up pylint

Shhh!

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-3-armbru@redhat.com>

13 months agoqapi/parser: fix typo - self.returns.info => self.errors.info
John Snow [Fri, 15 Mar 2024 15:22:37 +0000 (16:22 +0100)] 
qapi/parser: fix typo - self.returns.info => self.errors.info

Small copy-pasto. The correct info field to use in this conditional
block is self.errors.info.

Fixes: 3a025d3d1ffa
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240315152301.3621858-2-armbru@redhat.com>

13 months agoqapi: Inline and remove QERR_PROPERTY_VALUE_BAD definition
Philippe Mathieu-Daudé [Tue, 12 Mar 2024 14:13:43 +0000 (15:13 +0100)] 
qapi: Inline and remove QERR_PROPERTY_VALUE_BAD definition

Address the comment added in commit 4629ed1e98
("qerror: Finally unused, clean up"), from 2015:

  /*
   * These macros will go away, please don't use
   * in new code, and do not add new ones!
   */

Manual change. Remove the definition in
include/qapi/qmp/qerror.h.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240312141343.3168265-11-armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
13 months agoqapi: Inline and remove QERR_MIGRATION_ACTIVE definition
Philippe Mathieu-Daudé [Tue, 12 Mar 2024 14:13:42 +0000 (15:13 +0100)] 
qapi: Inline and remove QERR_MIGRATION_ACTIVE definition

Address the comment added in commit 4629ed1e98
("qerror: Finally unused, clean up"), from 2015:

  /*
   * These macros will go away, please don't use
   * in new code, and do not add new ones!
   */

Mechanical transformation using sed, manually
removing the definition in include/qapi/qmp/qerror.h.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-ID: <20240312141343.3168265-10-armbru@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
[Straightforward conflict with commit aeaafb1e59f (migration: export
migration_is_running) resolved]