re PR target/68163 (GCC on power8 does not issue the stxsspx instruction on power8)
[gcc]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
are now unused after splitting mov{sf,sd}_hardfloat.
(f32_lr2): Likewise.
(f32_lm): Likewise.
(f32_lm2): Likewise.
(f32_li): Likewise.
(f32_li2): Likewise.
(f32_lv): Likewise.
(f32_sr): Likewise.
(f32_sr2): Likewise.
(f32_sm): Likewise.
(f32_sm2): Likewise.
(f32_si): Likewise.
(f32_si2): Likewise.
(f32_sv): Likewise.
(f32_dm): Likewise.
(f32_vsx): Likewise.
(f32_av): Likewise.
(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
For movsf, order stores so the VSX stores occur before the GPR
store which encourages the register allocator to use a traditional
FPR instead of a GPR. For movsd, order the stores so that the GPR
store comes before the VSX stores to allow the power6 to work.
This is due to the power6 not having a 32-bit integer store
instruction from a FPR.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
[gcc/testsuite]
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* gcc.target/powerpc/pr68163.c: New test.
Janus Weil [Tue, 9 May 2017 20:55:38 +0000 (22:55 +0200)]
re PR fortran/79311 ([OOP] ICE in generate_finalization_wrapper, at fortran/class.c:1992)
2017-05-09 Janus Weil <janus@gcc.gnu.org>
PR fortran/79311
* resolve.c (gfc_resolve_finalizers): Ensure that derived-type
components have a their finalizers resolved, also if the superordinate
type itself has a finalizer.
2017-05-09 Janus Weil <janus@gcc.gnu.org>
PR fortran/79311
* gfortran.dg/finalize_32.f90: New test.
Martin Sebor [Tue, 9 May 2017 15:39:54 +0000 (15:39 +0000)]
re PR translation/80280 (Missing closing quote (%>) c/semantics.c and c/c-typeck.c)
gcc/ChangeLog:
PR translation/80280
* config/i386/msformat-c.c (ms_printf_flag_specs): Initialize new
data member added in r247778.
(ms_scanf_flag_specs, ms_strftime_flag_specs): Same.
When a processor enters a fast interrupts handler, and duplicate
register banks are configured, the processor saves the user context by
saving the registers in the main register bank to these additional
registers in the duplicate register bank. In this fast interrupt
context, when you specify the rgf_banked_regs option,the compiler does
not save the registers duplicated in the additional register bank are
not saved.
gcc/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* config/arc/arc.c (ARC_AUTOBLINK_IRQ_P): Consider fast interrupts
case also.
(ARC_AUTOFP_IRQ_P): Likewise.
(ARC_AUTO_IRQ_P): Likewise.
(rgf_banked_register_count): New variable.
(parse_mrgf_banked_regs_option): New function.
(arc_override_options): Handle rgf_banked_regs option.
(arc_handle_interrupt_attribute): Add firq option.
(arc_compute_function_type): Return fast irq type when required.
(arc_must_save_register): Handle fast interrupts.
(arc_expand_prologue): Do not emit dwarf info for fast interrupts.
(arc_return_address_regs): Update.
* config/arc/arc.h (arc_return_address_regs): Update.
(arc_function_type): Add fast interrupt type.
(ARC_INTERRUPT_P): Update.
(RC_FAST_INTERRUPT_P): Define.
* config/arc/arc.md (simple_return): Update for fast interrupts.
(p_return_i): Likewise.
* config/arc/arc.opt (mrgf-banked-regs): New option.
* doc/invoke.texi (mrgf-banked-regs): Document.
testsuite/
2017-05-09 Claudiu Zissulescu <claziss@synopsys.com>
Andrew Burgess <andrew.burgess@embecosm.com>
[ARC] Automatic context save/restore for regular interrupts.
The AUX_IRQ_CTRL register controls the behavior of automated register
save and restore or prologue and epilogue sequences during a non-fast
interrupt entry and exit, and context save and restore instructions.
A user passes to the compiler the configuration of the AUX_IRQ_CTRL
register via mirq-ctrl-saved option. This option, specifies
gneral-purposes registers that the processor saves/restores on
interrupt entry and exit, and it is only valid for ARC EM and ARC HS
cores.
The test reports bogus failures because the loop variable i is declared
as int, and the constant expected in the dump doesn't fit in an int for avr.
Fixed by explicitly using __INT32_TYPE__ for targets with __SIZEOF_INT__ < 4.
Richard Biener [Tue, 9 May 2017 08:14:44 +0000 (08:14 +0000)]
tree-vrp.c (get_single_symbol): Add assert that we don't get overflowed constants as invariant part.
2017-05-09 Richard Biener <rguenther@suse.de>
* tree-vrp.c (get_single_symbol): Add assert that we don't
get overflowed constants as invariant part.
(compare_values_warnv): Add comment before the TREE_NO_WARNING
checks. Use wi::cmp instead of recursing for integer constants.
(compare_values): Just ignore whether we assumed undefined
overflow instead of failing the compare.
(extract_range_for_var_from_comparison_expr): Add comment before the
TREE_NO_WARNING sets.
(test_for_singularity): Likewise.
(extract_range_from_comparison): Do not disable optimization
when we assumed undefined overflow.
(extract_range_basic): Remove init of unused var.
Richard Biener [Tue, 9 May 2017 07:57:04 +0000 (07:57 +0000)]
tree-vrp.c (vrp_int_const_binop): Use wide-ints and simplify.
2017-05-09 Richard Biener <rguenther@suse.de>
* tree-vrp.c (vrp_int_const_binop): Use wide-ints and simplify.
(extract_range_from_multiplicative_op_1): Adjust.
(extract_range_from_binary_expr_1): Use int_const_binop.
Kelvin Nilsen [Tue, 9 May 2017 01:15:46 +0000 (01:15 +0000)]
re PR target/80101 (ICE in store_data_bypass_p, at recog.c:3737)
gcc/testsuite/ChangeLog:
2017-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/80101
* gcc.target/powerpc/pr80101-1.c: New test.
gcc/ChangeLog:
2017-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org>
PR target/80101
* config/rs6000/power6.md: Replace store_data_bypass_p calls with
rs6000_store_data_bypass_p in seven define_bypass directives and
in several comments.
* config/rs6000/rs6000-protos.h: Add prototype for
rs6000_store_data_bypass_p function.
* config/rs6000/rs6000.c (rs6000_store_data_bypass_p): New
function implements slightly different (rs6000-specific) semantics
than store_data_bypass_p, returning false rather than aborting
with assertion error when arguments do not satisfy the
requirements of store data bypass.
(rs6000_adjust_cost): Replace six calls of store_data_bypass_p with
rs6000_store_data_bypass_p.
Max Filippov [Mon, 8 May 2017 23:53:14 +0000 (23:53 +0000)]
xtensa: add support for SSP
gcc/
2017-05-08 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-protos.h
(xtensa_initial_elimination_offset): New declaration.
* config/xtensa/xtensa.c (xtensa_initial_elimination_offset):
New function. Move its body from the INITIAL_ELIMINATION_OFFSET
macro definition, add case for FRAME_POINTER_REGNUM when
FRAME_GROWS_DOWNWARD.
* config/xtensa/xtensa.h (FRAME_GROWS_DOWNWARD): New macro
definition.
(INITIAL_ELIMINATION_OFFSET): Replace body with call to
xtensa_initial_elimination_offset.
Thomas Koenig [Mon, 8 May 2017 18:22:44 +0000 (18:22 +0000)]
re PR fortran/79930 (Potentially Missed Optimisation for MATMUL / DOT_PRODUCT)
2017-05-08 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/79930
* frontend-passes.c (matmul_to_var_expr): New function,
add prototype.
(matmul_to_var_code): Likewise.
(optimize_namespace): Use them from gfc_code_walker.
2017-05-08 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/79930
* gfortran.dg/inline_transpose_1.f90: Add
-finline-matmul-limit=0 to options.
* gfortran.dg/matmul_5.f90: Likewise.
* gfortran.dg/vect/vect-8.f90: Likewise.
* gfortran.dg/inline_matmul_14.f90: New test.
* gfortran.dg/inline_matmul_15.f90: New test.
Nathan Sidwell [Mon, 8 May 2017 17:59:03 +0000 (17:59 +0000)]
decl.c (builtin_function_1): Set DCL_ANTICIPATED before pushing.
* decl.c (builtin_function_1): Set DCL_ANTICIPATED before pushing.
(start_preparsed_function): Do decl pushing before setting
current_funciton_decl and announcing it.
[AArch64] Tighten move constraints for symbolic operands
The movsi and movdi constraints allowed the source to be any
absolute symbolic expression ("S"). That's OK for operands that
have already been vetted by the aarch64_mov_operand predicate but
causes problems if the register allocator substitutes an equivalence
(the usual "the constraints can't accept more than the predicates"
restriction).
Although all other uses of "S" in the backend are redundant and could
in principle be removed, "S" itself is a publicly-documented constraint
and so we'd have to keep its definition. This patch therefore adds a
new "Usa" constraint for legitimate absolute address operands.
2017-05-08 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/constraints.md (Usa): New constraint.
* config/aarch64/aarch64.md (*movsi_aarch64, *movdi_aarch64): Use it.
TM_MULTILIB_CONFIG is not set in config.gcc when building with multilib
for arm targets, leading to config/arm/t-multilib not including any of
the files (t-aprofile and t-rmprofile) definining the architecture and
FPU to build multilib for. This patch fixes that by setting
TM_MULTILIB_CONFIG to with_multilib_list's value after it has been
checked. It also fix a trailing whitespace issue.
2017-05-08 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config.gcc (arm*-*-*): Set TM_MULTILIB_CONFIG from
with_multilib_list after it has been checked.
Richard Biener [Mon, 8 May 2017 12:52:44 +0000 (12:52 +0000)]
tree-vrp.c (gimple_assign_nonzero_warnv_p): Rename to ...
2017-05-08 Richard Biener <rguenther@suse.de>
* tree-vrp.c (gimple_assign_nonzero_warnv_p): Rename to ...
(gimple_assign_nonzero): ... this and remove strict_overflow_p
argument.
(gimple_stmt_nonzero_warnv_p): Rename to ...
(gimple_stmt_nonzero_p): ... this and remove strict_overflow_p
argument.
(vrp_stmt_computes_nonzero): Remove strict_overflow_p argument.
(extract_range_basic): Adjust, do not disable propagation on
strict overflow sensitive simplification.
(vrp_visit_cond_stmt): Likewise.
Jeff Law [Sun, 7 May 2017 15:10:55 +0000 (09:10 -0600)]
revert: re PR tree-optimization/78496 (Missed opportunities for jump threading)
2017-05-07 Jeff Law <law@redhat.com>
Revert:
2017-05-06 Jeff Law <law@redhat.com>
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): Remove debugging
code.
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): New function.
(simplify_stmt_using_ranges): Call it.
(vrp_dom_walker::before_dom_children): Extract equivalences
from an ASSERT_EXPR with an equality comparison against a
constant.
Revert:
2017-05-06 Jeff Law <law@redhat.com>
PR tree-optimization/78496
* gcc.dg/tree-ssa/ssa-thread-16.c: New test.
* gcc.dg/tree-ssa/ssa-thread-17.c: New test.
Jeff Law [Sat, 6 May 2017 15:03:40 +0000 (09:03 -0600)]
re PR tree-optimization/78496 (Missed opportunities for jump threading)
PR tree-optimization/78496
* tree-vrp.c (simplify_assert_expr_using_ranges): New function.
(simplify_stmt_using_ranges): Call it.
(vrp_dom_walker::before_dom_children): Extract equivalences
from an ASSERT_EXPR with an equality comparison against a
constant.
PR tree-optimization/78496
* gcc.dg/tree-ssa/ssa-thread-16.c: New test.
* gcc.dg/tree-ssa/ssa-thread-17.c: New test.
If we decide to allocate a call-clobbered register R to a value that
is live across a call, LRA will create a new spill register TMPR,
insert:
TMPR <- R
before the call and
R <- TMPR
after it. But if we then failed to allocate a register to TMPR, we would
always spill it to the stack, even if R was known to be equivalent to
a constant or to some existing memory location. And on AArch64, we'd
always fail to allocate such a register for 128-bit Advanced SIMD modes,
since no registers of those modes are call-preserved.
This patch avoids the problem by copying the equivalence information
from the original pseudo to the spill register. It means that the
code for the testcase is as good with -O2 as it is with -O,
whereas previously the -O code was better.
[Based on the code ARM contributed in branches/ARM/sve-branch@247248]
2017-05-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* lra-constraints.c (lra_copy_reg_equiv): New function.
(split_reg): Use it to copy equivalence information from the
original register to the spill register.
gcc/testsuite/
* gcc.target/aarch64/spill_1.c: New test.
Uros Bizjak [Sat, 6 May 2017 07:01:51 +0000 (09:01 +0200)]
i386.c (ext_80387_constant_init): Do not explicitly initialize to zero.
* config/i386/i386.c (ext_80387_constant_init): Do not explicitly
initialize to zero.
(init_regs): Remove declaration.
(function_arg_advance_32): Initialize error_p as boolean variable.
David Malcolm [Fri, 5 May 2017 21:03:07 +0000 (21:03 +0000)]
Get rid of macros for diagnostic_report_current_module
diagnostic.h has a couple of macros (diagnostic_last_module_changed
and diagnostic_set_last_module) which are only used within
diagnostic_report_current_module.
This patch eliminates the macros in favor of static functions within
diagnostic.c.
No functional change intended.
gcc/ChangeLog:
* diagnostic.c (last_module_changed_p): New function.
(set_last_module): New function.
(diagnostic_report_current_module): Convert macro usage to
the above functions.
* diagnostic.h (diagnostic_context::last_module): Strengthen
from const line_map * to const line_map_ordinary *.
(diagnostic_last_module_changed): Delete macro.
(diagnostic_set_last_module): Delete macro.
David Malcolm [Fri, 5 May 2017 20:56:36 +0000 (20:56 +0000)]
diagnostic.c: add print_option_information
This patch simplifies diagnostic_report_diagnostic by moving
option-printing to a new subroutine.
Doing so required a slight rewrite. In both the old and new
code, context->option_name returns a malloc-ed string.
The old behavior was to then use ACONCAT to manipulate the
format_spec, appending the option metadata.
ACONCAT calcs the buffer size, then uses alloca, and then copies the
data to the on-stack buffer.
Given the alloca, this needs rewriting when moving the printing to
a subroutine. In the new version, the metadata is simply printed
using pp_* calls (so it's hitting the obstack within the
pretty_printer).
This means we can get rid of the save/restore of format_spec: I don't
believe anything else in the code modifies it.
It also seems inherently simpler; it seems odd to me to be
appending metadata to the formatting string, rather than simply
printing the metadata after the formatted string is printed
(the old code also assumed that no option name contained a '%').
No functional change intended.
gcc/ChangeLog:
* diagnostic.c (diagnostic_report_diagnostic): Eliminate
save/restor of format_spec. Move option-printing code to...
(print_option_information): ...this new function, and
reimplement by simply printing to the pretty_printer,
rather than appending to the format string.
Andrew Waterman [Fri, 5 May 2017 20:24:46 +0000 (20:24 +0000)]
RISC-V: Add -mstrict-align option
The RISC-V user ISA permits misaligned accesses, but they may trap
and be emulated. That emulation software needs to be compiled assuming
strict alignment.
Even when strict alignment is not required, set SLOW_UNALIGNED_ACCESS
based upon -mtune to avoid a performance pitfall.
gcc/ChangeLog:
2017-05-04 Andrew Waterman <andrew@sifive.com>
* config/riscv/riscv.opt (mstrict-align): New option.
* config/riscv/riscv.h (STRICT_ALIGNMENT): Use it. Update comment.
(SLOW_UNALIGNED_ACCESS): Define.
(riscv_slow_unaligned_access): Declare.
* config/riscv/riscv.c (riscv_tune_info): Add slow_unaligned_access
field.
(riscv_slow_unaligned_access): New variable.
(rocket_tune_info): Set slow_unaligned_access to true.
(optimize_size_tune_info): Set slow_unaligned_access to false.
(riscv_cpu_info_table): Add entry for optimize_size_tune_info.
(riscv_valid_lo_sum_p): Use TARGET_STRICT_ALIGN.
(riscv_option_override): Set riscv_slow_unaligned_access.
* doc/invoke.texi: Add -mstrict-align to RISC-V.
re PR target/79038 (Improve PowerPC ISA 3.0 conversion between integers and hardware _Float128)
[gcc]
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79038
PR target/79202
PR target/79203
* config/rs6000/rs6000.md (u code attribute): Add FIX and
UNSIGNED_FIX.
(extendsi<mode>2): Add support for doing sign extension via
VUPKHSW and XXPERMDI if the value is in Altivec registers and we
don't have ISA 3.0 instructions.
(extendsi<mode>2 splitter): Likewise.
(fix_trunc<mode>si2): If we are at ISA 2.07 (VSX small integer),
generate the normal insns since SImode can now go in vector
registers. Disallow the special UNSPECs needed for previous
machines to hide SImode being used. Add new insns
fctiw{,w}_<mode>_smallint if SImode can go in vector registers.
(fix_trunc<mode>si2_stfiwx): Likewise.
(fix_trunc<mode>si2_internal): Likewise.
(fixuns_trunc<mode>si2): Likewise.
(fixuns_trunc<mode>si2_stfiwx): Likewise.
(fctiw<u>z_<mode>_smallint): Likewise.
(fctiw<u>z_<mode>_mem): New combiner pattern to prevent conversion
of floating point to 32-bit integer from doing a direct move to
the GPR registers to do a store.
(fctiwz_<mode>): Break long line.
[gcc/testsuite]
2017-05-05 Michael Meissner <meissner@linux.vnet.ibm.com>
Steve Ellcey [Fri, 5 May 2017 17:00:46 +0000 (17:00 +0000)]
invoke.texi (-fopt-info): Explicitly say order of options included in -fopt-info does not matter.
2017-05-05 Steve Ellcey <sellcey@cavium.com>
* doc/invoke.texi (-fopt-info): Explicitly say order of options
included in -fopt-info does not matter.
* doc/optinfo.texi (-fopt-info): Fix description of default
behavour. Explicitly say order of options included in -fopt-info
does not matter.