Bin Meng [Fri, 1 May 2020 13:23:02 +0000 (21:23 +0800)]
roms/opensbi: Upgrade from v0.7 to v0.8
Upgrade OpenSBI from v0.7 to v0.8.
The v0.8 release includes the following commits:
1bb00ab lib: No need to provide default PMP region using platform callbacks a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback 6585fab lib: utils: Add SiFive test device 4781545 platform: Add Nuclei UX600 platform 3a326af scripts: adapt binary archive script for Nuclei UX600 5bdf022 firmware: fw_base: Remove CSR_MTVEC update check e6c1345 lib: utils/serial: Skip baudrate config if input frequency is zero 01a8c8e lib: utils: Improve fdt_parse_uart8250() API 0a0093b lib: utils: Add fdt_parse_uart8250_node() function 243b0d0 lib: utils: Remove redundant clint_ipi_sync() declaration e3ad7c1 lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr() a39cd6f lib: utils: Add FDT match table based node lookup dd33b9e lib: utils: Make fdt_get_node_addr_size() public function 66185b3 lib: utils: Add fdt_parse_sifive_uart_node() function 19e966b lib: utils: Add fdt_parse_hart_id() function 44dd7be lib: utils: Add fdt_parse_max_hart_id() API f0eb503 lib: utils: Add fdt_parse_plic_node() function 1ac794c include: Add array_size() macro 8ff2b94 lib: utils: Add simple FDT timer framework 76f0f81 lib: utils: Add simple FDT ipi framework 75322a6 lib: utils: Add simple FDT irqchip framework 76a8940 lib: utils: Add simple FDT serial framework 7cc6fa4 lib: utils: Add simple FDT reset framework 4d06353 firmware: fw_base: Introduce optional fw_platform_init() f1aa9e5 platform: Add generic FDT based platform support 1f21b99 lib: sbi: Print platform hart count at boot time 2ba7087 scripts: Add generic platform to create-binary-archive.sh 4f18c6e platform: generic: Add Sifive FU540 TLB flush range limit override 13717a8 platform: Remove qemu/virt directory 65c06b0 platform: Remove spike directory d626037 docs: Add missing links in platform.md 7993ca2 include: sbi: Remove redundant page table related defines 5338679 lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation dc38929 lib: sbi: Improve misa_string() implementation 433bac7 docs: platform/generic: Add details about stdout-path DT property b4efa70 docs: platform/generic: Add details about IPI and timer expectations dfd9dd6 docs: Add platform requirements document c2286b6 docs: Fix ordering of pages in table of contents 7be75f5 docs: Don't use italic text in page title 63a513e lib: Rename unprivileged trap handler aef9a60 lib: Add csr detect support 13ca20d lib: Create a separate math helper function file 79d0fad lib: utils: Update reserved memory fdt node even if PMP is not present 6a053f6 lib: Add support for hart specific features b2df751 platform: Move platform features to hart 4938024 platform: fpga: Remove redundant platform specific features ec0d2a7 lib: timer: Provide a hart based timer feature 1f235ec lib: Add platform features in boot time print 22c4334 lib: Add hart features in boot time print 36833ab lib: Optimize inline assembly for unprivilege access functions 38a4b54 firmware: Correct spelling mistakes 28b4052 lib: sbi: detect features before everything else in sbi_hart_init() 4984183 lib: sbi: Improve get_feature_str() implementation and usage 3aa1036 lib: sbi: Remove extra spaces from boot time prints 3a8fc81 lib: sbi: Print platform HART count just before boot HART id 63b0f5f include: sbi: Use scratch pointer as parmeter in HART feature APIs 2966510 lib: sbi: Few cosmetic improvements to HART feature detection a38bea9 lib: sbi_hart: Detect number of supported PMP regions 89ba634 include: sbi: Add firmware extension constants 73d6ef3 lib: utils: Remove redundant parameters from PLIC init functions 446a9c6 lib: utils: Allow PLIC functions to be used for multiple PLICs 2c685c2 lib: utils: Extend fdt_find_match() Implementation d30bb68 lib: utils/irqchip: Initialize all matching irqchip DT nodes a9a9751 lib: utils: Allow CLINT functions to be used for multiple CLINTs 569dd64 lib: utils: Add fdt_parse_clint_node() function 6956e83 lib: utils/ipi: Initialize all matching ipi DT nodes a63f05f lib: utils/timer: Initialize all matching timer DT nodes 30b6040 Makefile: Fix builtin DTB compilation for out-of-tree platforms 64f1408 firmware: fw_base: Make builtin DTB available to fw_platform_init() 4ce6b7a firmware: fw_base: Don't OR forced FW_OPTIONS 86ec534 firmware: Allow fw_platform_init() to return updated FDT location c6c65ee Makefile: Preprocess builtin DTS 4e3876d Makefile: Add mechanism for platforms to have multiple builtin DTBs 72019ee platform: kendryte/k210: Use new mechanism of builtin DTB 51f0e4a firmware: Remove FW_PAYLOAD_FDT and related documentation 1b8c012 lib: Add RISC-V hypervisor v0.6.1 support 79bfd67 docs: Use doxygen config to mark the main page 106b888 docs: Remove redundant documentation about combined payload use case 9802906 platform: Add AE350 platform specific SBI handler 32f87e5 platform: Add AE350 cache control SBIs e2c3f01 lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va() 6966ad0 platform/lib: Allow the OS to map the regions that are protected by PMP 518e85c platform: Update Nuclei ux600 platform support d5725c2 lib: Don't print delegation CSRs if there is no S-Mode 637b348 lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check db56ef3 platform: Add support for Shakti C-class SoC from IIT-M 9bd5f8f lib: sbi: Fix 32/64 bits variable compatibility 2314101 lib: Don't return any invalid error from SBI ecall a98258d include: Bump-up version to 0.8
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Mon, 22 Jun 2020 05:09:32 +0000 (13:09 +0800)]
configure: Create symbolic links for pc-bios/*.elf files
Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Hou Weiying [Sat, 8 Aug 2020 08:56:40 +0000 (16:56 +0800)]
riscv: Fix bug in setting pmpcfg CSR for RISCV64
First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.
If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.
We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <SG2PR02MB263420036254AC8841F66CE393460@SG2PR02MB2634.apcprd02.prod.outlook.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Bin Meng [Mon, 20 Jul 2020 06:49:08 +0000 (23:49 -0700)]
hw/riscv: sifive_u: Add a dummy L2 cache controller device
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Fri, 24 Jul 2020 00:28:07 +0000 (17:28 -0700)]
target/riscv: check before allocating TCG temps
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Fri, 24 Jul 2020 00:28:06 +0000 (17:28 -0700)]
target/riscv: Clean up fmv.w.x
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan. The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-6-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Generate nanboxed results from trans_rvf.inc.c
Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv: Generate nanboxed results from fp helpers
Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Peter Maydell [Fri, 21 Aug 2020 13:51:43 +0000 (14:51 +0100)]
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-20200812' into staging
Acceptance tests patches
- Use stable URLs for the Debian and Ubuntu installer
(Ubuntu has been updated last Wednesday, August 5, 2020).
CI jobs results:
. https://cirrus-ci.com/build/6385815351721984
. https://gitlab.com/philmd/qemu/-/pipelines/177054604
# gpg: Signature made Wed 12 Aug 2020 14:17:09 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/acceptance-testing-20200812:
acceptance: use stable URLs for the Debian and Ubuntu installer
tests/acceptance/boot_linux: Extract common URL from xlnx-versal test
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Meson warns if xgettext is not found. In the future we may want to add
a required argument to i18n.gettext(); in the meanwhile, I am adding a
--enable-gettext/--disable-gettext option and feature detection in
configure. This preserves QEMU's default behavior of detecting system
features, without any warning, if neither --enable-* nor --disable-*
is requested.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 5 Aug 2020 13:49:10 +0000 (15:49 +0200)]
meson: sphinx-build
For now, sphinx is run on every invocation of make. The previous mechanism
using $(wildcard) is not reproducible in Meson and was also brittle; for
example some .rst.inc files were left out. The next patch will introduce
a Sphinx extension to emit a depfile.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The most interesting or most complicated part here is the syscall_nr.h
generators. In order to keep the generation logic all in meson.build,
I am adding to config_target the name of the .tbl file, and making the
generated file syscall<SUFFIX>_nr.h for input file syscall<SUFFIX>.tbl.
For architectures where the input file is not named syscall_nr.tbl,
syscall_nr.h has to be a source file; it's just a forwarder for x86
(i386/x86_64), while for MIPS64 it chooses between N32 and N64 ABIs.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 7 Aug 2020 10:10:23 +0000 (12:10 +0200)]
meson: target
Similar to hw_arch, each architecture defines two sourceset which are placed in
dictionaries target_arch and target_softmmu_arch. These are then picked up
from there when building the per-emulator static_library.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
projects / thirdparty / qemu.git / log
