Eric Botcazou [Fri, 24 May 2013 08:52:35 +0000 (08:52 +0000)]
ada-tree.h (LOOP_STMT_NO_UNROLL): New define.
* gcc-interface/ada-tree.h (LOOP_STMT_NO_UNROLL): New define.
(LOOP_STMT_UNROLL): Likewise.
(LOOP_STMT_NO_VECTOR): Likewise.
(LOOP_STMT_VECTOR): Likewise.
* gcc-interface/trans.c (struct loop_info_d): Replace label field
with stmt field.
(Pragma_to_gnu) <Pragma_Loop_Optimize>: New case.
(Loop_Statement_to_gnu): Save the loop statement onto the stack
instead of the label.
(gnat_to_gnu) <N_Exit_Statement>: Retrieve the loop label.
Eric Botcazou [Fri, 24 May 2013 08:27:55 +0000 (08:27 +0000)]
decl.c (gnat_to_gnu_entity): Constify a handful of local variables.
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Record_Type>: Constify
a handful of local variables.
For a derived untagged type that renames discriminants, change the type
of the stored discriminants to a subtype with the bounds of the type
of the visible discriminants.
(build_subst_list): Rename local variable.
Eric Botcazou [Fri, 24 May 2013 06:46:11 +0000 (06:46 +0000)]
re PR tree-optimization/55177 (missed optimizations with __builtin_bswap)
PR rtl-optimization/55177
* simplify-rtx.c (simplify_unary_operation_1) <NOT>: Deal with BSWAP.
(simplify_byte_swapping_operation): New.
(simplify_binary_operation_1): Call it for AND, IOR and XOR.
(simplify_relational_operation_1): Deal with BSWAP.
Vidya Praveen [Thu, 23 May 2013 13:36:41 +0000 (14:36 +0100)]
[AArch64] Support for CLZ
2013-05-23 Vidya Praveen <vidyapraveen@arm.com>
* config/aarch64/aarch64-simd.md (clzv4si2): Support for CLZ
instruction (AdvSIMD).
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handler for BUILT_IN_CLZ.
* config/aarch64/aarch-simd-builtins.def: Entry for CLZ.
Martin Jambor [Thu, 23 May 2013 13:20:41 +0000 (15:20 +0200)]
re PR middle-end/57347 (wrong code for bitfield on x86_64-linux at -Os and above)
2013-05-22 Martin Jambor <mjambor@suse.cz>
PR middle-end/57347
* tree.h (contains_bitfld_component_ref_p): Declare.
* tree-sra.c (contains_bitfld_comp_ref_p): Move...
* tree.c (contains_bitfld_component_ref_p): ...here. Adjust its caller.
* ipa-prop.c (determine_known_aggregate_parts): Check that LHS does
not access a bit-field. Assert all final offsets are byte-aligned.
Richard Biener [Thu, 23 May 2013 12:23:59 +0000 (12:23 +0000)]
re PR tree-optimization/57380 (GCC 4.9.0 will not vectorize std::max and similar functions)
2013-05-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/57380
* tree-ssa-phiprop.c (propagate_with_phi): Do not require at
least one invariant or re-used load.
* passes.c (init_optimization_passes): Move pass_phiprop before
pass_forwprop.
Jakub Jelinek [Thu, 23 May 2013 09:17:34 +0000 (11:17 +0200)]
re PR rtl-optimization/57344 (wrong code with pragma pack(1) and -O1 on x86)
PR middle-end/57344
* expmed.c (store_split_bit_field): If op0 is a REG or
SUBREG of a REG, don't lower unit. Handle unit not being
always BITS_PER_WORD.
* gcc.c-torture/execute/pr57344-1.c: New test.
* gcc.c-torture/execute/pr57344-2.c: New test.
* gcc.c-torture/execute/pr57344-3.c: New test.
* gcc.c-torture/execute/pr57344-4.c: New test.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__CRYPTO__ if the crypto instructions are available.
(altivec_overloaded_builtins): Add support for overloaded power8
builtins.
* config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add
support for power8 crypto builtins.
(builtin_function_type): Likewise.
(altivec_init_builtins): Add support for builtins that take vector
long long (V2DI) arguments.
* config/rs6000/crypto.md: New file, define power8 crypto
instructions.
2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use
constraints.md instead of rs6000.h. Reorder w* constraints. Add
wm, wn, wr documentation.
* gcc/config/rs6000/constraints.md (wm): New constraint for VSX
registers if direct move instructions are enabled.
(wn): New constraint for no registers.
(wq): New constraint for quad word even GPR registers.
(wr): New constraint if 64-bit instructions are enabled.
(wv): New constraint if power8 vector instructions are enabled.
(wQ): New constraint for quad word memory locations.
* gcc/config/rs6000/predicates.md (const_0_to_15_operand): New
constraint for 0..15 for crypto instructions.
(gpc_reg_operand): If VSX allow registers in VSX registers as well
as GPR and floating point registers.
(int_reg_operand): New predicate to match only GPR registers.
(base_reg_operand): New predicate to match base registers.
(quad_int_reg_operand): New predicate to match even GPR registers
for quad memory operations.
(vsx_reg_or_cint_operand): New predicate to allow vector logical
operations in both GPR and VSX registers.
(quad_memory_operand): New predicate for quad memory operations.
(reg_or_indexed_operand): New predicate for direct move support.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):
Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS.
(ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8).
(POWERPC_MASKS): Add power8 options.
(power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the
various options.
* gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8.
* gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for
power8.
(rs6000_hard_regno_mode_ok): Make PTImode only match even GPR
registers.
(rs6000_debug_reg_print): Print the base register class if
-mdebug=reg.
(rs6000_debug_vector_unit): Add p8_vector.
(rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint
definitions. Also print fusion state.
(rs6000_init_hard_regno_mode_ok): Set up power8 constraints.
(rs6000_builtin_mask_calculate): Add power8 builtin support.
(rs6000_option_override_internal): Add support for power8.
(rs6000_common_init_builtins): Add debugging for skipped builtins
if -mdebug=builtin.
(rs6000_adjust_cost): Add power8 support.
(rs6000_issue_rate): Likewise.
(insn_must_be_first_in_group): Likewise.
(insn_must_be_last_in_group): Likewise.
(force_new_group): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a
power8 capable assembler, default to power7 options.
(TARGET_DIRECT_MOVE): Likewise.
(TARGET_CRYPTO): Likewise.
(TARGET_P8_VECTOR): Likewise.
(VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support.
(VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise.
(VECTOR_MEM_P8_VECTOR_P): Likewise.
(VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise.
(VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise.
(TARGET_XSCVDPSPN): Likewise.
(TARGET_XSCVSPDPN): Likewsie.
(TARGET_SYNC_HI_QI): Likewise.
(TARGET_SYNC_TI): Likewise.
(MASK_CRYPTO): Likewise.
(MASK_DIRECT_MOVE): Likewise.
(MASK_P8_FUSION): Likewise.
(MASK_P8_VECTOR): Likewise.
(REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the
TFmode temporary used by some of the direct move instructions to
get two FP temporary registers does not force creation of a stack
frame.
(VLOGICAL_REGNO_P): Allow vector logical operations in GPRs.
(MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so
that any VSX registers are tieable, even if they are also an
Altivec vector mode.
(r6000_reg_class_enum): Add wm, wr, wv constraints.
(RS6000_BTM_P8_VECTOR): Power8 builtin support.
(RS6000_BTM_CRYPTO): Likewise.
(RS6000_BTM_COMMON): Likewise.
PR target/19599
PR target/57340
* config/arm/arm.c (any_sibcall_uses_r3): Rename to ..
(any_sibcall_could_use_r3): this and handle indirect calls.
(arm_get_frame_offsets): Rename use of any_sibcall_uses_r3.
Tobias Burnus [Wed, 22 May 2013 11:13:17 +0000 (13:13 +0200)]
re PR fortran/57338 (ICE with assumed rank)
2013-05-22 Tobias Burnus <burnus@net-b.de>
PR fortran/57338
* intrinsic.c (do_check): Move some checks to ...
(do_ts29113_check): ... this new function.
(check_specific, gfc_intrinsic_sub_interface): Call it.
Eric Botcazou [Wed, 22 May 2013 10:39:03 +0000 (10:39 +0000)]
sol2-unwind.h (sparc64_frob_update_context): Do it for signal frames as well.
* config/sparc/sol2-unwind.h (sparc64_frob_update_context): Do it for
signal frames as well.
(MD_FALLBACK_FRAME_STATE_FOR): Do minor cleanups throughout and add the
STACK_BIAS to the CFA offset.
Jonathan Wakely [Wed, 22 May 2013 08:12:45 +0000 (08:12 +0000)]
acinclude.m4 (GLIBCXX_ENABLE_LIBSTDCXX_TIME): Add KIND=auto to enable features if target OS is known to support them.
* acinclude.m4 (GLIBCXX_ENABLE_LIBSTDCXX_TIME): Add KIND=auto to
enable features if target OS is known to support them.
* configure.ac (GLIBCXX_ENABLE_LIBSTDCXX_TIME): Default to 'auto'.
* configure: Regenerate.
Jakub Jelinek [Tue, 21 May 2013 15:17:31 +0000 (17:17 +0200)]
re PR tree-optimization/57331 (ICE: tree check: expected integer_type or enumeral_type or boolean_type or real_type or fixed_point_type, have pointer_type in int_fits_type_p, at tree.c:8437)
PR tree-optimization/57331
* tree-vrp.c (simplify_cond_using_ranges): Don't optimize
comparison of conversion from pointer type to integral type
with integer.
Jonathan Wakely [Tue, 21 May 2013 08:15:13 +0000 (08:15 +0000)]
re PR libstdc++/57336 (Cannot INVOKE a reference_wrapper around an abstract type)
PR libstdc++/57336
* include/std/functional (__invoke): Do not form function types with
abstract return type.
* testsuite/20_util/reference_wrapper/invoke-3.cc: New.
Christian Bruel [Tue, 21 May 2013 07:48:08 +0000 (09:48 +0200)]
dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for spanning registers.
2013-05-21 Christian Bruel <christian.bruel@st.com>
* dwarf2out.c (multiple_reg_loc_descriptor): Use dbx_reg_number for
spanning registers. LEAF_REG_REMAP is supported only for contiguous
registers. Set register size out of the PARALLEL loop.
Tobias Burnus [Mon, 20 May 2013 20:05:40 +0000 (22:05 +0200)]
re PR fortran/48858 (Incorrect error for same binding label on two generic interface specifics)
2013-05-20 Tobias Burnus <burnus@net-b.de>
PR fortran/48858
* decl.c (add_global_entry): Use nonbinding name
only for F2003 or if no binding label exists.
(gfc_match_entry): Update calls.
* parse.c (gfc_global_used): Improve error message.
(add_global_procedure): Use nonbinding name
only for F2003 or if no binding label exists.
(gfc_parse_file): Update call.
* resolve.c (resolve_global_procedure): Use binding
name when available.
* trans-decl.c (gfc_get_extern_function_decl): Ditto.
gcc/
* config/mips/mips.h (BASE_INSN_LENGTH, NOP_INSN_LENGTH): New macros.
* config/mips/mips.c (mips_symbol_insns, mips_address_insns)
(mips_const_insns, mips_split_const_insns, mips_load_store_insns)
(mips_idiv_insns): Update the comments to say that the returned
instruction counts are in units of BASE_INSN_LENGTH.
(mips_adjust_insn_length): Multiply the mips_load_label_num_insns
by BASE_INSN_LENGTH rather than 4. Add the jump separately,
using 2 rather than 4 as the length of indirect MIPS16 and
microMIPS jumps. Use NOP_INSN_LENGTH rather than 4 as the
length of a NOP. Don't divide MIPS16 lengths by 2.
(mips16_split_long_branches): Assume a branch is long if the
length is greater than 4 rather than 8.
* config/mips/mips.md (length): Give MIPS16 lengths directly,
rather than multiplying them by 2. Multiply instruction counts
by BASE_INSN_LENGTH rather than 4.
(*jump_mips16, tls_get_tp_mips16_<mode>)
(*tls_get_tp_mips16_call_<mode>): Divide lengths by 2.
Easwaran Raman [Sat, 18 May 2013 01:35:04 +0000 (01:35 +0000)]
tree-ssa-reassoc.c (find_insert_point): New function.
2013-05-17 Easwaran Raman <eraman@google.com>
* tree-ssa-reassoc.c (find_insert_point): New function.
(insert_stmt_after): Likewise.
(get_def_stmt): Likewise.
(ensure_ops_are_available): Likewise.
(not_dominated_by): Likewise.
(rewrite_expr_tree): Do not move statements beyond what is
necessary. Remove call to swap_ops_for_binary_stmt...
(reassociate_bb): ... and move it here.
(build_and_add_sum): Assign UIDs for new statements.
(linearize_expr): Likewise.
(do_reassoc): Renumber gimple statement UIDs.
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