Jani Nikula [Tue, 12 Nov 2024 11:10:44 +0000 (13:10 +0200)]
drm/i915/dp: add comments about hooks called from MST stream encoders
It would be best to have self-explanatory code, but lacking that, add
some comments about the way the DDI encoder hooks get called from DP MST
stream encoders.
Jani Nikula [Tue, 12 Nov 2024 11:10:43 +0000 (13:10 +0200)]
drm/i915/mst: change naming from fake encoders to MST stream encoders
The fake encoders pretty much match individual MST streams. The encoders
remain as fake as ever, but change the naming to MST stream
encoders. Rename all the encoder hooks and related functions called from
them to mst_stream_* to clarify what type of encoders the hooks are
called on.
Jani Nikula [Tue, 12 Nov 2024 11:10:42 +0000 (13:10 +0200)]
drm/i915/mst: convert to struct intel_display
struct intel_display will replace struct drm_i915_private as the main
display device data structure. Convert the DP MST code to struct
intel_display as much as possible.
Jani Nikula [Tue, 12 Nov 2024 11:10:41 +0000 (13:10 +0200)]
drm/i915/display: make CHICKEN_TRANS() display version aware
Making register macros platform or display version aware is not exactly
something I want to promote widely, but in this case it's the lesser of
two evils. hsw_chicken_trans_reg() is not pretty, and it doesn't have a
suitable home.
Jani Nikula [Tue, 12 Nov 2024 11:10:39 +0000 (13:10 +0200)]
drm/i915/mst: introduce to_primary_encoder() and to_primary_dp()
Add helpers to_primary_encoder() and to_primary_dp() to convert fake MST
encoder pointers to primary encoder and DP pointers, respectively, and
use them.
The main point is to highlight the primary encoder and DP usage. Very
few places actually need the struct intel_dp_mst_encoder pointer, or the
primary struct intel_digital_port, so ditch them where possible for
clarity.
Jani Nikula [Tue, 12 Nov 2024 11:10:37 +0000 (13:10 +0200)]
drm/i915/mst: pass primary encoder to primary encoder hooks
Pass the primary encoder to the primary encoder hooks. This is
pedantically correct, but intel_ddi_post_pll_disable() also works with
the fake encoder by coincidence.
Jani Nikula [Mon, 11 Nov 2024 10:34:04 +0000 (12:34 +0200)]
drm/i915/display: add mobile platform group
Identify mobile platforms separately in display, using the platform
group mechanism. This enables dropping the dependency on i915_drv.h
IS_MOBILE() from display code.
Jani Nikula [Mon, 11 Nov 2024 10:34:03 +0000 (12:34 +0200)]
drm/i915/display: pass struct pci_dev * to intel_display_device_probe()
Convert intel_display_device_probe() to accept struct pci_dev * instead
of struct drm_i915_private *. Return struct intel_display * in
preparation of allocating the memory of it later.
Jani Nikula [Mon, 11 Nov 2024 10:34:02 +0000 (12:34 +0200)]
drm/i915/display: convert display device identification to struct intel_display
Convert intel_display_device.[ch] to struct intel_display, including
callers, but excluding intel_display_device_probe() which will be
handled in follow-up.
Jani Nikula [Mon, 11 Nov 2024 10:33:50 +0000 (12:33 +0200)]
drm/i915/display: identify discrete graphics
Identify discrete graphics separately in display, using the platform
group mechanism. This enables dropping the dependency on i915_drv.h
IS_DGFX() from display code.
Start grouping platform groups separately in INTEL_DISPLAY_PLATFORMS()
in anticipation of more groups to come.
Suraj Kandpal [Mon, 4 Nov 2024 03:59:51 +0000 (09:29 +0530)]
drm/i915/hdcp: Fix when the first read and write are retried
Make sure that the first read/write in hdcp2_authentication_key_exchange
are only retried when we have either DP/DPMST encoder connected,
since we do this to give docks and dp encoders some extra time to
get their HDCP DPCD registers ready only for DP/DPMST encoders as
this issue is only observed here no need to burden other encoders
with extra retries as this causes the HDMI connector to have some
other timing issue and fails HDCP authentication.
--v2
-Add intent of patch [Chaitanya]
-Add reasoning for loop [Jani]
-Make sure we forfiet the 50ms wait for non DP/DPMST encoders.
--v3
-Remove the is_dp_encoder check [Jani/Chaitanya]
-Make the commit message more clearer [Jani]
Ville Syrjälä [Thu, 7 Nov 2024 12:26:55 +0000 (14:26 +0200)]
drm/i915/scaler: Convert the scaler code to intel_display
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the scaler code to
use it (as much as possible at this stage).
Ville Syrjälä [Thu, 7 Nov 2024 12:26:54 +0000 (14:26 +0200)]
drm/i915/scaler: Clean up intel_atomic_setup_scalers() a bit
intel_atomic_setup_scalers() is currently messing around with
the internals of the atomic states. Stop doing that and instead
use the regular interfaces so that we don't need to know any ugly
implementation details.
Ville Syrjälä [Thu, 7 Nov 2024 12:26:53 +0000 (14:26 +0200)]
drm/i915/scaler: Pass the whole atomic state into intel_atomic_setup_scalers()
intel_atomic_setup_scalers() currently digs out the full atomic
state from the crtc state. Flip that on its head so that we instead
pass in the full atomic state and dig out the crtc state (and whatever
else we need). This is generallte the better approach as it works
in all phases of the atomic commit, whereas the other apporoach only
really works during .atomic_check().
Ville Syrjälä [Thu, 7 Nov 2024 16:11:18 +0000 (18:11 +0200)]
drm/i915/crt: Clean up ADPA_HOTPLUG_BITS definitions
ADPA_HOTPLUG_BITS is defined in terms of the individual
register bits and is defined in intel_crt.c, whereas the
counterpart mask (ADPA_CRT_HOTPLUG_MASK) is just defined
as a raw hex constant and lives in i915_reg.h. Just define
both the same way (with unified name to boot) and move both
to intel_crt.c since they are more an implementation detail
rather than anything to do with the actual register definitions.
Ville Syrjälä [Thu, 7 Nov 2024 16:11:14 +0000 (18:11 +0200)]
drm/i915: Grab intel_display from the encoder to avoid potential oopsies
Grab the intel_display from 'encoder' rather than 'state'
in the encoder hooks to avoid the massive footgun that is
intel_sanitize_encoder(), which passes NULL as the 'state'
argument to encoder .disable() and .post_disable().
TODO: figure out how to actually fix intel_sanitize_encoder()...
Jani Nikula [Tue, 29 Oct 2024 11:32:48 +0000 (13:32 +0200)]
drm/i915/psr: add LATENCY_REPORTING_REMOVED() register bit helper
Drop the wa_16013835468_bit_get() function in favour of the register
macro. It doesn't have to be so complicated, and we don't have to use
the workaround name in everything that's related to it.
Jani Nikula [Wed, 6 Nov 2024 16:23:25 +0000 (18:23 +0200)]
drm/i915/dp: demote source OUI read/write failure logging to debug
Commit 1f12d63a14d7 ("drm/i915/dp: Write the source OUI for non-eDP
sinks as well") started writing source OUI for non-eDP sinks as well,
increasing the possibilities of hitting read/write failures either due
to the sink behaviour or hotplug or whatever.
Even before that, commit 3fb0501f0c07 ("drm/i915/display/dp: Reduce log
level for SOURCE OUI write failures") already reduced write failures to
info level when source OUI was just for eDP.
Further reduce the log level to just debug. Switch to struct
intel_display while at it.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:20 +0000 (09:57 -0300)]
drm/i915/xe3lpd: Use DMC wakelock by default
Although Bspec doesn't explicitly mentions that, as of Xe3_LPD, using
DMC wakelock is the officially recommended way of accessing registers
that would be off during DC5/DC6 and the legacy method (where the DMC
intercepts MMIO to wake up the hardware) is to be avoided.
As such, update the driver to use the DMC wakelock by default starting
with Xe3_LPD. Since the feature is somewhat new to the driver, also
allow disabling it via a module parameter for debugging purposes.
For that, make the existing parameter allow values -1 (per-chip
default), 0 (disabled) and 1 (enabled), similarly to what is done for
other parameters.
v2:
- Describe -1 in the same area where 0 and 1 are described. (Luca)
Gustavo Sousa [Fri, 8 Nov 2024 12:57:18 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Add and use HAS_DMC_WAKELOCK()
A HAS_DMC_WAKELOCK() macro gives more semantic than openly checking the
display version. Define it and use it where appropriate.
v2:
- Make this patch contain only the non-functional refactor. Functional
changes related to including HAS_DMC() in the macro are done in
upcoming changes. (Jani)
Gustavo Sousa [Fri, 8 Nov 2024 12:57:17 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Couple enable/disable with dynamic DC states
Enabling and disabling the DMC wakelock should be done as part of
enabling and disabling of dynamic DC states, respectively. We should not
enable or disable DMC wakelock independently of DC states, otherwise we
would risk ending up with an inconsistent state where dynamic DC states
are enabled and the DMC wakelock is disabled, going against current
recommendations and making MMIO transactions potentially slower. In
future display IPs that could have a worse outcome if DMC trap
implementation is completely removed.
So, let's make things safer by tying stuff together, removing the
independent calls, and also put warnings in place to detect inconsistent
calls.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:16 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Deal with existing references when disabling
It is possible that there are active wakelock references at the time we
are disabling the DMC wakelock mechanism. We need to deal with that in
two ways:
(A) Implement the missing step from Bspec:
The Bspec instructs us to clear any existing wakelock request bit
after disabling the mechanism. That gives a clue that it is okay to
disable while there are locks held and we do not need to wait for
them. However, since the spec is not explicit about it, we need
still to get confirmation with the hardware team. Let's thus
implement the spec and add a TODO note.
(B) Ensure a consistent driver state:
The enable/disable logic would be problematic if the following
sequence of events would happen:
1. Function A calls intel_dmc_wl_get();
2. Some function calls intel_dmc_wl_disable();
3. Some function calls intel_dmc_wl_enable();
4. Function A is done and calls intel_dmc_wl_put().
At (2), the refcount becomes zero and then (4) causes an invalid
decrement to the refcount. That would cause some issues:
- At the time between (3) and (4), function A would think that
the hardware lock is held but it could not be really held
until intel_dmc_wl_get() is called by something else.
- The call made to (4) could cause the refcount to become zero
and consequently the hardware lock to be released while there
could be innocent paths trusting they still have the lock.
To fix that, we need to keep the refcount correctly in sync with
intel_dmc_wl_{get,put}() calls and retake the hardware lock when
enabling the DMC wakelock with a non-zero refcount.
One missing piece left to be handled here is the following scenario:
1. Function A calls intel_dmc_wl_get();
2. Some function calls intel_dmc_wl_disable();
3. Some function calls intel_dmc_wl_enable();
4. Concurrently with (3), function A performs the MMIO in between
setting DMC_WAKELOCK_CFG_ENABLE and asserting the lock with
__intel_dmc_wl_take().
I'm mostly sure this would cause issues future display IPs if DMC
trap implementation was completely removed. We need to check with
the hardware team whether it would be safe to assert the hardware
lock before setting DMC_WAKELOCK_CFG_ENABLE to avoid this scenario.
If not, then we would have to deal with that via software
synchronization.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:15 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Allow simpler syntax for single reg in range tables
Allow simpler syntax for defining entries for single registers in range
tables. That makes them easier to type as well as to read, allowing one
to quickly tell whether a range actually refers to a single register or
a "true range".
Gustavo Sousa [Fri, 8 Nov 2024 12:57:14 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Track registers touched by the DMC
There are extra registers that require the DMC wakelock when specific
dynamic DC states are in place. Those are registers that are touched by
the DMC and require DC exit for proper access. Add the range tables for
them and use the correct one depending on the enabled DC state.
v2:
- Do not look into power domains guts (i.e.
display->power.domains.dc_state). (Jani)
- Come up with better names for variables containing register ranges.
(Luca)
- Keep a copy of dc_state in struct intel_dmc_wl.
- Update commit message for a clearer explanation for the need of
these new tables.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:13 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Rename lnl_wl_range to powered_off_ranges
In an upcoming change, we will add extra range tables for registers that
are touched by the DMC during DC states. The range table that we are
currently using is meant for registers that are powered off during DC
states. As such, let's rename the table to powered_off_ranges and also
add a comment regarding its purpose in the function that uses it.
We will be using more than one range table in
intel_dmc_wl_check_range(). As such, move the logic to a new function
and name it intel_dmc_wl_reg_in_range().
Gustavo Sousa [Fri, 8 Nov 2024 12:57:11 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Use sentinel item for range tables
We are currently using ARRAY_SIZE() to iterate address ranges in
intel_dmc_wl_check_range(). In upcoming changes, we will be using more
than a single table and will extract the range checking logic into a
dedicated function that takes a range table as argument. As we will not
able to use ARRAY_SIZE() then, let's make range tables contain a
sentinel item at the end and use that instead of having to pass the size
as parameter in this future function.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:09 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Check for non-zero refcount in release work
When the DMC wakelock refcount reaches zero, we know that there are no
users and that we can do the actual release operation on the hardware,
which is queued with a delayed work. The idea of the delayed work is to
avoid performing the release if a new lock user appears (i.e. refcount
gets incremented) in a very short period of time.
Based on the above, the release work should bail out if refcount is
non-zero (meaning new lock users appeared in the meantime), but our
current code actually does the opposite: it bails when refcount is zero.
That means that the wakelock is not released when it should be; and
that, when the work is not canceled in time, it ends up being releasing
when it should not.
Gustavo Sousa [Fri, 8 Nov 2024 12:57:08 +0000 (09:57 -0300)]
drm/i915/dmc_wl: Use non-sleeping variant of MMIO wait
Some display MMIO transactions for offsets in the range that requires
the DMC wakelock happen in atomic context (this has been confirmed
during tests on PTL). That means that we need to use a non-sleeping
variant of MMIO waiting function.
Implement __intel_de_wait_for_register_atomic_nowl() and use it when
waiting for acknowledgment of acquire/release.
v2:
- No __intel_de_wait_for_register_atomic_nowl() wrapper to convert
i915 to display. (Jani)
- Add a quick explanation why DMC_WAKELOCK_CTL_TIMEOUT_US is defined
in microseconds. (Luca)
Gustavo Sousa [Fri, 8 Nov 2024 12:57:07 +0000 (09:57 -0300)]
drm/xe: Mimic i915 behavior for non-sleeping MMIO wait
In upcoming display changes, we will modify the DMC wakelock MMIO
waiting code to choose a non-sleeping variant implementation, because
the wakelock is also taking in atomic context.
While xe provides an explicit parameter (namely "atomic") to prevent
xe_mmio_wait32() from sleeping, i915 does not and implements that
behavior when slow_timeout_ms is zero.
So, for now, let's mimic what i915 does to allow for display to use
non-sleeping MMIO wait. In the future, we should come up with a better
and explicit interface for this behavior in i915, at least while display
code is not an independent entity with proper interfaces between xe and
i915.
v2:
- Make the tone in comment the comment added in
__intel_wait_for_register() more explanatory than a FIXME-like text.
(Luca)
Suraj Kandpal [Thu, 7 Nov 2024 02:28:08 +0000 (07:58 +0530)]
drm/i915/hdcp: Handle HDCP Line Rekeying for HDCP 1.4
TRANS_DDI_FUNC_CTL asks us to disable hdcp line rekeying when not in
hdcp 2.2 and we are not using an hdmi transcoder and it need to be
enabled when we are using an HDMI transcoder to enable HDCP 1.4.
We use intel_de_rmw cycles to update TRANS_DDI_FUNC_CTL register so
we cannot depend on the value being 0 by default everytime which calls
for seprate handling of HDCP 1.4 case.
--v2
-Use the exising function and modify it based on a bool rather than
have a different function [Matt]
--v3
-No need for kzalloc [Jani]
--v4
-i915_reg_t should not be pointer [Jani]
-use rekey_bit to ensure when writing to reg everything is initialized
Ville Syrjälä [Tue, 29 Oct 2024 21:52:17 +0000 (23:52 +0200)]
drm/i915/cdclk: Unify cdclk max() parameter order
In some places we do
min_cdclk = max(min_cdclk, other_min_cdclk)
and in other places we have the arguments swapped as
min_cdclk = max(other_min_cdclk, min_cdclk)
Unify everyone to use the first order of arguments, because
it looks cleaner, especially within intel_crtc_compute_min_cdclk()
which is doing a lot of these back-to-back.
Ville Syrjälä [Tue, 29 Oct 2024 21:52:10 +0000 (23:52 +0200)]
drm/i915/cdclk: Extract intel_audio_min_cdclk()
Pull the audio min cdclk calculation into a helper and hide
it inside intel_audio.c in order to keep most audio related
details in one place.
The one audio related thing that remains in intel_cdclk.c
is commit 451eaa1a614c ("drm/i915: Bump GLK CDCLK frequency when
driving multiple pipes") but given that's implemented in terms
of the cdclk_state I think it should stay put.
Ville Syrjälä [Tue, 29 Oct 2024 21:52:09 +0000 (23:52 +0200)]
drm/i915/cdclk: Extract hsw_ips_min_cdclk()
Pull the whole BDW IPS min CDCLK stuff into the IPS code
so that all the details around IPS are contained in once
place.
Note that while
- min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
vs.
+ min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)
may look different, they are in fact the same because
min_cdclk==crtc_state->pixel_rate at this point in
intel_crtc_compute_min_cdclk() on BDW.
Ville Syrjälä [Tue, 29 Oct 2024 21:52:08 +0000 (23:52 +0200)]
drm/i915/cdclk: Extract intel_cdclk_guardband() and intel_cdclk_ppc()
We are duplicating the CDCLK guardband and "pixels per clock"
figures in two places. Pull those out into small helpers that
can be used by both places.
Ville Syrjälä [Wed, 6 Nov 2024 22:09:04 +0000 (00:09 +0200)]
drm/i915/dsi: Stop using pixel_format_from_register_bits() to parse VBT
Introduce a proper VBT->enum mipi_dsi_pixel_format converter
instead of abusing pixel_format_from_register_bits() (whose
job is to parse the pixel format from some pre-ICL DSI
hardware register).
Imre Deak [Wed, 30 Oct 2024 19:23:12 +0000 (21:23 +0200)]
drm/i915/adlp+/dp_mst: Align slave transcoder sequences with spec wrt. DP2 config
On ADLP+ during modeset enabling and disabling, enable and disable the DP2
configuration for MST slave transcoders as required by the specification.
Update the documentation of intel_ddi_config_transcoder_func() /
intel_ddi_disable_transcoder_func() based on the above. While at it also
clarify the programming steps of these functions specific to transcoder
types.
v2:
- Enable/disable the DP2 config from
intel_ddi_config_transcoder_func()/intel_ddi_disable_transcoder_func().
(Jani)
- Handle all ADLP+ platforms in one patch, instead of doing that
separately wrt. PTL.
Imre Deak [Wed, 30 Oct 2024 19:23:10 +0000 (21:23 +0200)]
drm/i915/adlp+/dp_mst: Align slave transcoder enabling with spec wrt. DDI function
On ADLP+ during modeset enabling configure the DDI function without
enabling it for MST slave transcoders before programming the data and
link M/N values. The DDI function gets enabled separately later in the
transcoder enabling sequence.
Align the code with the spec based on the above.
v2: Move this patch earlier in the series, addressing the DP2
config fixes for all ADLP+ platforms later.
Imre Deak [Wed, 30 Oct 2024 19:23:09 +0000 (21:23 +0200)]
drm/i915/ptl/dp_mst: Fix slave transcoder enabling wrt. DDI function
On PTL during modeset enabling configure the DDI function without
enabling it for MST slave transcoders before programming the data and
link M/N values. The DDI function gets enabled separately later in the
transcoder enabling sequence.
This fixes a slave transcoder getting stuck during enabling, leading
to page flip timeout errors on the corresponding pipe.
The spec requires the same programming step for ADLP+ platforms, that
will be addressed separately (on those platforms the above transcoder
getting stuck issue was not observed).
Ville Syrjälä [Thu, 31 Oct 2024 15:56:45 +0000 (17:56 +0200)]
drm/i915: Sanitize MBUS joining
If the system boots with MBUS joining enabled but we disable
the relevant pipe during sanitation we later get into trouble
as the rest of the code doesn't expect MBUS joining to be
enabled unless the set of active pipes is in agreement.
We could relax some of the MBUS joining related checks during
normal atomic commits to let this slide, but that might also
let some real bugs through. So let's sanitize the MBUS joining
instead. And in order to keep things more or less in sync we'll
do the related credit, cdclk/mdclk ratio, etc. updates as well.
We'll stick to sturct drm_i915_private for now (instead of
struct intel_display) since the rest of the skl wm code does the
same, and we might need to bakport this.
Ville Syrjälä [Thu, 31 Oct 2024 15:56:44 +0000 (17:56 +0200)]
drm/i915: Extract mbus_ctl_join_update()
We'll be wanting to reprogram the MBUS_CTL register during an
upcoming MBUS sanitation stage. Extract the reprogramming
into a helper that doesn't depend on the full atomic state
so that it can be reused.
We'll stick to sturct drm_i915_private for now (instead of
struct intel_display) since the rest of the skl wm code does the
same, and we might need to bakport this.
Ville Syrjälä [Thu, 31 Oct 2024 15:56:43 +0000 (17:56 +0200)]
drm/i915: Extract pipe_mbus_dbox_ctl_update()
We'll be wanting to reprogram the PIPE_MBUS_DBOX_CTL registers
during an upcoming MBUS sanitation stage. Extract the reprogramming
loop into a helper that doesn't depend on the full atomic state
so that it can be reused.
We'll stick to sturct drm_i915_private for now (instead of
struct intel_display) since the rest of the skl wm code does the
same, and we might need to bakport this.
Ville Syrjälä [Thu, 31 Oct 2024 15:56:42 +0000 (17:56 +0200)]
drm/i915: Extract pipe_mbus_dbox_ctl()
We'll be wanting to reprogram the PIPE_MBUS_DBOX_CTL registers
during an upcoming MBUS sanitation stage. To make that easier
extract a helper that computes the full register value for us.
Ville Syrjälä [Thu, 31 Oct 2024 15:56:41 +0000 (17:56 +0200)]
drm/i915: Relocate the SKL wm sanitation code
In order to add more MBUS sanitation into the code we'll want
to reuse a bunch of the code that performs the MBUS/related
hardware programming. Currently that code comes after the
main skl_wm_get_hw_state_and_sanitize() entrypoint. In order
to avoid annoying forward declarations relocate the
skl_wm_get_hw_state_and_sanitize() and related stuff nearer to
the end of the file.
Ankit Nautiyal [Wed, 30 Oct 2024 04:10:36 +0000 (09:40 +0530)]
drm/i915/dp: Enable 3 DSC engines for 12 slices
Certain resolutions require 12 DSC slices support along with ultrajoiner.
For such cases, the third DSC Engine per Pipe is enabled. Each DSC
Engine processes 1 Slice, resulting in a total of 12 VDSC slices
(4 Pipes * 3 DSC Instances per Pipe).
Add support for 12 DSC slices and 3 DSC engines for such modes.
v2: Add missing check for 3 slices support only with 4 joined pipes.
(Suraj)
Ankit Nautiyal [Wed, 30 Oct 2024 04:10:35 +0000 (09:40 +0530)]
drm/i915/dp: Ensure hactive is divisible by slice count
According to the DSC spec, the slice width should be chosen such that
the picture width (hactive) is evenly divisible by the slice width.
If not, extra pixels (padding) must be added to the last slice to
ensure all slices have the same width.
Currently, we do not support handling these extra pixels.
Therefore, select a slice count that evenly divides the hactive
(slice_width = hactive / slice_count).
This check is already implemented for DSI, where the slice count is
selected from the BIOS.
For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have
slice count not being able to divide hactive, but with 3 DSC engines
and 3 slices, we can have such cases. Adding this check prepares for
future scenarios where such configurations might be used.
Ankit Nautiyal [Wed, 30 Oct 2024 04:10:31 +0000 (09:40 +0530)]
drm/i915/display: Prepare for dsc 3 stream splitter
At the moment dsc_split represents whether the dsc splitter is used
or not. With 3 DSC engines, the splitter can split into two streams
or three streams.
Instead of representing the splitter's state, it is more effective to
represent the number of DSC streams per pipe.
Replace the `dsc.dsc_split` member with `dsc.num_streams` to indicate the
number of DSC streams used per pipe. This change will implicitly
convey the splitter's operation mode.
v2: Avoid new enum for dsc split. (Suraj)
v3:
-Replace dsc_split with num_stream. (Suraj)
-Avoid extra parentheses. (Jani)
v4: Set num_streams to 1, if VDSC_JOINER not set while readout.
Ankit Nautiyal [Wed, 30 Oct 2024 04:10:30 +0000 (09:40 +0530)]
drm/i915/dp: Update Comment for Valid DSC Slices per Line
For some platforms, the maximum slices per DSC engine is 4, while for
others it is 2. Update the comment to reflect this and clarify that
the 'valid_dsc_slicecount' list represents the valid number of slices
per pipe.
Currently, we are working with 1, and 2 slices per DSC engine,
which works for all platforms. With this the number of slices per pipe
can be 1,2 or 4 with different slice & DSC engine configuration.
Add a #TODO for adding support for 4 slices per DSC engine where
supported.
drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.
All MTL and ARL SKUs share the same GSC FW, but the newer platforms are
only supported in newer blobs. In particular, ARL-S is supported
starting from 102.0.10.1878 (which is already the minimum required
version for ARL in the code), while ARL-H and ARL-U are supported from
102.1.15.1926. Therefore, the driver needs to check which specific ARL
subplatform its running on when verifying that the GSC FW is new enough
for it.
Fixes: 2955ae8186c8 ("drm/i915: ARL requires a newer GSC firmware") Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241028233132.149745-1-daniele.ceraolospurio@intel.com
Jani Nikula [Tue, 29 Oct 2024 09:25:25 +0000 (11:25 +0200)]
drm/i915: add a dedicated mutex for VLV/CHV IOSF sideband
The VLV/CHV IOSF sideband is unrelated to pcode. It's just confusing to
piggyback on the same mutex. Add a dedicated lock with init and cleanup
functions.
Jani Nikula [Tue, 29 Oct 2024 09:25:24 +0000 (11:25 +0200)]
drm/i915/sbi: add a dedicated mutex for LPT/WPT IOSF sideband
The LPT/WPT IOSF sideband is unrelated to pcode or VLV/CHV IOSF
sideband. It's just confusing to piggyback on the same mutex. Add a
dedicated lock with init and cleanup functions.
Suraj Kandpal [Mon, 4 Nov 2024 18:50:55 +0000 (00:20 +0530)]
drm/i915/xe3lpd: Update HDCP rekeying bit
The TRANS_DDI_FUNC_CTL bit used to enable/disable HDCP rekeying
has moved from bit 12 (Xe2) to bit 15 (Xe3); update the RMW
toggle accordingly.
Also drop the misleading workaround comment tag on this function
since disabling of HDCP rekeying is something that happens on
all platforms, not just those impacted by that workaround.
While we're here, also re-order the if/else ladder to use
standard "newest platform first" order.
v2: add additional definition instead of function, commit message typo
fix and update.
v3: restore lost conditional from v2.
v4: subject line and subject message updated, fix the if ladder order,
fix the bit definition order.
v5: Add the bspec link and remove the Wa comment tag
v6: Rebase over new changes
v7: Fix commit subject and message, reladder the if/else blocks
drm/i915/display: Allow fastset for change in HDR infoframe
Changes in Dynamic Range and Mastering infoframe
should not trigger a full modeset. Therefore, allow
fastset. DP SDP programming is already hooked up in the
fastset flow but HDMI AVI infoframe update is not, add it.
Any other infoframe that can be fastset should be added to
the helper intel_hdmi_fastset_infoframes().
v3:
- Create a wrapper intel_ddi_update_pipe_hdmi to stick to
uniform naming (Jani)
- Do not disable HDMI AVI infoframe if already disabled (Uma)
Jouni Högander [Tue, 29 Oct 2024 12:24:15 +0000 (14:24 +0200)]
drm/i915/psr: WA for panels stating bad link status after PSR is enabled
We are currently seeing unexpected link trainings with several different
eDP panels. These are caused by these panels stating bad link status in
their dpcd registers. This can be observed by doing following test:
1. Boot up without Xe module loaded
2. Load Xe module with PSR disabled:
$ modprobe xe enable_psr=0
3. Read panel link status register
$ dpcd_reg read --offset 0x200e --count=1
0x200e: 00
4. Enable PSR, sleep for 2 seconds and disable PSR again:
projects / thirdparty / kernel / linux.git / log
