Frank Min [Wed, 10 Apr 2024 13:40:16 +0000 (21:40 +0800)]
drm/amdgpu: add sdma 7.0 support for copy dcc buffer
1. Add dcc buffer flag for copy buffer
2. Add sdma 7.0 support copy dcc buffer
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Chang [Fri, 10 May 2024 02:38:19 +0000 (10:38 +0800)]
drm/amd/display: Extend PSRSU residency mode
1. To support multiple PSRSU residency measurement mode
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add outbox notification support for HPD redetect
[Why]
HPD sense changes can occur during low power states and need to be
notified from firmware to driver. Upon notification the hotplug
redetection routines should execute.
[How]
Add Support in DMUB srv and DMUB srv stat for receiving these
notifications. DM can hook them up and process the HPD redetection
once received.
Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add null checks for 'stream' and 'plane' before dereferencing
This commit adds null checks for the 'stream' and 'plane' variables in
the dcn30_apply_idle_power_optimizations function. These variables were
previously assumed to be null at line 922, but they were used later in
the code without checking if they were null. This could potentially lead
to a null pointer dereference, which would cause a crash.
The null checks ensure that 'stream' and 'plane' are not null before
they are used, preventing potential crashes.
Fixes the below static smatch checker:
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c:938 dcn30_apply_idle_power_optimizations() error: we previously assumed 'stream' could be null (see line 922)
drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn30/dcn30_hwseq.c:940 dcn30_apply_idle_power_optimizations() error: we previously assumed 'plane' could be null (see line 922)
Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fangzhi Zuo [Fri, 10 May 2024 19:23:02 +0000 (15:23 -0400)]
drm/amd/display: Prevent IPX From Link Detect and Set Mode
IPX involvment proven to affect LT, causing link loss. Need to prevent
IPX enabled in LT process in which link detect and set mode are main
procedures that have LT taken place.
Reviewed-by: Roman Li <roman.li@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lin.Cao [Fri, 31 May 2024 06:02:39 +0000 (14:02 +0800)]
drm/amdgpu: fix failure mapping legacy queue when FLR
Flag "mes.ring.shced.ready" will be set as true after mes hw init and set
as false when mes hw fini to avoid duplicate initialization. But hw fini
will not be called when function level reset, which will cause mes hw
init be skipped during FLR, which will leads to mapping legacy queue
fail. Set this flag as false when post reset will fix this issue.
Signed-off-by: Lin.Cao <lincao12@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Daniel Sa [Thu, 16 May 2024 16:03:34 +0000 (12:03 -0400)]
drm/amd/display: Fetch Mall caps from DC
[Why]
When performing P-State switching with Subvp on 8k (downscaled to 4k).
corruption can be seen on the screen. MALL data was not being fetched
from DC, and the system things there is more MALL space then what is
actually available.
[How]
Read MALL size from dc caps.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Daniel Sa <daniel.sa@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Wed, 15 May 2024 21:32:29 +0000 (17:32 -0400)]
drm/amd/display: fix YUV video color corruption in DCN401
[Why]
Missing check causes sequence error which results in chroma
filter coefficients not being updated in certain modes
when we display YUV video in fullscreen. This results in
color corruption in video
[How]
Add back chroma_coef_mode check in dscl_set_scl_filter
so that filter coefficients are calculated and updated when
we have YUV surface
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 27 May 2024 05:22:16 +0000 (13:22 +0800)]
drm/amdgpu: Update soc24_enum.h and soc21_enum.h
Update to latest changes.
Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 3 Jun 2024 01:53:58 +0000 (09:53 +0800)]
drm/amdgpu: Set PTE_IS_PTE bit for gfx12
Set PTE_IS_PTE bit while PRT is enabled on gfx12.
Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Tue, 14 May 2024 20:22:01 +0000 (16:22 -0400)]
drm/amd/display: Use current_state when checking old_pipe subvp type
[Description]
When checking the subvp type of the previous state we must
pass in current_state to the interface instead of context
otherwise we will get the wrong result.
Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Thu, 30 May 2024 03:27:28 +0000 (11:27 +0800)]
drm/amdkfd: remove dead code in kfd_create_vcrat_image_gpu
kfd_create_vcrat_image_gpu itself checks the avail_size at the start.
So the value of avail_size is at least VCRAT_SIZE_FOR_GPU(16384),
minus struct crat_header(40UL) and struct crat_subtype_compute(40UL) it cannot be less than 0.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Fri, 31 May 2024 01:56:40 +0000 (09:56 +0800)]
drm/amdkfd: fix the kdf debugger issue
The expression caps | HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED
and caps | HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED
are always 1/true regardless of the values of its operand.
Fixes: 9243240bed38 ("drm/amdkfd: enable single alu ops for gfx12") Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 26 Apr 2024 21:28:46 +0000 (17:28 -0400)]
drm/amd/display: Move fpo_in_use to stream_status
[Description]
Refactor code and move fpo_in_use into stream_status to avoid
unexpected changes to previous dc_state (i.e., current_state).
Since stream pointers are shared between current and new dc_states,
updating parameters of one stream will update the other as well
which causes unexpected behaviors (i.e., checking that fpo_in_use
isn't set in previous state and set in the new state is invalid).
To avoid incorrect updates to current_state, move the fpo_in_use flag
into dc_stream_status since stream_status is owned by dc and are not
shared between different dc_states.
Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 26 Apr 2024 21:14:19 +0000 (17:14 -0400)]
drm/amd/display: Only program P-State force if pipe config changed
[Description]
Today for MED update type we do not call update clocks. However, for FPO
the assumption is that update clocks should be called to disable P-State
switch before any HW programming since FPO in FW and driver are not
synchronized. This causes an issue where on a MED update, an FPO P-State
switch could be taking place, then driver forces P-State disallow in the below
code and prevents FPO from completing the sequence. In this case we add a check
to avoid re-programming (and thus re-setting) the P-State force register by
only reprogramming if the pipe was not previously Subvp or FPO. The assumption
is that the P-State force register should be programmed correctly the first
time SubVP / FPO was enabled, so there's no need to update / reset it if the
pipe config has never exited SubVP / FPO.
Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joan Lee [Wed, 15 May 2024 02:23:01 +0000 (10:23 +0800)]
drm/amd/display: Add retires when read DPCD
[why & how]
Sometimes read DPCD return fail while result not retrieved yet. Add
retries mechanism in Replay handle hpd irq to get real result.
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joan Lee <joan.lee@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Susanto [Tue, 14 May 2024 15:38:39 +0000 (11:38 -0400)]
drm/amd/display: Fix DML2 logic to set clk state to min
[Why]
When an eDP with high clock states is going into s0i3, stream_count is
0. This causes DML to not update the clks to the lowest state and
blocking us to enter s0i3 since eDP is out of vmin.
[How]
When stream_count is 0, set all the clocks to the lowest state.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Tue, 28 May 2024 20:55:56 +0000 (15:55 -0500)]
drm/amdkfd: Handle deallocated VPGRs in gfx11+ trap handler
A wavefront may deallocate its VGPRs at the end of a program while
waiting for memory transactions to complete. If it subsequently
receives a context save exception it will be unable to save,
since this requires VGPRs. In this case the trap handler should
terminate the wavefront.
Fixes intermittent VM faults under context switching load.
V2: Use S_ENDPGM instead of S_ENDPGM_SAVED for performance counters
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chris Park [Tue, 14 May 2024 17:55:18 +0000 (13:55 -0400)]
drm/amd/display: Support new VA page table block size
[Why]
Page table definition increased up to 2MB.
[How]
Define new use case of page table for VA.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Mon, 13 May 2024 22:14:59 +0000 (18:14 -0400)]
drm/amd/display: workaround for oled eDP not lighting up on DCN401
[Why]
Currently there's an issue on DCN401 that prevents oled eDP panels from
being lit up that is still under investigation. To unblock dev work
while investigating, we can work around the issue by skipping toggling
the enablement of the backlight.
[How]
- new debug bit that will skip touching backlight enable DPCD for oled
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chun-LiangChang [Fri, 10 May 2024 07:00:18 +0000 (02:00 -0500)]
drm/amd/display: Add params of set_abm_event for VB Scaling
[Why]
Add parameters for set_abm_event to enable varibright scaling.
VariBright Scaling is a feature to refer to system states like
1. Power mode
2. Battery Life percent
3. FullScreen video
4. Backlight slider
to adjust variBright strength to get low power or user experience.
[How]
Add parameters of set_abm_event for VB Scaling
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Chun-LiangChang <chuchang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The values calculated in optc1_get_otg_active_size are assigned to the
wrong output parameters, vertical blank is being used for horizontal size
and vice versa. This results in DPG test pattern looking wrong during
hardware init, as the DPG dimensions get assigned from this output, and
potentially other issues.
Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Fri, 10 May 2024 16:43:53 +0000 (12:43 -0400)]
drm/amd/display: turn on symclk for dio virtual stream in dpms sequence
[why]
In order to support glitchless display clock ramping for virtual stream,
we must
turn on symclk for stream encoder. The code will power on phy and enable
symclk
for dio encoder during virtual stream dpms sequence.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Keep VBios pixel rate div setting until next mode set
[why]
Vbios & Driver have difference pixel rate div policy.
When enabling fast boot & performing blank & unblank w/o timing setting,
pixel clock & pixel rate dividor are not match.
It would cause too high pixel reate and eDP would be black screen.
[How]
We would keep pixel rate div setting by Vbios until next timing setting.
Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by: yi-lchen <yi-lchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Thu, 30 May 2024 02:41:03 +0000 (10:41 +0800)]
drm/amdkfd: remove dead code in the function svm_range_get_pte_flags
The varible uncached set false, the condition uncached cannot be true.
So remove the dead code, mapping flags will set the flag AMDGPU_VM_MTYPE_UC in else.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 31 May 2024 09:32:11 +0000 (10:32 +0100)]
drm/amd/display: Fix a handful of spelling mistakes
There are a few spelling mistakes in dml2_printf messages. Fix them.
Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix type mismatch in amdgpu_gfx_kiq_init_ring
This commit fixes a type mismatch in the amdgpu_gfx_kiq_init_ring
function triggered by the snprintf function expecting unsigned char
arguments due to the '%hhu' format specifier, but receiving int and u32
arguments.
The issue occurred because the arguments xcc_id, ring->me, ring->pipe,
and ring->queue were of type int and u32, not unsigned char. This led to
a type mismatch when these arguments were passed to snprintf.
To resolve this, the snprintf line was modified to cast these arguments
to unsigned char. This ensures that the arguments are of the correct
type for the '%hhu' format specifier and resolves the warning.
Fixes the below:
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:4: warning: format
>> specifies type 'unsigned char' but the argument has type 'int'
>> [-Wformat]
xcc_id, ring->me, ring->pipe, ring->queue);
^~~~~~
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:12: warning: format
>> specifies type 'unsigned char' but the argument has type 'u32' (aka
>> 'unsigned int') [-Wformat]
xcc_id, ring->me, ring->pipe, ring->queue);
^~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:22: warning: format specifies type 'unsigned char' but the argument has type 'u32' (aka 'unsigned int') [-Wformat]
xcc_id, ring->me, ring->pipe, ring->queue);
^~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:34: warning: format specifies type 'unsigned char' but the argument has type 'u32' (aka 'unsigned int') [-Wformat]
xcc_id, ring->me, ring->pipe, ring->queue);
^~~~~~~~~~~
4 warnings generated.
Fixes: 0ea554455542 ("drm/amdgpu: Fix snprintf usage in amdgpu_gfx_kiq_init_ring") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405250446.XeaWe66u-lkp@intel.com/ Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Wed, 29 May 2024 09:29:01 +0000 (17:29 +0800)]
drm/amdgu: fix Unintentional integer overflow for mall size
Potentially overflowing expression mall_size_per_umc * adev->gmc.num_umc with type unsigned int (32 bits, unsigned)
is evaluated using 32-bit arithmetic,and then used in a context that expects an expression of type u64 (64 bits, unsigned).
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bill Wendling [Wed, 29 May 2024 21:54:44 +0000 (14:54 -0700)]
drm/radeon: Remove __counted_by from StateArray.states[]
Work for __counted_by on generic pointers in structures (not just
flexible array members) has started landing in Clang 19 (current tip of
tree). During the development of this feature, a restriction was added
to __counted_by to prevent the flexible array member's element type from
including a flexible array member itself such as:
struct foo {
int count;
char buf[];
};
struct bar {
int count;
struct foo data[] __counted_by(count);
};
because the size of data cannot be calculated with the standard array
size formula:
sizeof(struct foo) * count
This restriction was downgraded to a warning but due to CONFIG_WERROR,
it can still break the build. The application of __counted_by on the
states member of 'struct _StateArray' triggers this restriction,
resulting in:
drivers/gpu/drm/radeon/pptable.h:442:5: error: 'counted_by' should not be applied to an array with element of unknown size because 'ATOM_PPLIB_STATE_V2' (aka 'struct _ATOM_PPLIB_STATE_V2') is a struct type with a flexible array member. This will be an error in a future compiler version [-Werror,-Wbounds-safety-counted-by-elt-type-unknown-size]
442 | ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
Remove this use of __counted_by to fix the warning/error. However,
rather than remove it altogether, leave it commented, as it may be
possible to support this in future compiler releases.
Tvrtko Ursulin [Tue, 28 May 2024 12:57:11 +0000 (13:57 +0100)]
drm/amd/display: Convert some legacy DRM debug macros into appropriate categories
Currently when one enables driver debugging dmesg gets spammed, at I
suspect vblank rate, with messages like:
[drm:amdgpu_dm_atomic_check [amdgpu]] MPO enablement requested on crtc:[00000000f073c3bb]
Fix if by converting some logging from deprecated and incorrect
DRM_DEBUG_DRIVER to drm_dbg_atomic. Plus some localized drive-by changes
to drm_dbg_kms.
By no means an exhaustive conversion but at least it allows turning on
driver debug selectively.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 20 May 2024 08:47:32 +0000 (16:47 +0800)]
drm/amdgpu: use u32 for buf size in __amdgpu_eeprom_xfer
And also make sure the value of msg[1].len should be in the range of u16.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ensure STATE_PRIV.BARRIER_COMPLETE cannot change after reading or
before writing. Other waves in the threadgroup may cause this field
to assert if they complete the barrier.
Do not overwrite EXCP_FLAG_PRIV.{SAVE_CONTEXT,HOST_TRAP} when
restoring this register. Both of these fields can assert while the
wavefront is running the trap handler.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
We have messages when the VCN fails to initialize and
there is no need to report on success.
Also PSP loading FWs is the default for production.
Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Sonny Jiang <sonjiang@amd.com> Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shane Xiao [Wed, 29 May 2024 09:53:11 +0000 (17:53 +0800)]
drm/amdgpu: Update the impelmentation of AMDGPU_PTE_MTYPE_GFX12
This patch changes the implementation of AMDGPU_PTE_MTYPE_GFX12,
clear the bits before setting the new one.
This fixed the potential issue that GFX12 setting memory to NC.
v2: Clear mtype field before setting the new one (Alex)
v3: Fix typo (Felix)
Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: longlyao <Longlong.Yao@amd.com> Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arnd Bergmann [Tue, 28 May 2024 11:51:21 +0000 (13:51 +0200)]
drm/amd/display: Move 'struct scaler_data' off stack
The scaler_data structure is implicitly copied onto the stack twice by
being returned from a function. This is usually a bad idea, but it
was not flagged by the compiler until a recent addition that pushed
it over the 1024 byte function stack limit:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_translation_helper.c: In function 'populate_dml_plane_cfg_from_plane_state':
drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml2_translation_helper.c:1075:1: error: the frame size of 1032 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
Use an explicit kzalloc() and memcpy() instead here to keep it off the
stack.
Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Fixes: 7966f319c66d ("drm/amd/display: Introduce DML2") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arnd Bergmann [Tue, 28 May 2024 11:51:20 +0000 (13:51 +0200)]
drm/amd/display: avoid large on-stack structures
Putting excessively large objects on a function stack causes
a warning about possibly overflowing the 8KiB of kernel stack:
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c: In function 'dcn401_update_bw_bounding_box':
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn401/dcn401_resource.c:1599:1: error: the frame size of 1196 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
1599 | }
| ^
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c: In function 'dc_state_create':
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:221:1: error: the frame size of 1196 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
221 | }
| ^
Use dynamic allocation instead.
Fixes: e779f4587f61 ("drm/amd/display: Add handling for DC power mode") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arnd Bergmann [Tue, 28 May 2024 11:51:19 +0000 (13:51 +0200)]
drm/amd/display: fix graphics_object_id size
The graphics_object_id structure is meant to fit into 32 bits, as it's
passed by value in and out of functions. A recent change increased
the size to 128 bits, so it's now always passed by reference, which
is clearly not intended and ends up producing a compile-time warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c: In function 'construct_phy':
drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:743:1: error: the frame size of 1040 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
Add back the bitfields to revert to the original size, while keeping
the 'enum' type change.
Fixes: fec85f995a4b ("drm/amd/display: Fix compiler redefinition warnings for certain configs") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This structure is too large to fit on a stack, as shown by the
newly introduced warnings from a recent code change:
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn32/dcn32_resource.c: In function 'dcn32_update_bw_bounding_box':
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn32/dcn32_resource.c:2019:1: error: the frame size of 1180 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn321/dcn321_resource.c: In function 'dcn321_update_bw_bounding_box':
drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn321/dcn321_resource.c:1597:1: error: the frame size of 1180 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c: In function 'dc_state_create':
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:219:1: error: the frame size of 1184 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
Instead of open-coding the assignment of a large structure to a stack
variable, use an explicit kmemdup() in each case to move it off the stack.
Fixes: e779f4587f61 ("drm/amd/display: Add handling for DC power mode") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bruno Rocha Levi [Tue, 28 May 2024 13:08:04 +0000 (10:08 -0300)]
drivers/gpu: Fix misalignment in comment block
This patch fixes a warning from checkpatch by ensuring the trailing */ is
aligned with the rest of the *, improving readability.
Co-developed-by: Lucas Antonio <lucasantonio.santos@usp.br> Signed-off-by: Lucas Antonio <lucasantonio.santos@usp.br> Signed-off-by: Bruno Rocha Levi <brunolevilevi@usp.br> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Newer assemblers reject S_WAITCNT. All instances of S_WAITCNT can be
replaced by S_WAITCNT 0 (< gfx12) or S_WAIT_IDLE (>= gfx12) since
there is no concurrency of different memory instruction classes.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Thu, 23 May 2024 13:55:44 +0000 (08:55 -0500)]
drm/amdkfd: Sync trap handler binary with source
Source and binary have become mismatched during branch activity.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Reviewed-by: Lancelot Six <lancelot.six@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Fix shutdown (again) on some SMU v13.0.4/11 platforms
commit cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown for
some SMU 13.0.4/13.0.11 users") attempted to fix shutdown issues
that were reported since commit 31729e8c21ec ("drm/amd/pm: fixes a
random hang in S4 for SMU v13.0.4/11") but caused issues for some
people.
Adjust the workaround flow to properly only apply in the S4 case:
-> For shutdown go through SMU_MSG_PrepareMp1ForUnload
-> For S4 go through SMU_MSG_GfxDeviceDriverReset and
SMU_MSG_PrepareMp1ForUnload
Reported-and-tested-by: lectrode <electrodexsnet@gmail.com> Closes: https://github.com/void-linux/void-packages/issues/50417 Cc: stable@vger.kernel.org Fixes: cd94d1b182d2 ("dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users") Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
On GFXIP9.4.3, make CPX mode as the default compute mode if the node is
setup in NPS4 memory partition mode. This change is only applicable for
dGPU, for APU, continue to use TPX mode.
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Skvortsov [Mon, 27 May 2024 20:10:43 +0000 (16:10 -0400)]
drm/amdgpu: Add lock around VF RLCG interface
flush_gpu_tlb may be called from another thread while
device_gpu_recover is running.
Both of these threads access registers through the VF
RLCG interface during VF Full Access. Add a lock around this interface
to prevent race conditions between these threads.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 22 May 2024 19:26:50 +0000 (15:26 -0400)]
drm/amdkfd: simplify APU VRAM handling
With commit 89773b85599a
("drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs")
big and small APU "VRAM" handling in KFD was unified. Since AMD_IS_APU
is set for both big and small APUs, we can simplify the checks in
the code.
v2: clean up a few more places (Lang)
Acked-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Tue, 14 May 2024 00:17:00 +0000 (00:17 +0000)]
drm/amd/display: Fix null pointer dereference for dcn401
When ODM slice happens on DCN401, there is a null pointer exception
caused by that. This commit address this issue by checking if the
required data structures are initialized.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
All the DC_FP_START/END should be used before call anything from DML2,
for this reason, the use of those guards inside DML it is not correct.
This commit removes two unnecessary DC_FP_START/END from a dml2
function.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 13 May 2024 23:31:10 +0000 (19:31 -0400)]
drm/amd/display: Use DCN 410 includes for DCN401
DCN401 is using DCN 320 headers, which does not have all the right
registers for DCN401. This commit just replace DCN320 includes with the
one from DCN410.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Most of the DML code is generated, and it is necessary to update some
parts of it from time to time. This commit brings the latest generated
code for DML 2.1.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Fri, 26 Apr 2024 16:17:26 +0000 (12:17 -0400)]
drm/amd/display: Enable ISHARP support for DCN401
[Why]
Enable sharpener support for DCN401
[How]
- Removed memcmp check that was preventing ISHARP from being enabled.
- Add missing ISHARP register defines, masks, and writes.
- Add programming of Blur and Scale coefficients.
- Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel
- format
- Only enable ISHARP for YUV420
- Add disabling of ISHARP
- Add debug flags and registry keys for debugging ISHARP.
- Set default to medium level
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Mon, 27 May 2024 07:40:38 +0000 (15:40 +0800)]
drm/amdgpu: fix typo in amdgpu_ras_aca_sysfs_read() function
fix typo "info.ue_count" in amdgpu_ras_aca_sysfs_read() function.
Fixes: 865d3397630b ("drm/amdgpu: add aca deferred error type support") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jesse Zhang [Thu, 23 May 2024 09:14:45 +0000 (17:14 +0800)]
drm/amdgpu: fix dereference null return value for the function amdgpu_vm_pt_parent
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent.
To make the code more robust, check the pointer parent.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 2 May 2024 20:50:39 +0000 (16:50 -0400)]
drm/amdgpu: drop MES 10.1 support v3
It was an enablement vehicle for MES 11 and was never
productized. Remove it.
v2: drop additional checks in the GFX10 code.
v3: drop mes_api_def.h
Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / thirdparty / kernel / linux.git / log
