Since SVE has support for an FSCALE instruction, we can use this to process
scalar floats by moving them to a vector register and performing an fscale call,
similar to how LLVM tackles an ldexp builtin as well.
This is a revision of an earlier patch, and now uses the extended definition of
aarch64_ptrue_reg to generate predicate registers with the appropriate set bits.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Soumya AR <soumyaa@nvidia.com>
gcc/ChangeLog:
PR target/111733
* config/aarch64/aarch64-sve.md
(ldexp<mode>3): Added a new pattern to match ldexp calls with scalar
floating modes and expand to the existing pattern for FSCALE.
* config/aarch64/iterators.md:
(SVE_FULL_F_SCALAR): Added an iterator to match all FP SVE modes as well
as their scalar equivalents.
(VPRED): Extended the attribute to handle GPF_HF modes.
* internal-fn.def (LDEXP): Changed macro to incorporate ldexpf16.
xuli [Tue, 12 Nov 2024 02:31:28 +0000 (02:31 +0000)]
RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]
This patch fixs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117483
If prev and next satisfy the following rules, we should forbid the case
(next.get_sew() < prev.get_sew() && (!next.get_ta() || !next.get_ma()))
in the compatible function max_sew_overlap_and_next_ratio_valid_for_prev_sew_p.
Otherwise, the tail elements of next will be polluted.
Xianmiao Qu [Wed, 13 Nov 2024 04:03:24 +0000 (21:03 -0700)]
[RISC-V] Fix costing of LO_SUM expressions
This is a rewrite of a patch originally from Xianmiao Qu. Xianmiao
noticed that the costs we compute for LO_SUM expressions was incorrect.
Essentially we costed based solely on the first input to the LO_SUM.
In a LO_SUM, the first input is almost always going to be a REG and thus
isn't interesting. The second argument is almost always going to be
some kind of symbolic operand, which is much more interesting from a
costing standpoint.
The right way to fix this is to sum the cost of the two operands. I've
verified this produces the same code as Xianmiao's Qu's original patch.
This has been tested on rv32 and rv64 in my tester. It missed today's
bootstrap of riscv64 though :( Naturally I'll wait on the pre-commit CI
tester to render a verdict, but I don't expect any problems.
-- From Xianmiao Qu's original submission --
Currently, the cost of the LO_SUM expression is based on
the cost of calculating the first subexpression. When the
first subexpression is a register, the cost result will
be zero. It seems a bit unreasonable for a SET expression
to have a zero cost when its source is LO_SUM. Moreover,
having a cost of zero for the expression will lead the
loop invariant pass to calculate its benefits of being
moved outside the loop as zero, thus preventing the
out-of-loop placement of the loop invariant.
As an example, consider the following test case:
long a;
long b[];
long *c;
foo () {
for (;;)
*c = b[a];
}
When compiling with -march=rv64gc -mabi=lp64d -Os, the following code is
generated:
.cfi_startproc
lui a5,%hi(c)
ld a4,%lo(c)(a5)
lui a2,%hi(b)
lui a1,%hi(a)
.L2:
ld a5,%lo(a)(a1)
addi a3,a2,%lo(b)
slli a5,a5,3
add a5,a5,a3
ld a5,0(a5)
sd a5,0(a4)
j .L2
After adjust the cost of the LO_SUM expression, the instruction addi will be
moved outside the loop:
.cfi_startproc
lui a5,%hi(c)
ld a3,%lo(c)(a5)
lui a4,%hi(b)
lui a2,%hi(a)
addi a4,a4,%lo(b)
.L2:
ld a5,%lo(a)(a2)
slli a5,a5,3
add a5,a5,a4
ld a5,0(a5)
sd a5,0(a3)
j .L2
gcc/
* config/riscv/riscv.cc (riscv_rtx_costs): Correct costing of LO_SUM
expressions.
Yangyu Chen [Tue, 12 Nov 2024 23:50:03 +0000 (16:50 -0700)]
RISC-V: Fix target-attr-norelax.c testcase
The target-attr-norelax.c testcase was failing due to the redundant "\t"
check in the assembly output, and forgot to skip the check for lto build
in the testcase.
Since r15-4981-g5c34f02ba7e these tests have been failing on vector
targets with excess errors due to the new deprecation warning message.
Remove the <cstdalign> header.
Andrew Carlotti [Fri, 1 Nov 2024 17:27:38 +0000 (17:27 +0000)]
testsuite: Adjust jump threading test expectation
This test started failing on aarch64 after 0cfc9c95 in 2023 ("Phi
analyzer - Initialize with range instead of a tree.").
The only change visible in the pass dumps prior to thread2 is the upper
bounds of some ranges are reduced from +INF to 7, consistent with the
bitamsk information. After thread2, there are changes in the control
flow, but only affecting edges that are obviously never taken (from
basic blocks 6 through 12). These are cleaned up in the following pass,
but the final codegen remains different.
There isn't anything obviously wrong with the change in dump output, so
let's just update the test expectations (as has happened previously
here).
Wilco Dijkstra [Mon, 7 Oct 2024 15:42:49 +0000 (15:42 +0000)]
AArch64: Remove duplicated addr_cost tables
Remove duplicated addr_cost tables - use generic_armv9_a_addrcost_table for
Armv9-a cores and generic_armv8_a_addrcost_table for recent Armv8-a cores.
No changes in generated code.
Wilco Dijkstra [Wed, 2 Oct 2024 16:34:41 +0000 (16:34 +0000)]
AArch64: Cleanup fusion defines
Cleanup the fusion defines by introducing AARCH64_FUSE_BASE as a common base
level of fusion supported by almost all cores. Add AARCH64_FUSE_MOVK as a
shortcut for all MOVK fusion. In most cases there is no change. It enables
AARCH64_FUSE_CMP_BRANCH for a few older cores since it has no measurable
effect if a core doesn't support it. Also it may have been accidentally
left out on some cores that support all other types of branch fusion.
Pan Li [Tue, 24 Sep 2024 02:22:07 +0000 (10:22 +0800)]
RISC-V: Fix incorrect test macro for signed scalar SAT_ADD form 2 run test
This patch would like to fix one incorrect test macro usage for
form 2 of signed scalar SAT_ADD run test. It should leverage the
_FMT_2 instead of _FMT_1 for form 2.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macro.
* gcc.target/riscv/sat_s_add-run-5.c: Take form 2 for run test.
* gcc.target/riscv/sat_s_add-run-6.c: Ditto.
* gcc.target/riscv/sat_s_add-run-7.c: Ditto.
* gcc.target/riscv/sat_s_add-run-8.c: Ditto.
Jeff Law [Tue, 12 Nov 2024 14:05:02 +0000 (07:05 -0700)]
[RISC-V] Drop undesirable two instruction macc alternatives
So I was looking at sub_dct a little while ago and was surprised to see
us emit two instructions out of a single pattern. We generally try to
avoid that -- it's not always possible, but as a general rule of thumb
it should be avoided. Specifically I saw:
When we emit multiple instructions out of a single pattern we can't
build a good schedule as we can't really describe the two instructions
well and we can't split them up -- they move as an atomic unit.
These cases can also raise correctness issues if the pattern doesn't
properly account for both instructions in its length computation.
Note the length, 4 bytes. So this is both a performance and latent
correctness issue.
It appears that these alternatives are meant to deal with the case when
we have three source inputs and a non-matching output. The author did
put in "?" to slightly disparage these alternatives, but a "!" would
have been better. The best solution is to just remove those
alternatives and let the allocator manage the matching operand issue.
That's precisely what this patch does. For the various integer
multiply-add/multiply-accumulate patterns we drop the alternatives which
don't require a match between the output and one of the inputs.
That fixes the correctness issue and should shave a cycle or two off our
sub_dct code. Essentially the move bubbles up into an empty slot and we
can schedule around the vmacc sensibly.
Interestingly enough this fixes a scan-assembler test in my tester for
both rv32 and rv64.
My BPI is already in a bootstrap test, so this patch won't hit the BPI
for bootstrapping until Wednesday, meaning no data until Thursday. Will
wait for the pre-commit tester though.
gcc/
* config/riscv/vector.md (pred_mul_plus<mode>_undef): Drop alternatives
where output doesn't have to match input.
(pred_madd<mode>, pred_macc<mode>): Likewise.
(pred_madd<mode>_scalar, pred_macc<mode>_scalar): Likewise.
(pred_madd<mode>_exended_scalar): Likewise.
(pred_macc<mode>_exended_scalar): Likewise.
(pred_minus_mul<mode>_undef): Likewise.
(pred_nmsub<mode>, pred_nmsac<mode>): Likewise.
(pred_nmsub<mode>_scalar, pred_nmsac<mode>_scalar): Likewise.
(pred_nmsub<mode>_exended_scalar): Likewise.
(pred_nmsac<mode>_exended_scalar): Likewise.
Richard Biener [Tue, 12 Nov 2024 09:31:30 +0000 (10:31 +0100)]
tree-optimization/116973 - SLP permute lower heuristic and single-lane SLP
When forcing single-lane SLP to emulate non-SLP behavior we need to
disable heuristics designed to optimize SLP loads and instead in
all cases resort to an interleaving scheme as requested by forcefully
doing single-lane SLP.
This fixes the remaining fallout for --param vect-force-slp=1 on x86.
PR tree-optimization/116973
* tree-vect-slp.cc (vect_lower_load_permutations): Add
force_single_lane parameter. Disable heuristic that keeps
some load-permutations.
(vect_analyze_slp): Pass force_single_lane to
vect_lower_load_permutations.
Kito Cheng [Wed, 6 Nov 2024 09:35:46 +0000 (17:35 +0800)]
libsanitizer: Improve FrameIsInternal
`FrameIsInternal` is a function that improves report quality by filtering out
internal functions from the sanitizer, allowing it to point to a more precise
root cause. However, the current checks are mostly specific to compiler-rt,
so we are adding a few more rules to enhance the filtering for libsanitizer as
well.
Jeff Law [Tue, 12 Nov 2024 13:15:50 +0000 (06:15 -0700)]
[committed] Fix minor c6x backend bug exposed by CRC patches
This is a minor bug in the c6x port I saw when testing Mariam's CRC work.
Specifically some of the CRC tests were failing with a segfault testing if an
operand was an "a_register" from within the dest_regfile attribute. We were
extracting what we thought should have been a register operand then looking at
the REGNO. The underlying data was totally bogus, hence the fault in the
accessor macros.
The core issue is we were trying to extract operands from a nop insn which has
no operands. As far as I can tell "unknown" is a reasonable answer for the
dest_regfile attribute on a nop insn, so this patch adds an explicit setting of
dest_regfile rather than letting the default processing kick in.
I'm applying the attached patch to the trunk.
There's still a backend bug affecting ~15 CRC tests. Essentially the assembler
complains about a label (related to debugging info) not at the start of an
execution packet. I'm not chasing this down.
squirek [Wed, 30 Oct 2024 16:33:29 +0000 (16:33 +0000)]
ada: Compile time crash on limited object in extended return
This patch fixes an error in the compiler whereby using an extended return on
an object of limited tagged type which extends a tagged protected type may lead
to a compile-time crash.
gcc/ada/ChangeLog:
* exp_ch3.adb (Build_Assignment): Add condition to fetch corresponding
record types for concurrent tagged types.
Eric Botcazou [Wed, 30 Oct 2024 10:22:12 +0000 (11:22 +0100)]
ada: Fix spurious error on iterated component association with large index type
This is only for the Ada 2022 form of the iterated component association.
gcc/ada/ChangeLog:
* exp_aggr.adb (Two_Pass_Aggregate_Expansion): Use a type sized
from the index type to compute the length. Simplify and remove
useless calls to New_Copy_Tree for this computation.
Pat Bernardi [Mon, 18 Jul 2022 05:56:28 +0000 (01:56 -0400)]
ada: Include design documentation within runtime sources
The existing design documentation, required when generating the Software
Architecture Design Specification and Software Component Design
Specification documents for the light and light-tasking runtimes, has been
included directly within runtime sources.
Eric Botcazou [Tue, 29 Oct 2024 12:14:16 +0000 (13:14 +0100)]
ada: Make sure not to access past the end of bit-packed arrays
The code generated for the routines of the run-time library that implement
support for bit-packed arrays with non-power-of-2 component sizes turns out
to be problematic for the Address Sanitizer and the CHERI architecture, as
it may access past the end of bit-packed arrays in specific cases.
Eric Botcazou [Fri, 25 Oct 2024 19:16:14 +0000 (21:16 +0200)]
ada: Get rid of N_Unchecked_Expression node
This node is used in a single place in the front-end: it wraps the newly
built N_Indexed_Component nodes on the left-hand side of assignments
generated to elaborate array aggregates, and its effect is to disable
range checks for the expressions of these nodes.
Most of the code in the front-end does not expect to encounter it at all,
which leads to weird effects when this actually happens after changes are
made to the processing of array aggregates.
This change replaces the node by the Kill_Range_Check flag already present
on N_Unchecked_Type_Conversion, but with a slightly adjusted semantics.
gcc/ada/ChangeLog:
* exp_aggr.adb (Build_Array_Aggr_Code.Gen_Assign): Do not call
Checks_Off on the newly built N_Indexed_Component node but instead
set Kill_Range_Check on it.
* exp_ch4.ads (Expand_N_Unchecked_Expression): Delete.
* exp_ch4.adb (Expand_N_Indexed_Component): Remove handling of
N_Unchecked_Expression.
(Expand_N_Unchecked_Expression): Delete.
(Expand_N_Unchecked_Type_Conversion): Propagate the Assignment_OK
flag and rewrite the node manually.
* exp_util.adb (Insert_Actions): Remove handling of
N_Unchecked_Expression.
(Side_Effect_Free): Likewise.
* expander.adb (Expand): Likewise.
* gen_il-gen-gen_nodes.adb (N_Indexed_Component): Add flag
Kill_Range_Check for the purpose of semantics.
(N_Unchecked_Expression): Delete.
* gen_il-internals.ads (Type_Frequency): Remove entry for
N_Unchecked_Expression.
* gen_il-types.ads (Opt_Type_Enum): Remove N_Unchecked_Expression.
* pprint.adb (Expression_Image): Remove handling of
N_Unchecked_Expression.
* sem.adb (Analyze): Likewise.
* sem_ch4.ads (Analyze_Unchecked_Expression): Delete.
* sem_ch4.adb (Analyze_Unchecked_Expression): Likewise.
* sem_res.adb (Resolve_Unchecked_Expression): Likewise.
(Resolve): Remove handling of N_Unchecked_Expression.
(Resolve_Indexed_Component): Do not call Apply_Scalar_Range_Check
on the expressions if Kill_Range_Check is set on the node.
* sem_util.adb (Is_Non_Preelaborable_Construct): Remove handling of
N_Unchecked_Expression.
* sinfo.ads (Kill_Range_Check): Document it for N_Indexed_Component.
(Unchecked Expression): Delete specification.
* sprint.adb (Sprint_Node_Actual): Remove handling of
N_Unchecked_Expression.
* tbuild.ads (Checks_Off): Delete.
* tbuild.adb (Checks_Off): Likewise.
Eric Botcazou [Mon, 28 Oct 2024 10:28:53 +0000 (11:28 +0100)]
ada: Fix unexpected Program_Error raised in the parser on mismatched []
This happens for example with:
A : constant array (Natural range <>) of String := [ "xor" [;
The problem is that the left bracket token is incorrectly classified as
a name extension, but there is no handler in the Scan_Name_Extension_OK
part of P_Name in Par.Ch4.
gcc/ada/ChangeLog:
PR ada/112821
* scans.ads (Token_Type): Remove Tok_Left_Bracket from Namext.
Eric Botcazou [Mon, 28 Oct 2024 08:13:33 +0000 (09:13 +0100)]
ada: Fix internal error on instantiation of package with a nested ghost package
The instantiation triggers an internal error in Gigi because of a dangling
ghost entity created by the finalization machinery.
gcc/ada/ChangeLog:
PR ada/114300
* exp_ch7.adb (Attach_Object_To_Master_Node): Propagate the
Is_Ignored_Ghost_Entity flag from the finalization procedure.
(Build_Finalizer.Process_Declarations): Move up the test on
Is_Ignored_Ghost_Entity.
* exp_util.adb (Requires_Cleanup_Actions): Likewise.
Eric Botcazou [Mon, 28 Oct 2024 07:33:49 +0000 (08:33 +0100)]
ada: Fix premature finalization of anonymous access result from library function
In GNAT's implementation, the finalization of controlled objects created
through anonymous access types occurs when the enclosing library unit goes
out of scope if this is safe, and never occurs otherwise.
The case of a function that is a library unit with an anonymous access
result type falls in the second category for the anonymous access result
type itself and, therefore, finalization cannot take place for it.
gcc/ada/ChangeLog:
PR ada/55725
* exp_ch6.adb (Add_Collection_Actual_To_Build_In_Place_Call): Be
prepared for no collection if the access type is anonymous.
* exp_ch7.adb (Build_Anonymous_Collection): Return early for the
anonymous access result type of a library function.
Piotr Trojanek [Mon, 28 Oct 2024 12:17:03 +0000 (13:17 +0100)]
ada: Accept SPARK.Big_Integers.Big_Integer where Big_Integer is accepted
For certification of a light SPARK runtime libraries we now accept
expressions of type SPARK.Big_Integers.Big_Integer in subprogram and
loop variants.
gcc/ada/ChangeLog:
* exp_util.adb (Make_Variant_Comparison): Accept new types in
expansion.
* rtsfind.adb (Get_Unit_Name): Support SPARK.Big_Integers.
* rtsfind.ads (RTU_Id, RE_Id, RE_Unit_Table): Support new type
and its enclosing unit.
* sem_prag.adb (Analyze_Pragma): Support new type in pragma
Loop_Variant.
(Analyze_Subprogram_Variant_In_Decl_Part): Support new type in
aspect Subprogram_Variant.
ada: Make Interrupt and Attach Handlers Obsolescent in VXWorks
In order to trigger an obsolescent feature warning in
VXWorks if either the pragma or aspect of Interrupt_Handler
or Attach_Handler is used, the spec of the Register_Interrupt_Handler
method needs to be marked as obsolescent in a VXWorks specific
version of the file.
gcc/ada/ChangeLog:
* libgnarl/s-interr__vxworks.ads (new): A VXWorks specific
version of the file where Register_Interrupt_Handler is marked
with the Obsolescent pragma.
* libgnarl/s-interr__vxworks.adb: Remove pragma Obsoloescent
that had no effect.
* Makefile.rtl: Add entries for using the
libgnarl/s-interr__vxworks.ads file.
Eric Botcazou [Mon, 28 Oct 2024 06:42:54 +0000 (07:42 +0100)]
ada: Remove couple of irregular calls to Resolve_Aggr_Expr
The function is supposed to be passed an expression, but it is passed the
enclosing N_Component_Association node in a couple of cases, only to give
an error that can as well be given in the caller, at the cost of bypasses
to disable most of its processing.
gcc/ada/ChangeLog:
* sem_aggr.adb (Resolve_Array_Aggregate): In the case of an others
choice with a box, do not call Resolve_Aggr_Exp and give the error
for a multidimensional array directly.
(Resolve_Aggr_Expr): Remove bypasses for above case.
Before this patch, it was never allowed to use pragma Source_File_Name
for the spec of System, allegedly because Targparm.Get_Target_Parameters
is called before configuration pragmas are processed. Using a mapping
file was allowed but did not work correctly.
This patch makes mapping files loading happen before the call to
Get_Target_Parameters so mapping file can set the file name of System.
Also, pragma Source_File_Name is allowed if it confirms a mapping that
was previously given in a mapping file, to accommodate GPRbuild that
uses both pragmas and mapping files.
gcc/ada/ChangeLog:
* frontend.adb (Frontend): Move call to Fmap.Initialize ...
* gnat1drv.adb (Gnat1drv): ... here. Look up Fmap when loading System.
* par-prag.adb (Prag): Allow pragma Source_File_Name for System when
it confirms an existing mapping.
Eric Botcazou [Thu, 24 Oct 2024 17:20:30 +0000 (19:20 +0200)]
ada: Get rid of Kill_Range_Checks flag on entities
This flag is set in a single context, namely semantic analysis of record
type definitions, to avoid generating spurious range checks from it, and
a large testing campaign showed that, in practice, it makes a difference
in a single case, namely an access-to-constrained-array component with a
default expression, for example:
type Acc_String is access all String (1 .. 100);
type Rec (D : Positive) is record
A : Acc_String := new String (1 .. D);
end record;
Now there is another mechanism implemented in Process_Range_Expr_In_Decl to
avoid generating spurious range checks, which does not work in this specific
case but can be made to work with a small tweak to Denotes_Discriminant.
gcc/ada/ChangeLog:
* checks.adb (Range_Checks_Suppressed): Remove test on the
Kill_Range_Checks flag.
* einfo.ads (Kill_Range_Checks): Delete.
* gen_il-fields.ads (Opt_Field_Enum): Remove Kill_Range_Checks.
* gen_il-gen-gen_entities.adb (Entity_Kind): Likewise.
* sem_ch3.adb (Record_Type_Declaration): Do not set the
Kill_Range_Checks flag.
* sem_util.adb (Denotes_Discriminant): In a default expression,
also return True for a discriminal.
Steve Baird [Tue, 22 Oct 2024 23:20:27 +0000 (16:20 -0700)]
ada: Improve message for misused implicitly-defined preprocessor symbol.
If the -u option is specified, then otherwise-undefined preprocessor
symbols are implicitly defined to be False. If such an implicitly-defined
symbol is then incorrectly used in a context that requires an integer value,
the resulting error message should not incorrectly state that the symbol is
undefined.
gcc/ada/ChangeLog:
* prep.adb (Expression): Improve error message text when an
implicitly-defined Boolean-valued symbol is used in a context that
requires an integer value.
The predicate is passed an aggregate node and goes up its parent chain,
but that's unnecessary because Convert_To_Assignments has already done
so in the case of a record aggregate and Expand_Array_Aggregate does not
fully support intermediate conditional expressions yet.
gcc/ada/ChangeLog:
* exp_aggr.adb (Is_Build_In_Place_Aggregate_Return): Directly test
the node and remove dead code for extended return statements.
ada: Set correct minimum stack size for aarch64-linux
The minimum stack size defined by PTHREAD_STACK_MIN defined on
AArch64 Linux is 131072 bytes. Add a separate version for this
target to reflect that value. Previously the x86-64 value of 16384
bytes was used.
gcc/ada/ChangeLog:
* Makefile.rtl: Use libgnat/s-parame__aarch64-linux.adb for
s-parame.adb on aarch64-linux.
* libgnat/s-parame__aarch64-linux.adb: Add file.
Piotr Trojanek [Thu, 24 Oct 2024 08:47:09 +0000 (10:47 +0200)]
ada: Detect sharing of external file in inconsistent read-write modes
When opening files with "shared=yes", as described in GNAT RM 11.10,
Sharing Files, we now prevent sharing a single file in inconsistent
read-write modes.
gcc/ada/ChangeLog:
* doc/gnat_rm/the_implementation_of_standard_i_o.rst
(Shared Files): Add trailing period.
* libgnat/s-ficobl.ads (AFCB): Reflect new behavior in comment.
* libgnat/s-fileio.adb (Open): Detect inconsistent sharing,
just like we do in System.File_IO.Reset.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
squirek [Tue, 13 Aug 2024 12:06:52 +0000 (12:06 +0000)]
ada: Spurious error on abstract primitive with access formals
This patch fixes an issue in the compiler whereby using anonymous access
types as abstract overridden subprogram formals for a derived abtract type
may lead to compile-time errors.
gcc/ada/ChangeLog:
* accessibility.adb (Type_Access_Level): Add handling for
subprogram aliases.
squirek [Tue, 13 Aug 2024 11:35:06 +0000 (11:35 +0000)]
ada: Missing runtime tag check on mutably tagged objects
This patch fixes an issue in the compiler whereby assigning to a non-existant
mutably tagged object component failed to result in the expected run-time
exception.
gcc/ada/ChangeLog:
* exp_ch4.adb (Expand_N_Type_Conversion): Add special runtime check
generation for mutably tagged objects.
Douglas B Rupp [Wed, 9 Oct 2024 19:44:16 +0000 (12:44 -0700)]
ada: GNAT Calendar Support for 64-bit Unix Time
The Epochalypse of 2038 will require the use of 64-bit time_t and
tv_sec (aka time in seconds from the Unix Epoch). The subprograms
in Ada calendar are self contained but nevertheless will malfunction
if a 64-bit integer type and calculations aren't used. Add 64-bit
versions and mark the old ones with pragma Obsolescent.
gcc/ada/ChangeLog:
* libgnat/a-calcon.adb (To_Ada_Time) (To_Duration)
(To_Struct_Timespec) (To_Unix_Time): Mark as obsolescent.
(To_Ada_Time_64) (To_Duration_64) (To_Struct_Timespec_64)
(To_Unix_Time_64): New.
* libgnat/a-calcon.ads (To_Ada_Time) (To_Duration)
(To_Struct_Timespec) (To_Unix_Time): Mark as obsolescent.
(To_Ada_Time_64) (To_Duration_64) (To_Struct_Timespec_64)
(To_Unix_Time_64): New.
* libgnat/a-calend.adb (To_Ada_Time) (To_Duration)
(To_Struct_Timespec) (To_Unix_Time): Mark as obsolescent.
(To_Ada_Time_64) (To_Duration_64) (To_Struct_Timespec_64)
(To_Unix_Time_64): New.
* libgnat/a-calend.ads (To_Ada_Time) (To_Duration)
(To_Struct_Timespec) (To_Unix_Time): Mark as obsolescent.
(To_Ada_Time_64) (To_Duration_64) (To_Struct_Timespec_64)
(To_Unix_Time_64): New.
Eric Botcazou [Wed, 23 Oct 2024 07:42:25 +0000 (09:42 +0200)]
ada: Fix internal error on nested iterated component associations
The problem is that Insert_Actions gets confused as to where it should
insert actions coming from within an N_Iterated_Component_Association,
because some actions may be generated during semantic analysis and some
others during expansion.
Instead of another ad-hoc fix, this change extends the processing done
for N_Component_Association, that is to say waiting for the Loop_Actions
field to be set during expansion before inserting actions in there.
This in turn requires semantic analysis to stop generating actions for
N_Iterated_Component_Association nodes. The current processing is a
little unstable:
- for container aggregates, Resolve_Iterated_Association preanalyzes
a copy of the expression,
- for delta aggregates, Resolve_Delta_Array_Aggregate fully analyzes
a copy of the expression,
- for array aggregate, Resolve_Aggr_Expr entirely skips the analysis.
The change implements a preanalysis of a copy of the expression using
Copy_Separate_Tree, which should be sufficient since the expression is
supposed to be unanalyzed at this point, recursively in the context of
N_Iterated_Component_Association nodes.
gcc/ada/ChangeLog:
PR ada/117018
* exp_aggr.adb (Build_Array_Aggr_Code): Do not expect the
Loop_Actions field to be already present on association nodes.
* exp_util.adb (Insert_Actions): For association nodes, insert
into the Loop_Actions field only if it is already present.
* sem_aggr.adb (Resolve_Array_Aggregate): Add Iterated parameter.
(Resolve_Aggregate): Adjust calls to Resolve_Array_Aggregate.
(Resolve_Aggr_Expr): Add Iterated_Elmt defaulted parameter and
a default for Single_Elmt. Adjust call to Resolve_Array_Aggregate.
Preanalyze a copy of the expression in an iteration context.
(Resolve_Iterated_Component_Association): Pass Iterated_Elmt as
True to Resolve_Aggr_Expr and remove processing of Loop_Actions.
Do not check incorrect use of dynamically tagged expression in
an iteration context.
(Resolve_Iterated_Association): Use Copy_Separate_Tree instead of
New_Copy_Tree and set the Parent field of the result.
(Resolve_Delta_Array_Aggregate): Likewise. Only preanalyze the
copy instead of analyzing it.
Richard Kenner [Mon, 14 Oct 2024 20:55:27 +0000 (16:55 -0400)]
ada: Add documentation about GNAT LLVM to GNAT User's Guide
Also be consistent on spelling of "back end".
gcc/ada/ChangeLog:
* doc/gnat_ugn/about_this_guide.rst: Add information about GNAT LLVM.
Be consistent about spelling of "back end".
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Likewise.
* doc/gnat_ugn/gnat_and_program_execution.rst: Be consistent about
spelling of "back end".
* doc/gnat_ugn/the_gnat_compilation_model.rst: Likewise.
* gnat_ugn.texi: Regenerate.
The code has been simplified to use a single way to create a DLL.
The relocation support is based on whether the base address for the
DLL is passed to the final linker step or not.
gcc/ada/ChangeLog:
* mdll.adb: Use the same procedure to create relocatable or non
relocatable DLL. The only difference is wether the base address is
passed to the final linker. If no base-address is given the DLL is
relocatable.
squirek [Mon, 21 Oct 2024 18:21:13 +0000 (18:21 +0000)]
ada: The Library_Unit field was used for all sorts of different purposes, which led to confusing code.
This patch further refines the previous work to fix several cases.
gcc/ada/ChangeLog:
* inline.adb (In_Main_Unit_Or_Subunit): Use Other_Comp_Unit instead of
Spec_Or_Body_Lib_Unit.
(Must_Inline): Use Other_Comp_Unit instead of Spec_Or_Body_Lib_Unit.
Eric Botcazou [Mon, 21 Oct 2024 08:55:28 +0000 (10:55 +0200)]
ada: Elide the copy in aggregate returns for nonlimited types
This implements elision of the copy operation for aggregate returns, i.e.
simple return statements whose expression is an aggregate, in the case of
nonlimited by-reference types (the copy operation is already elided for
limited types), which comprise controlled and tagged types. This is the
copy operation in the called function, that is to say the copy from the
anonymous object built for the aggregate to the anonymous return object.
The implementation simply extends that of limited types, which rewrites
the simple return statement as an extended return statement internally
and then leverages the built-in-place implementation of return objects
for these statements.
gcc/ada/ChangeLog:
* exp_aggr.adb (Is_Build_In_Place_Aggregate_Return): Also return
True for functions returning on the secondary stack or returning
a by-reference type if the back end exposes its return slot.
(Expand_Array_Aggregate): Call Is_Build_In_Place_Aggregate_Return
to spot aggregates to be built in place.
* exp_ch3.adb (Make_Allocator_For_Return): Add missing condition
in assertion pragma deduced from Expand_Subtype_From_Expr.
* exp_ch6.adb (Expand_Simple_Function_Return): Rewrite the statement
as an extended return statement if the expression is an aggregate
whose expansion is delayed. Properly relocate the expression in
this case.
* sem_ch6.adb: Add clauses for Exp_Aggr.
(Analyze_Function_Return): Do not apply the predicate check to an
aggregate whose expansion is delayed. Extended the processing of
case expressions to all conditional expressions.
Eric Botcazou [Fri, 18 Oct 2024 10:06:23 +0000 (12:06 +0200)]
ada: Implement built-in-place expansion of container aggregates
It is implemented for container aggregates that are used to initialize an
object, as specified by RM 7.6(17.2/3-17.3/3) for immutably limited types
and types that need finalization, but for all types like other aggregates.
gcc/ada/ChangeLog:
* exp_aggr.adb (Expand_Delta_Array_Aggregate): Move declaration.
(Expand_Delta_Record_Aggregate): Likewise.
(Expand_Container_Aggregate): Likewise. Move implementation to
Build_Container_Aggr_Code. Implement built-in-place expansion
for object declarations and allocators.
(Build_Container_Aggr_Code): New function containing most of the
code of the original Expand_Container_Aggregate. Do not build a
temporary for the size calculation. Minor formatting tweaks.
(Expand_N_Aggregate): Add comment.
* exp_ch4.adb (Expand_Allocator_Expression): Detect the case of
a container aggregate as qualified expression. Do not apply the
predicate check on entry in this case and rewrite the allocator.
* exp_ch7.adb (Build_Finalizer.Process_Object_Declaration): Deal
with Last_Aggregate_Assignment first to compute the attachment
point (as already done in Attach_Object_To_Master_Node).
Eric Botcazou [Fri, 18 Oct 2024 07:28:17 +0000 (09:28 +0200)]
ada: Fix weird error in Ada.Numerics.Discrete_Random with Component_Alignment
The problem arises when an instance of Ada.Numerics.Discrete_Random is
covered by a pragma Component_Alignment with a non-default alignment.
gcc/ada/ChangeLog:
* exp_ch5.adb (Expand_Assign_Array): Make Act_Rhs a constant and
do not recompute it, as well as R_Type, when there is a change of
representation. Move comment about the RHS from here to...
(Expand_N_Assignment_Statement): ...here.
Richard Biener [Tue, 12 Nov 2024 10:15:15 +0000 (11:15 +0100)]
tree-optimization/117417 - ICE with complex load optimization
When we decompose a complex load only used as real and imaginary
parts we fail to honor IL constraints which are that a BIT_FIELD_REF
of register type should be outermost in a ref. The following
simply avoids the transform when the complex load has such a
BIT_FIELD_REF.
rtl: Validate subreg info when optimizing vec_select.
When optimizing for NOPs in case of overlapping regs in VEC_SELECT expressions,
validate subreg data before using simplify_subreg_regno. There is no real
SUBREG rtx here, but a pseudo subreg call to check if subregs are possible.
gcc/ChangeLog:
* rtlanal.cc (set_noop_p): Validate subreg constraints before checking
for overlapping regs using simplify_subreg_regno.
Richard Biener [Fri, 8 Nov 2024 10:17:22 +0000 (11:17 +0100)]
Add X86_TUNE_AVX512_TWO_EPILOGUES, enable for Zen4 and Zen5
The following adds X86_TUNE_AVX512_TWO_EPILOGUES tuning and directs the
vectorizer to produce both a vector AVX2 and SSE epilogue for AVX512
vectorized loops when set. The tuning is enabled by default for Zen4
and Zen5 where I benchmarked it to be overall positive on SPEC CPU 2017 both
in performance and overall code size. In particular it speeds up
525.x264_r which with only an AVX2 epilogue ends up in unvectorized code
at the moment.
* config/i386/i386.cc (ix86_vector_costs::finish_cost): Set
m_suggested_epilogue_mode according to X86_TUNE_AVX512_TWO_EPILOGUES.
* config/i386/x86-tune.def (X86_TUNE_AVX512_TWO_EPILOGUES): Add.
Enable for znver4 and znver5.
Richard Biener [Fri, 8 Nov 2024 10:12:06 +0000 (11:12 +0100)]
Add suggested_epilogue_mode to vector costs
The following enables targets to suggest the vector mode to be used
preferably for the epilogue of a vectorized loop. The patch also
enables more than one vectorized epilogue in case the target suggests
a vector mode for the epilogue of a vector epilogue.
* tree-vectorizer.h (vector_costs::suggested_epilogue_mode): New.
(vector_costs::m_suggested_epilogue_mode): Likewise.
(vector_costs::vector_costs): Initialize m_suggested_epilogue_mode.
* tree-vect-loop.cc (vect_analyze_loop): Honor the target
suggested prefered epilogue mode and support vector epilogues
of vector epilogues if requested.
Richard Biener [Fri, 8 Nov 2024 08:43:26 +0000 (09:43 +0100)]
tree-optimization/117484 - issue with SLP discovery of permuted .MASK_LOAD
When we do SLP discovery of a .MASK_LOAD for a dataref group with gaps
the discovery for the mask will have gaps as well and this was
unexpected in a few places. The following re-organizes things
slightly to accomodate for this.
PR tree-optimization/117484
* tree-vect-slp.cc (vect_build_slp_tree_2): Handle gaps in
mask discovery. Fix condition to release the load permutation.
(vect_lower_load_permutations): Assert we get no load
permutation for the unpermuted node.
* tree-vect-slp-patterns.cc (linear_loads_p): Properly identify
loads (without permutation).
(compatible_complex_nodes_p): Likewise.
* gcc.dg/vect/pr117484-1.c: New testcase.
* gcc.dg/vect/pr117484-2.c: Likewise.
where we now vectorize the loop with VNx4QI, I'll leave it to ARM folks
to investigate whether that's OK and to adjust the testcase or to see
where to adjust things to make the testcase not vectorized again. The
original fix for which the testcase was introduced is still efffective.
PR tree-optimization/117502
* tree-vect-stmts.cc (get_group_load_store_type): Also consider
VMAT_STRIDED_SLP when checking to use gather/scatter for
single-element interleaving access.
* tree-vect-loop.cc (update_epilogue_loop_vinfo): STMT_VINFO_STRIDED_P
can be classified as VMAT_GATHER_SCATTER, so update DR_REF for
those as well.
Jason Merrill [Mon, 14 Oct 2024 20:22:34 +0000 (16:22 -0400)]
c++: rename -fmodules-ts to -fmodules
The C++ modules support is not targeting the Modules TS, so it doesn't make
much sense to refer to the TS in the option name. But keep the old spelling
as an undocumented alias for now.
gcc/ChangeLog:
* doc/invoke.texi: Rename -fmodules-ts to -fmodules.
gcc/c-family/ChangeLog:
* c.opt: Add -fmodules with same effect as -fmodules-ts.
gcc/cp/ChangeLog:
* lang-specs.h: Check fmodules* instead of fmodules-ts.
Jason Merrill [Mon, 11 Nov 2024 02:42:48 +0000 (21:42 -0500)]
opts: fix narrowing warning
The init-list initialization of cl_deferred_option p had a couple of
narrowing warnings: first of opt_index from int to size_t and then of value
from HOST_WIDE_INT to int. Fixed by making the types more consistent.
gcc/ChangeLog:
* opts.h (cl_deferred_option::value): Change to HOST_WIDE_INT.
(set_option): Change opt_index parm to size_t.
* opts-common.cc (set_option): Likewise.
Simon Martin [Mon, 11 Nov 2024 19:22:32 +0000 (20:22 +0100)]
c++: Fix another crash with invalid new operators [PR117463]
Even though this PR is very close to PR117101, it's not addressed by the
fix I made through r15-4958-g5821f5c8c89a05 because cxx_placement_new_fn
has the very same issue as std_placement_new_fn_p used to have.
As suggested by Jason, this patch changes both functions so that
cxx_placement_new_fn leverages std_placement_new_fn_p which reduces code
duplication and fixes the PR.
PR c++/117463
gcc/cp/ChangeLog:
* constexpr.cc (cxx_placement_new_fn): Implement in terms of
std_placement_new_fn_p.
* cp-tree.h (std_placement_new_fn_p): Declare.
* init.cc (std_placement_new_fn_p): Add missing checks to ensure
that fndecl is a non-replaceable ::operator new.
Jakub Jelinek [Mon, 11 Nov 2024 18:54:32 +0000 (19:54 +0100)]
c++: Add __builtin_operator_{new,delete} support
clang++ adds __builtin_operator_{new,delete} builtins which as documented
work similarly to ::operator {new,delete}, except that it is an error
if the called ::operator {new,delete} is not a replaceable global operator
and allow optimizations which C++ normally allows just when those are used
from new/delete expressions https://eel.is/c++draft/expr.new#14
When using these builtins, the same optimizations can be done even when
using those builtins.
For GCC we note that in the CALL_FROM_NEW_OR_DELETE_P flag on CALL_EXPRs.
The following patch implements it as a C++ FE keyword (because passing
references through ... changes the argument and so BUILT_IN_FRONTEND
builtin can't be used), just attempts to call the ::operator {new,delete}
and if it isn't replaceable, diagnoses it.
libstdc++ already uses the builtin in some cases.
2024-11-11 Jakub Jelinek <jakub@redhat.com>
gcc/c-family/
* c-common.h (enum rid): Add RID_BUILTIN_OPERATOR_NEW
and RID_BUILTIN_OPERATOR_DELETE.
(names_builtin_p): Change return type from bool to int.
* c-common.cc (c_common_reswords): Add __builtin_operator_new
and __builtin_operator_delete.
gcc/c/
* c-decl.cc (names_builtin_p): Change return type from
bool to int, adjust return statments.
gcc/cp/
* parser.cc (cp_parser_postfix_expression): Handle
RID_BUILTIN_OPERATOR_NEW and RID_BUILTIN_OPERATOR_DELETE.
* cp-objcp-common.cc (names_builtin_p): Change return type from
bool to int, adjust return statments. Handle
RID_BUILTIN_OPERATOR_NEW and RID_BUILTIN_OPERATOR_DELETE.
* pt.cc (tsubst_expr) <case CALL_EXPR>: Handle
CALL_FROM_NEW_OR_DELETE_P.
gcc/
* doc/extend.texi (New/Delete Builtins): Document
__builtin_operator_new and __builtin_operator_delete.
gcc/testsuite/
* g++.dg/ext/builtin-operator-new-1.C: New test.
* g++.dg/ext/builtin-operator-new-2.C: New test.
* g++.dg/ext/builtin-operator-new-3.C: New test.
Jonathan Wakely [Mon, 11 Nov 2024 11:54:00 +0000 (11:54 +0000)]
libstdc++: Fix typos in iterator increment for std::text_encoding [PR117520]
The intended behaviour for std::text_encoding::aliases_view's iterator
is that it incrementing or decrementing too far sets it to a
value-initialized state, or fails an assertion when those are enabled.
There were typos that used == instead of = which meant that instead of
becoming singular or aborting, an out-of-range increment just did
nothing. This meant erroneous operations were well-defined and didn't
produce any undefined behaviour, but were not diagnosed with assertions
enabled, as had been intended.
This change fixes the bugs and adds more tests to verify the intended
behaviour.
libstdc++-v3/ChangeLog:
PR libstdc++/117520
* include/std/text_encoding (aliases_view:_Iterator::operator+=):
Fix typos that caused == to be used instead of =.
(aliases_view::_Iterator): Fix friend declaration.
* testsuite/std/text_encoding/members.cc: Adjust expected
behaviour of invalid subscript. Add tests for other erroneous
operations on iterators.
Dimitar Dimitrov [Sun, 27 Oct 2024 07:49:49 +0000 (09:49 +0200)]
testsuite: Require atomic operations for c2y-if-decls-*
Since some of the c2y-if-decls tests use _Atomic, add a
requirement for target to support atomic operations on
int and long types.
This fixes spurious test link failures on pru-unknown-elf,
which lacks atomic ops. The tests still pass on x86_64-linux-gnu.
gcc/testsuite/ChangeLog:
* gcc.dg/c2y-if-decls-1.c: Require target that supports atomic
operations on int and long types.
* gcc.dg/c2y-if-decls-11.c: Ditto.
* gcc.dg/c2y-if-decls-4.c: Ditto.
* gcc.dg/c2y-if-decls-8.c: Ditto.
According to the aapcs64: If the argument is an 8-bit (...) precision
Floating-point or short vector type and the NSRN is less than 8, then the
argument is allocated to the least significant bits of register v[NSRN].
gcc/
* config/aarch64/aarch64.cc
(aarch64_vfp_is_call_or_return_candidate): use fp registers to
return svmfloat8_t parameters.
Jason Merrill [Tue, 5 Nov 2024 15:27:39 +0000 (10:27 -0500)]
c++: reduce unnecessary tree_common
Lewis' r15-5067 fixing the marking of TRAIT_EXPR led me to compare some
other front-end type definitions to their marking in cp_common_init_ts; it
seems we can change tree_common to something smaller in several cases, to
match how they are marked.
gcc/cp/ChangeLog:
* cp-tree.h (struct ptrmem_cst): Change tree_common to tree_typed.
(struct tree_trait_expr): Likewise.
(struct tree_static_assert): Change tree_common to tree_base.
(struct tree_argument_pack_select): Likewise.
Tobias Burnus [Mon, 11 Nov 2024 16:22:20 +0000 (17:22 +0100)]
libgomp.c-c++-common/pr109062.c: Fix expected spin count for hybrid x86
On my system with E and P cores (hybrid) x86, the spincount is by default 1
and not 300000, cf. PR109812 and r14-4571-ge1e127de18dbee.
Hence, this commit updates the expected value of the testcase to also
accept omp_display_env showing "GOMP_SPINCOUNT = '1'" - but only for
x86-64, which might be hybrid.
libgomp/ChangeLog:
* testsuite/libgomp.c-c++-common/pr109062.c: Update dg-output
to also accept GOMP_SPINCOUNT = 1 for x86-64.
Richard Biener [Fri, 8 Nov 2024 12:59:05 +0000 (13:59 +0100)]
Add missing SLP discovery for CFN[_MASK][_LEN]_SCATTER_STORE
This was responsible for a bunch of SVE FAILs with --param vect-force-slp=1
* tree-vect-slp.cc (arg1_arg3_map): New.
(arg1_arg3_arg4_map): Likewise.
(vect_get_operand_map): Handle IFN_SCATTER_STORE,
IFN_MASK_SCATTER_STORE and IFN_MASK_LEN_SCATTER_STORE.
(vect_build_slp_tree_1): Likewise.
* tree-vect-stmts.cc (vectorizable_store): For SLP masked
gather/scatter record the mask with proper number of copies.
* tree-vect-loop.cc (vectorizable_recurr): Avoid costing
the initial value construction in the prologue twice with SLP.
This patch adds the instructions that are new to FEAT_SVE2p1.
It mostly contains simple additions, so it didn't seem worth
splitting up further.
It's likely that we'll find more autovec uses for some of these
instructions, but for now this patch just deals with one obvious case:
using the new hybrid-VLA permutations to handle "stepped" versions of
some Advanced SIMD permutations. See aarch64_evpc_hvla for details.
The patch also continues the existing practice of lowering ACLE
permutation intrinsics to VEC_PERM_EXPR. That's admittedly a bit
inconsistent with the approach I've been advocating for when it comes
to arithmetic, but I think the difference is that (a) these are pure
data movement, and so there's limited scope for things like gimple
canonicalisations to mess with the instruction selection or operation
mix; and (b) there are no added UB rules to worry about.
Another new thing in the patch is the concept of "memory-only"
SVE vector modes. These are used to represent the memory operands
of the new LD1[DW] (to .Q), LD[234]Q, ST1[DW] (from .Q), and ST[234]Q
instructions. We continue to use .B, .H, .S, and .D modes for the
registers, since there's no predicated contiguous LD1Q instruction,
and since there's no arithmetic that can be done on TI. (The new
instructions are instead intended for hybrid VLA, i.e. for vectors
of vectors.)
For now, all of the new instructions are non-streaming-only.
Some of them are streaming-compatible with SME2p1, but that's
a later patch.
gcc/
* config/aarch64/aarch64-modes.def (VNx1SI, VNx1DI): New modes.
* config/aarch64/aarch64-sve-builtins-base.cc
(svdup_lane_impl::expand): Update generation of TBL instruction.
(svtbl_impl): Delete.
(svtbl): Use unspec_based_uncond_function instead.
* config/aarch64/aarch64-sve-builtins-functions.h
(permute::fold_permute): Handle trailing immediate arguments.
* config/aarch64/aarch64-sve-builtins-shapes.h (extq): Declare.
(load_gather64_sv_index, load_gather64_sv_offset): Likewise.
(load_gather64_vs_index, load_gather64_vs_offset): Likewise.
(pmov_from_vector, pmov_from_vector_lane, pmov_to_vector_lane)
(reduction_neonq, store_scatter64_index, store_scatter64_offset)
(unary_lane): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(load_gather64_sv_base, store_scatter64_base): New classes.
(extq_def, ext): New shape.
(load_gather64_sv_index_def, load_gather64_sv_index): Likewise.
(load_gather64_sv_offset_def, load_gather64_sv_offset): Likewise.
(load_gather64_vs_index_def, load_gather64_vs_index): Likewise.
(load_gather64_vs_offset_def, load_gather64_vs_offset): Likewise.
(pmov_from_vector_def, pmov_from_vector): Likewise.
(pmov_from_vector_lane_def, pmov_from_vector_lane): Likewise.
(pmov_to_vector_lane_def, pmov_to_vector_lane): Likewise.
(reduction_neonq_def, reduction_neonq): Likewise.
(store_scatter64_index_def, store_scatter64_index): Likewise.
(store_scatter64_offset_def, store_scatter64_offset): Likewise.
(unary_lane_def, unary_lane): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h (svaddqv, svandqv)
(svdup_laneq, sveorqv, svextq, svld1q_gather, svld1udq, svld1uwq)
(svld2q, svld3q, svld4q, svmaxnmqv, svmaxqv, svminnmqv, svminqv)
(svorqv, svpmov, svpmov_lane, svst1qd, svst1q_scatter, svst1wq)
(svst2q, svst3q, svst4q, svtblq, svtbx, svtbxq, svuzpq1, svuzpq2)
(svzipq1, svzipq2): Declare.
* config/aarch64/aarch64-sve-builtins-sve2.cc (ld1uxq_st1xq_base)
(ld234q_st234q_base, svdup_laneq_impl, svextq_impl): New classes.
(svld1q_gather_impl, svld1uxq_impl, svld234q_impl): Likewise.
(svpmov_impl, svpmov_lane_impl, svst1q_scatter_impl): Likewise.
(svst1xq_impl, svst234q_impl, svuzpq_impl, svzipq_impl): Likewise.
(svaddqv, svandqv, svdup_laneq, sveorqv, svextq, svld1q_gather)
(svld1udq, svld1uwq, svld2q, svld3q, svld4q, svmaxnmqv, svmaxqv)
(svminnmqv, svminqv, svorqv, svpmov, svpmov_lane, svst1qd)
(svst1q_scatter, svst1wq, svst2q, svst3q, svst4q, svtblq, svtbx)
(svtbxq, svuzpq1, svuzpq2, svzipq1, svzipq2): New function entries.
* config/aarch64/aarch64-sve-builtins-sve2.def (svaddqv, svandqv)
(svdup_laneq, sveorqv, svextq, svld2q, svld3q, svld4q, svmaxnmqv)
(svmaxqv, svminnmqv, svminqv, svorqv, svpmov, svpmov_lanes, vst2q)
(svst3q, svst4q, svtblq, svtbxq, svuzpq1, svuzpq2, svzipq1, svzipq2)
(svld1q_gather, svld1udq, svld1uwq, svst1dq, svst1q_scatter)
(svst1wq): New function definitions.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_hsd_data)
(hsd_data, s_data): New type lists.
(function_resolver::infer_pointer_type): Give a specific error about
passing a pointer to 8-bit elements to an _index function.
(function_resolver::resolve_sv_displacement): Check whether the
function allows 32-bit bases.
* config/aarch64/iterators.md (UNSPEC_TBLQ, UNSPEC_TBXQ): New unspecs.
(UNSPEC_ADDQV, UNSPEC_ANDQV, UNSPEC_DUPQ, UNSPEC_EORQV, UNSPEC_EXTQ)
(UNSPEC_FADDQV, UNSPEC_FMAXQV, UNSPEC_FMAXNMQV, UNSPEC_FMINQV)
(UNSPEC_FMINNMQV, UNSPEC_LD1_EXTENDQ, UNSPEC_LD1Q_GATHER): Likewise.
(UNSPEC_LDNQ, UNSPEC_ORQV, UNSPEC_PMOV_PACK, UNSPEC_PMOV_PACK_LANE)
(UNSPEC_PMOV_UNPACK, UNSPEC_PMOV_UNPACK_LANE, UNSPEC_SMAXQV): Likewise.
(UNSPEC_SMINQV, UNSPEC_ST1_TRUNCQ, UNSPEC_ST1Q_SCATTER, UNSPEC_STNQ)
(UNSPEC_UMAXQV, UNSPEC_UMINQV, UNSPEC_UZPQ1, UNSPEC_UZPQ2): Likewise.
(UNSPEC_ZIPQ1, UNSPEC_ZIPQ2): Likewise.
(Vtype): Handle single-vector SVE modes.
(Vendreg): Handle SVE structure modes.
(VNxTI, LD1_EXTENDQ_MEM): New mode attributes.
(SVE_PERMUTE, SVE_TBL, SVE_TBX): New int iterators.
(SVE_INT_REDUCTION_128, SVE_FP_REDUCTION_128): Likewise.
(optab): Handle the new SVE2.1 reductions.
(perm_insn): Handle the new SVE2.1 permutations.
* config/aarch64/aarch64-sve.md
(@aarch64_sve_tbl<mode>): Generalize to...
(@aarch64_sve_<SVE_TBL:perm_insn><mode>): ...this.
(@aarch64_sve_<PERMUTE:perm_insn><mode>): Generalize to...
(@aarch64_sve_<SVE_PERMUTE:perm_insn><mode>): ...this.
* config/aarch64/aarch64-sve2.md (@aarch64_pmov_to_<mode>)
(@aarch64_pmov_lane_to_<mode>, @aarch64_pmov_from_<mode>)
(@aarch64_pmov_lane_from_<mode>, @aarch64_sve_ld1_extendq<mode>)
(@aarch64_sve_ldnq<mode>, aarch64_gather_ld1q): New patterns.
(@aarch64_sve_st1_truncq<mode>, @aarch64_sve_stnq<mode>): Likewise.
(aarch64_scatter_st1q, @aarch64_pred_reduc_<optab>_<mode>): Likewise.
(@aarch64_sve_dupq<mode>, @aarch64_sve_extq<mode>): Likewise.
(@aarch64_sve2_tbx<mode>): Generalize to...
(@aarch64_sve_<SVE_TBX:perm_insn><mode>): ...this.
* config/aarch64/aarch64.cc
(aarch64_classify_vector_memory_mode): New function.
(aarch64_regmode_natural_size): Use it.
(aarch64_classify_index): Likewise.
(aarch64_classify_address): Likewise.
(aarch64_print_address_internal): Likewise.
(aarch64_evpc_hvla): New function.
(aarch64_expand_vec_perm_const_1): Use it.
This patch handles the SVE2p1 instructions that are shared
with SME2. This includes the consecutive-register forms of
the 2-register and 4-register loads and stores, but not the
strided-register forms.
gcc/
* config/aarch64/aarch64.h (TARGET_SVE2p1_OR_SME2): New macro.
* config/aarch64/aarch64-early-ra.cc
(is_stride_candidate): Require TARGET_STREAMING_SME2
(early_ra::maybe_convert_to_strided_access): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def: Mark instructions
that are common to both SVE2p1 and SME2.
* config/aarch64/aarch64-sve.md
(@aarch64_<sur>dot_prod_lane<SVE_FULL_SDI:mode><SVE_FULL_BHI:mode>):
Test TARGET_SVE2p1_OR_SME2 instead of TARGET_STREAMING_SME2.
(@aarch64_sve_<sve_fp_op>vnx4sf): Move TARGET_SVE_BF16 condition
into SVE_BFLOAT_TERNARY_LONG.
(@aarch64_sve_<sve_fp_op>_lanevnx4sf): Likewise
SVE_BFLOAT_TERNARY_LONG_LANE.
* config/aarch64/aarch64-sve2.md
(@aarch64_<LD1_COUNT:optab><mode>): Require TARGET_SVE2p1_OR_SME2
instead of TARGET_STREAMING_SME2.
(@aarch64_<ST1_COUNT:optab><mode>): Likewise.
(@aarch64_sve_ptrue_c<BHSD_BITS>): Likewise.
(@aarch64_sve_pext<BHSD_BITS>): Likewise.
(@aarch64_sve_pext<BHSD_BITS>x2): Likewise.
(@aarch64_sve_cntp_c<BHSD_BITS>): Likewise.
(@aarch64_sve_fclamp<mode>): Likewise.
(*aarch64_sve_fclamp<mode>_x): Likewise.
(<sur>dot_prodvnx4sivnx8hi): Likewise.
(aarch64_sve_fdotvnx4sfvnx8hf): Likewise.
(aarch64_fdot_prod_lanevnx4sfvnx8hf): Likewise.
(@aarch64_sve_while<while_optab_cmp>_b<BHSD_BITS>_x2): Likewise.
(@aarch64_sve_while<while_optab_cmp>_c<BHSD_BITS>): Likewise.
(@aarch64_sve_<optab><VNx8HI_ONLY:mode><VNx8SI_ONLY:mode>): Move
TARGET_STREAMING_SME2 condition into SVE_QCVTxN.
(@aarch64_sve_<sve_int_op><mode>): Likewise
SVE2_INT_SHIFT_IMM_NARROWxN, but also require TARGET_STREAMING_SME2
for the 4-register forms.
* config/aarch64/iterators.md (SVE_BFLOAT_TERNARY_LONG): Require
TARGET_SVE2p1_OR_SME2 rather than TARGET_STREAMING_SME2 for
UNSPEC_BFMLSLB and UNSPEC_BFMLSLT. Require TARGET_SVE_BF16
for the others.
(SVE_BFLOAT_TERNARY_LONG_LANE): Likewise.
(SVE2_INT_SHIFT_IMM_NARROWxN): Require TARGET_SVE2p1_OR_SME2 for
the interleaving forms and TARGET_STREAMING_SME2 for the rest.
(SVE_QCVTxN): Likewise.
Some instructions that were previously restricted to streaming mode
can also be used in non-streaming mode with SVE2.1. This patch adds
support for those, as well as the usual new-extension boilerplate.
A later patch will add the feature macro.
gcc/
* config/aarch64/aarch64-option-extensions.def (sve2p1): New extension.
* doc/invoke.texi (sve2p1): Document it.
* config/aarch64/aarch64-sve-builtins-sve2.def: Mark instructions
that are common to both SVE2p1 and SME.
* config/aarch64/aarch64.h (TARGET_SVE2p1): New macro.
(TARGET_SVE2p1_OR_SME): Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve_psel<BHSD_BITS>): Require TARGET_SVE2p1_OR_SME
instead of TARGET_STREAMING.
(*aarch64_sve_psel<BHSD_BITS>_plus): Likewise.
(@aarch64_sve_<su>clamp<mode>): Likewise.
(*aarch64_sve_<su>clamp<mode>_x): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(@cond_<optab><mode>): Likewise.
This patch moves the scalar and single-vector Advanced SIMD types
from arm_neon.h into a private header, so that they can be defined
by arm_sve.h as well. This is needed for the upcoming SVE2.1
hybrid-VLA reductions, which return 128-bit Advanced SIMD vectors.
The approach follows Claudio's patch for FP8.
gcc/
* config.gcc (extra_headers): Add arm_private_neon_types.h.
* config/aarch64/arm_private_neon_types.h: New file, split out
from...
* config/aarch64/arm_neon.h: ...here.
* config/aarch64/arm_sve.h: Include arm_private_neon_types.h
This patch adds an svboolx4_t type, to go alongside the existing
svboolx2_t type. It doesn't require any special ISA support beyond
SVE itself and it currently has no associated instructions.
All extending gather load intrinsics encode the source type in
their name (e.g. svld1sb for an extending load from signed bytes).
The type of the extension result has to be specified using an
explicit type suffix; it isn't something that can be inferred
from the arguments, since there are multiple valid choices for
the same arguments.
This meant that type inference for gather loads was only needed for
non-extending loads, in which case the pointer target had to be a
32-bit or 64-bit element type. The gather_scatter_p argument to
function_resolver::infer_pointer_type therefore controlled two things:
how we should react to vector base addresses, and whether we should
require a minimum element size of 32.
The element size restriction doesn't apply to the upcomding SVE2.1
svld1q intrinsic, so this patch adds a separate argument for the minimum
element size requirement.
gcc/
* config/aarch64/aarch64-sve-builtins.h
(function_resolver::target_type_restrictions): New enum.
(function_resolver::infer_pointer_type): Add an extra argument
that specifies what the target type can be.
* config/aarch64/aarch64-sve-builtins.cc
(function_resolver::infer_pointer_type): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(load_gather_sv_base::get_target_type_restrictions): New virtual
member function.
(load_gather_sv_base::resolve): Use it. Update call to
infer_pointer_type.
aarch64: Add an abstraction for scatter store type inference
Until now, all data arguments to a scatter store needed to have
32-bit or 64-bit elements. This isn't true for the upcoming SVE2.1
svst1q scatter intrinsic, so this patch adds an abstraction around the
restriction.
gcc/
* config/aarch64/aarch64-sve-builtins-shapes.cc
(store_scatter_base::infer_vector_type): New virtual member function.
(store_scatter_base::resolve): Use it.
aarch64: Add an abstraction for vector base addresses
In the upcoming SVE2.1 svld1q and svst1q intrinsics, the relationship
between the base vector and the data vector differs from existing
gather/scatter intrinsics. This patch adds a new abstraction to
handle the difference.
gcc/
* config/aarch64/aarch64-sve-builtins.h
(function_shape::vector_base_type): New member function.
* config/aarch64/aarch64-sve-builtins.cc
(function_shape::vector_base_type): Likewise.
(function_resolver::resolve_sv_displacement): Use it.
(function_resolver::resolve_gather_address): Likewise.
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