* elfxx-sparc.c (allocate_dynrelocs): Don't make a symbol dynamic
unless it is undefined weak.
* elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Set the flag
relative_reloc to direct non-dynamic symbols to R_SPARC_RELATIVE
relocation.
* elfxx-sparc.c (_bfd_sparc_elf_finish_dynamic_symbol): If symbol
is not dynamic in PIC, abort.
These relocation types are supposed to be used for large memory model PIC/pic
mode under which we will have an initialized GP register points to the base of
GOT table, then these relocations are supposed to put the distance between GOT
entry and GOT table base address into the related instructions.
So, the parameters required to calculate the relocation should be the same as
BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 etc, all of them are require the GOT entry
address and GOT table base address to perform the relocation.
This patch has removed those duplicated code when handling above listed
relocation types, grouped them with others as relocation types that are
require GOT table base address during performing relocation, reused the
existed GOT handling code.
The relocation calculation for these types before and after this patch should be
identical.
bfd/
* elfnn-aarch64.c (aarch64_relocation_aginst_gp_p): New function.
(elfNN_aarch64_final_link_relocate): Delete duplicated code for
BFD_RELOC_AARCH64_LD64_GOTOFF_LO15, BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC,
BFD_RELOC_AARCH64_MOVW_GOTOFF_G1.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Optimize the
support for them.
Andreas Arnez [Thu, 29 Jun 2017 08:30:09 +0000 (10:30 +0200)]
S390: Support guarded-storage core note sections
Newer Linux kernel versions offer two new register sets in support of the
z/Architecture's guarded storage facility: NT_S390_GS_CB, the
"guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage
broadcast control block". This patch adds support for the respective core
notes sections to binutils.
bfd/ChangeLog:
* elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype.
(elfcore_write_s390_gs_bc): Likewise.
* elf.c (elfcore_grok_s390_gs_cb): New function.
(elfcore_grok_s390_gs_bc): New function.
(elfcore_grok_note): Call them.
(elfcore_write_s390_gs_cb): New function.
(elfcore_write_s390_gs_bc): New function.
(elfcore_write_register_note): Call them.
binutils/ChangeLog:
* readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC.
include/ChangeLog:
* elf/common.h (NT_S390_GS_CB): New macro.
(NT_S390_GS_BC): Likewise.
But doesn't include the corresponding header
("common/scoped_restore.h"). We haven't noticed a problem because
utils.h includes scoped_restore.h, and defs.h includes utils.h.
However, a patch that makes "symtab.h" include "completer.h", exposed
the issue:
https://sourceware.org/ml/gdb-patches/2017-06/msg00023.html.
Without this fix that would break building all .o files like this:
In file included from src/gdb/completer.h:21:0,
from src/gdb/symtab.h:28,
from src/gdb/language.h:26,
from src/gdb/frame.h:72,
from src/gdb/gdbarch.h:39,
from src/gdb/defs.h:636,
from src/gdb/top.c:20:
src/gdb/command.h:434:8: error: ‘scoped_restore_tmpl’ does not name a type
extern scoped_restore_tmpl<int> prevent_dont_repeat (void);
^
Makefile:1911: recipe for target 'top.o' failed
because defs.h includes gdbarch.h before it includes utils.h.
gdb/ChangeLog:
2017-06-28 Pedro Alves <palves@redhat.com>
Jiong Wang [Wed, 28 Jun 2017 10:00:55 +0000 (11:00 +0100)]
[ARM] Assembler and disassembler support Dot Product Extension
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
The basic issue is that section data referenced through an objfile
pointer can also be referenced via the program-space data pointer,
although via a separate mapping mechanism, which is set up by
update_section_map. Thus once section data attached to an objfile
pointer is released, the section map associated with the program-space
data pointer must be marked dirty to ensure that update_section_map is
called to prevent stale data being referenced. For the matter at hand
this marking is being done via a call to objfiles_changed.
Before commit 3e29f34 objfiles_changed could be called after all of
the objfile pointers were processed in reread_symbols since section
data references via the program-space data pointer would not occur in
the calls of read_symbols performed by reread_symbols.
With commit 3e29f34 MIPS target specific calls to find_pc_section were
added to the code for DWARF information processing, which is called
via read_symbols. Thus in reread_symbols the call to objfiles_changed
needs to be called before calling read_symbols, otherwise stale
section data can be referenced.
Thanks to Luis Machado for providing text for the main comment
associated with the change.
gdb/
2017-06-28 Doug Gilmore <Doug.Gilmore@imgtec.com>
PR gdb/21337
* symfile.c (reread_symbols): Call objfiles_changed just before
read_symbols.
gdb/testsuite/
2017-06-28 Doug Gilmore <Doug.Gilmore@imgtec.com>
PR gdb/21337
* gdb.base/reread-readsym.exp: New file.
* gdb.base/reread-readsym.c: New file.
MIPS: Add new Imagination interAptiv MR2 GAS and LD tests
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly,
disassembly and ELF object file flags.
Add LD tests to verify Imagination interAptiv MR2 ELF object file
link-time compatibility and flag merging/propagation. Use the framework
enhancement added with commit 7575e6a752ec ("MIPS/LD/testsuite:
mips-elf-flags: Add MIPS ABI Flags handling").
gas/
* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
* testsuite/gas/mips/save-err.d: New test.
* testsuite/gas/mips/save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
* testsuite/gas/mips/mips1@save-sub.d: New test.
* testsuite/gas/mips/mips2@save-sub.d: New test.
* testsuite/gas/mips/mips3@save-sub.d: New test.
* testsuite/gas/mips/mips4@save-sub.d: New test.
* testsuite/gas/mips/mips5@save-sub.d: New test.
* testsuite/gas/mips/mips32@save-sub.d: New test.
* testsuite/gas/mips/mips64@save-sub.d: New test.
* testsuite/gas/mips/mips16@save-sub.d: New test.
* testsuite/gas/mips/mips16e@save-sub.d: New test.
* testsuite/gas/mips/r3000@save-sub.d: New test.
* testsuite/gas/mips/r3900@save-sub.d: New test.
* testsuite/gas/mips/r4000@save-sub.d: New test.
* testsuite/gas/mips/vr5400@save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
* testsuite/gas/mips/sb1@save-sub.d: New test.
* testsuite/gas/mips/octeon2@save-sub.d: New test.
* testsuite/gas/mips/octeon3@save-sub.d: New test.
* testsuite/gas/mips/xlr@save-sub.d: New test.
* testsuite/gas/mips/r5900@save-sub.d: New test.
* testsuite/gas/mips/mips16e2-copy.d: New test.
* testsuite/gas/mips/mips16e2-copy-err.d: New test.
* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
option. Adjust for trailing padding change.
* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
* testsuite/gas/mips/save-sub.s: New test source.
* testsuite/gas/mips/mips16e2-copy.s: New test source.
* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
* testsuite/gas/mips/save.s: Update description, change trailing
padding and remove trailing white space.
* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
tests across the regular MIPS interAptiv MR2 architecture. Run
the new tests.
with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are
consistent with the remaining architecture results for these cases, that
do not take into account the lack of R_MIPS_JALR relocations produced by
GAS for these targets. As a preexisting issue these failures are not
addressed with this change.
gas/
* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
(mips16e2-interaptiv-mr2): Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d:
New test.
* testsuite/gas/mips/interaptiv-mr2@mcu.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test.
* testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE
flag lines present rather than just one.
* testsuite/gas/mips/attr-gnu-4-6.d: Likewise.
* testsuite/gas/mips/attr-gnu-4-7.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l:
New stderr output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr
output.
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:
1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
MIPS16e2 instructions[1], for assembly and disassembly,
2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
regular MIPS instructions[2], for assembly and disassembly,
3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
extension.
4. Support for interAptiv MR2 architecture selection for assembly, in
the form of the `-march=interaptiv-mr2' command-line option and its
corresponding `arch=interaptiv-mr2' setting for the `.set' and
`.module' pseudo-ops.
5. Support for interAptiv MR2 architecture selection for disassembly,
in the form of the `mips:interaptiv-mr2' target architecture, for
use e.g. with the `-m' command-line option for `objdump'.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
Imagination Technologies Ltd., Document Number: MD00904, Revision
02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
Instructions", pp. 878-883
[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917
include/
* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
(AFL_EXT_INTERAPTIV_MR2): Likewise.
* opcode/mips.h: Document new operand codes defined.
(INSN_INTERAPTIV_MR2): New macro.
(INSN_CHIP_MASK): Adjust accordingly.
(CPU_INTERAPTIV_MR2): New macro.
(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
(MIPS16_ALL_ARGS): Rename to...
(MIPS_SVRS_ALL_ARGS): ... this.
(MIPS16_ALL_STATICS): Rename to...
(MIPS_SVRS_ALL_STATICS): ... this.
bfd/
* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
* cpu-mips.c (I_interaptiv_mr2): New enum value.
(arch_info_struct): Add "mips:interaptiv-mr2" entry.
* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
case.
(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
`bfd_mach_mips_interaptiv_mr2' entries.
* bfd-in2.h: Regenerate.
opcodes/
* mips-formats.h (INT_BIAS): New macro.
(INT_ADJ): Redefine in INT_BIAS terms.
* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
(mips_print_save_restore): New function.
(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
call.
(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
(print_mips16_insn_arg): Call `mips_print_save_restore' for
OP_SAVE_RESTORE_LIST handling, factored out from here.
* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
(mips_builtin_opcodes): Add "restore" and "save" entries.
* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
(IAMR2): New macro.
(mips16_opcodes): Add "copyw" and "ucopyw" entries.
gas/
* config/tc-mips.c (validate_mips_insn): Handle
OP_SAVE_RESTORE_LIST specially.
(mips_encode_save_restore, mips16_encode_save_restore): New
functions.
(match_save_restore_list_operand): Factor out SAVE/RESTORE
operand insertion into the instruction word or halfword to these
new functions.
(mips_cpu_info_table): Add "interaptiv-mr2" entry.
* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
`-march=' argument list.
Pedro Alves [Tue, 27 Jun 2017 15:22:08 +0000 (16:22 +0100)]
objfile_per_bfd_storage non-POD
A following patch will want to add a std::vector to
objfile_per_bfd_storage. That makes it non-trivially
constructible/destructible. Since objfile_per_bfd_storage objects are
allocated on an obstack, we need to call their ctors/dtors manually.
This is what this patch does. And then since we can now rely on
ctors/dtors being run, make objfile_per_bfd_storage::storage_obstack
be an auto_obstack.
gdb/ChangeLog:
2017-06-27 Pedro Alves <palves@redhat.com>
* objfiles.c (get_objfile_bfd_data): Call bfd_alloc instead of
bfd_zalloc. Call objfile_per_bfd_storage's ctor.
(free_objfile_per_bfd_storage): Call objfile_per_bfd_storage's
dtor.
* objfiles.h (objfile_per_bfd_storage): Add ctor. Make
'storage_obstack' field an auto_obstack. In-class initialize all
non-bitfield fields. Make minsyms_read bool.
* symfile.c (read_symbols): Adjust.
Here, the 'name_obstack' variable is a global. The change means that
the obstack's contents from a previous parse will stay around until
the next parsing starts. I.e., memory won't be reclaimed until then.
I don't think that's a problem, these objects don't really grow much
at all.
The other option I tried was to add a separate type that is like
auto_obstack but manages an external obstack, just for those cases. I
like the current approach better as that other approach adds more
boilerplate and yet another type to learn.
gdb/ChangeLog:
2017-06-27 Pedro Alves <palves@redhat.com>
* c-exp.y (name_obstack): Now an auto_obstack.
(yylex): Use auto_obstack::clear.
(c_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* c-lang.c (evaluate_subexp_c): Use auto_obstack.
* d-exp.y (name_obstack): Now an auto_obstack.
(yylex): Use auto_obstack::clear.
(d_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* dwarf2loc.c (fetch_const_value_from_synthetic_pointer): Use
auto_obstack.
* dwarf2read.c (create_addrmap_from_index)
(dwarf2_build_psymtabs_hard)
(update_enumeration_type_from_children): Likewise.
* gdb_obstack.h (auto_obstack): New type.
* go-exp.y (name_obstack): Now an auto_obstack.
(build_packaged_name): Use auto_obstack::clear.
(go_parse): Use auto_obstack::clear instead of reinitializing and
freeing the obstack.
* linux-tdep.c (linux_make_mappings_corefile_notes): Use
auto_obstack.
* printcmd.c (printf_wide_c_string, ui_printf): Use auto_obstack.
* rust-exp.y (work_obstack): Now an auto_obstack.
(rust_parse, rust_lex_tests): Use auto_obstack::clear instead of
reinitializing and freeing the obstack.
* utils.c (do_obstack_free, make_cleanup_obstack_free): Delete.
(host_char_to_target): Use auto_obstack.
* utils.h (make_cleanup_obstack_free): Delete declaration.
* valprint.c (generic_emit_char, generic_printstr): Use
auto_obstack.
Fix incorrect adjustment of diff relocs when relaxing, and thus the
resulting source line to address mismatch.
Fix two issues when adjusting diff relocs to account for
deleted bytes.
1. Don't adjust the difference if the end address is the shrinked
insn's address i.e. use < instead of <=. The relaxation code deletes
count bytes from or after shrinked_insn_address, so the difference
between start_address and end_address should remain unchanged in this
case.
2. Adjust the reloc addend if the difference is to be adjusted and
symval + reloc addend is past the shrinked insn address. This is
because for a typical sym1 - sym2 diff reloc, sym1 is .text +
irel->r_addend, and the addend should be reduced to account for the
shrinked insn.
For example, assume the reloc value is .text + 0x8 with .text = 0, the
diff value in the object file = 0x4, and shrinked_insn_address = 0x4
with count = 0x2. Then the existing code writes 0x2 into the object
file to account for the deleted bytes, as shrinked_insn_address lies
between 0x8 and 0x8 - 0x4 = 0x4, but leaves the addend as is. The next
time the reloc is looked at, the code sees if a shrinked_insn_address
lies between 0x8 and 0x8 - 0x2 = 0x6, instead of 0x6 and 0x4. If there
happens to be one, then the diff value in the object file ends up
getting reduced again.
with the corresponding partial backtrace (sorry, taken with lldb,
because well, gdb is broken :)):
frame #9: 0x000000010004605a gdb`darwin_check_new_threads(inf=0x0000000100edf670) at darwin-nat.c:383
frame #10: 0x0000000100045848 gdb`darwin_init_thread_list(inf=0x0000000100edf670) at darwin-nat.c:1710
frame #11: 0x00000001000452f8 gdb`darwin_ptrace_him(pid=8375) at darwin-nat.c:1792
frame #12: 0x0000000100041d95 gdb`fork_inferior(...) at fork-inferior.c:440
frame #13: 0x0000000100043f82 gdb`darwin_create_inferior(...) at darwin-nat.c:1841
frame #14: 0x000000010034ac32 gdb`run_command_1(args=0x0000000000000000, from_tty=1, tbreak_at_main=1) at infcmd.c:611
The issue was introduced by commit
"Share fork_inferior et al with gdbserver"
because it changed the place where the dummy thread (pid, 0, 0) is added,
relative to the call to the init_trace_fun callback. In this callback, darwin
checks for new threads in the program (there should be exactly one) in order to
update this dummy thread with the right tid. Previously, things happened in
this order:
- fork_inferior calls fork()
- fork_inferior adds dummy thread
- fork_inferior calls init_trace_fun callback, which updates the dummy
thread info
Following the commit mentioned above, the new thread is added in the
darwin-nat code, after having called fork_inferior (in
darwin_create_inferior). So gdb tries to do things in this order:
- fork_inferior calls fork()
- fork_inferior calls init_trace_fun callback, which tries to update
the dummy thread info
- darwin_create_inferior adds the dummy thread
The error happens while trying to update the dummy thread that has not
been added yet.
I don't think this dummy thread is necessary for darwin. Previously, it
was fork_inferior that was adding this thread, for all targets, so
darwin had to deal with it. Now that it's done by targets themselves,
we can just skip that on darwin. darwin_check_new_threads called
indirectly by init_trace_fun/darwin_ptrace_him will simply notice the
new thread and add it with the right information.
My level of testing was: try to start a process and try to attach to a
process, and it seems to work somewhat like it did before. I tried to
run the testsuite, but it leaves a huge amount of zombie processes that
launchd doesn't seem to reap, leading to exhaustion of system resources
(number of processes).
MIPS/LD/testsuite: mips-elf-flags: Add MIPS ABI Flags handling
Complement commit 351cdf24d223 ("[MIPS] Implement O32 FPXX, FP64 and
FP64A ABI extensions") and add optional MIPS ABI Flags handling to
`good_combination' in the `mips-elf-flags.exp' test script. This lets
callers of this procedure request to examine MIPS ABI Flags in addition
to the `e_flags' member of the ELF file header so as to verify that
flags are merged correctly by LD. The presence of further arguments
triggers this verification, in which case `readelf' is called with the
`-A' option additionally specified and the ISA member, the ISA Extension
member and the ASEs member will be examined as per the arguments.
Unlike with `readelf -h' output consider a failure to retrieve the
member requested a test case failure rather than an unresolved result.
This is because unlike with the `e_flags' member of the ELF file header
which is always there in any valid ELF file the MIPS ABI Flags structure
is optional in LD output and the absence of this structure when expected
is surely a bug in LD.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Add an `args' final argument and examination code for `readelf
-A' output. Update procedure description accordingly.
MIPS/LD/testsuite: mips-elf-flags: Use `remote_exec' to call `readelf'
For ELF file header flag verification done in `good_combination' in the
`mips-elf-flags.exp' test script the version of `readelf' built along
with the rest of binutils has to be used rather than any such executable
already present on the build system, so that flags recognized by the
tool match those supported by LD being tested. Use `remote_exec' as
elsewhere in the LD test framework and also with GAS and LD used here,
getting and arranging for extra reporting of `readelf' calls included in
test logs on this occasion as well.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Use `remote_exec' to call `readelf'. Log the command issued.
MIPS/LD/testsuite: mips-elf-flags: Use `-h' only with `readelf'
For the purpose of link-time object compatibility handling verification
code in the `good_combination' procedure from the `mips-elf-flags.exp'
test script only examines the `e_flags' member of the ELF file header
and ignores data from any ELF program or section headers present. Use
`readelf -h' rather than `readelf --headers' then to obtain data for
examination, avoiding unnecessary processing to extract this extraneous
information.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
Use `readelf -h' rather than `readelf --headers'.
Kuan-Lin Chen [Thu, 8 Jun 2017 18:54:14 +0000 (11:54 -0700)]
RISC-V: Use pc-relative relocation for FDE initial location
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.
MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor
Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core
(for an odd reason referred to as LSI R4010 across our code base) as a
MIPS II processor in BFD as well, fixing a bug that has been there since
forever and addressing linker warnings like:
$ as -m4010 empty.s -o 4010.o
$ ld -r 4010.o -o 4010-r.o
ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags
$
due to the ISA level being recorded as MIPS III in ELF file header's
`e_flags' vs MIPS II in the MIPS ABI Flags section:
$ readelf -Ah 4010.o
ELF Header:
Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, big endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: REL (Relocatable file)
Machine: MIPS R3000
Version: 0x1
Entry point address: 0x0
Start of program headers: 0 (bytes into file)
Start of section headers: 348 (bytes into file)
Flags: 0x20821000, 4010, o32, mips3
Size of this header: 52 (bytes)
Size of program headers: 0 (bytes)
Number of program headers: 0
Size of section headers: 40 (bytes)
Number of section headers: 11
Section header string table index: 10
Attribute Section: gnu
File Attributes
Tag_GNU_MIPS_ABI_FP: Hard float (double precision)
Available documentation[1][2] clearly indicates the LSI CW4010 processor
is only backwards compatible with the MIPS R4000 processor as far as the
latter's 32-bit instructions are concerned and consequently can only be
considered a MIPS II ISA implementation (with vendor extensions).
triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
References:
[1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A
Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995,
presented at Hot Chips VII, Stanford University, Stanford,
California, August 1995
[2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI
Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017
bfd/
* cpu-mips.c (arch_info_struct): Mark the 4010 32-bit.
* elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set
E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'.
(mips_mach_extensions): Mark `bfd_mach_mips4010' as extending
`bfd_mach_mips6000' rather than `bfd_mach_mips4000'.
ld/
* testsuite/ld-mips-elf/lsi-4010-isa.d: New test.
* ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
H.J. Lu [Mon, 26 Jun 2017 16:24:49 +0000 (09:24 -0700)]
Check file size before getting section contents
Don't check the section size in bfd_get_full_section_contents since
the size of a decompressed section may be larger than the file size.
Instead, check file size in _bfd_generic_get_section_contents.
PR binutils/21665
* compress.c (bfd_get_full_section_contents): Don't check the
file size here.
* libbfd.c (_bfd_generic_get_section_contents): Check for and
reject a section whoes size + offset is greater than the size
of the entire file.
(_bfd_generic_get_section_contents_in_window): Likewise.
LD: Fix .startof.SECNAME/.sizeof.SECNAME tests for MIPS/IRIX
Correct .startof.SECNAME/.sizeof.SECNAME tests for MIPS/IRIX targets,
complementing commit dc74becf498f ("ld: Add tests for -Ur") and commit da614360f520 ("ld: Add tests for .startof.SECNAME/.sizeof.SECNAME") with
subsequent updates, and in reference to commit cbd0eecf261c ("Always
define referenced __start_SECNAME/__stop_SECNAME") and commit 7dba9362c172 ("Rewrite __start and __stop symbol handling").
These targets set the STT_OBJECT type for non-function symbol
references, according to `elf_frob_symbol' code in gas/config/obj-elf.c:
/* The Irix 5 and 6 assemblers set the type of any common symbol and
any undefined non-function symbol to STT_OBJECT. We try to be
compatible, since newer Irix 5 and 6 linkers care. However, we
only set undefined symbols to be STT_OBJECT if we are on Irix,
because that is the only time gcc will generate the necessary
.global directives to mark functions. */
if (S_IS_COMMON (symp))
symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
and consequently entries in the symbol table listing from `readelf'
produced with these tests do not match the NOTYPE pattern expected,
causing test suite failures:
specifically with the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
Given that it does not matter for the feature covered by these tests
whether the type of the symbols produced is STT_NOTYPE or STT_OBJECT
adjust the problematic cases to accept either type, removing the
failures observed.
ld/
* testsuite/ld-elf/sizeofa.d: Also accept the OBJECT type for
the symbols examined.
* testsuite/ld-elf/sizeofc.d: Likewise.
* testsuite/ld-elf/startofa.d: Likewise.
* testsuite/ld-elf/startofc.d: Likewise.
Simon Marchi [Mon, 26 Jun 2017 13:08:36 +0000 (15:08 +0200)]
record-full: Remove unused function netorder16
clang shows this warning:
/home/emaisin/src/binutils-gdb/gdb/record-full.c:2344:1: error: unused function 'netorder16' [-Werror,-Wunused-function]
netorder16 (uint16_t input)
^
Remove this function, which, AFAIK, has never been used. Note that GCC
doesn't warn about this, because the function is marked as inline.
According to gcc's man page, it should ideed not warn:
-Wunused-function
Warn whenever a static function is declared but not defined or a non-inline static function is unused. This warning is enabled by -Wall.
So it's probably not a GCC bug that it doesn't find this unused function, but a
different definition of "unused".
Simon Marchi [Mon, 26 Jun 2017 13:08:35 +0000 (15:08 +0200)]
vec: Silence -Wunused-function warnings on clang
clang has a too aggressive (or broken, depends on how you want to see
it) -Wunused-function warning, which is triggered by the functions
defined by DEF_VEC_* but not used in the current source file. Normally,
it won't warn about unused static inline functions defined in header
files, because it's expected that a source file won't use all functions
defined in a header file it includes. However, if the DEF_VEC_* macro
is used in a source file, it considers those functions as defined in the
source file, which leads it to think that we should remove those
functions. It is therefore missing a check to see whether those
functions are resulting from macro expansion. A bug already exists for
that:
https://bugs.llvm.org//show_bug.cgi?id=22712
It's quite easy to silence this warning in a localized way, that is in
the DEF_VEC_* macros.
gdb/ChangeLog:
* common/diagnostics.h: Define macros for GCC.
(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): New macro.
* common/vec.h: Include diagnostics.h.
(DIAGNOSTIC_IGNORE_UNUSED_VEC_FUNCTION): New macro.
(DEF_VEC_I, DEF_VEC_P, DEF_VEC_O): Ignore -Wunused-function
warning.
Simon Marchi [Mon, 26 Jun 2017 13:08:35 +0000 (15:08 +0200)]
ada-lex: Ignore warnings about register keyword
Some older versions of flex (such as the one shipped with macOS) generate
code that use the register keyword, which clang warns about. This patch
makes the compiler ignore those warnings for the portion of the code
generated by flex.
Nick Clifton [Mon, 26 Jun 2017 14:25:08 +0000 (15:25 +0100)]
Fix address violations when atempting to parse fuzzed binaries.
PR binutils/21665
bfd * opncls.c (get_build_id): Check that the section is beig enough
to contain the whole note.
* compress.c (bfd_get_full_section_contents): Check for and reject
a section whoes size is greater than the size of the entire file.
* elf32-v850.c (v850_elf_copy_notes): Allow for the ouput to not
contain a notes section.
binutils* objdump.c (disassemble_section): Skip any section that is bigger
than the entire file.
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
Alan Modra [Sun, 25 Jun 2017 23:40:22 +0000 (09:10 +0930)]
Don't attach linker created section to --just-syms bfd
All sections on a --just-syms bfd are discarded from the output, so
attaching linker created sections to such a bfd results in errors.
In other cases, like the .note.GNU-stack check, it's wrong to have a
--just-syms object potentially affect the output.
bfd/
* elflink.c (_bfd_elf_link_create_dynstrtab): Don't make dynobj
a --just-syms bfd.
(_bfd_elf_size_group_sections): Skip --just-syms bfds.
(bfd_elf_size_dynamic_sections): Ignore .note.GNU-stack and
.preinit_array on --just-syms bfds.
(_bfd_elf_gc_mark_extra_sections): Skip --just-syms bfds.
(elf_gc_sweep, bfd_elf_parse_eh_frame_entries): Likewise.
(bfd_elf_gc_sections, bfd_elf_discard_info): Likewise.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Skip
--just-syms bfds when looking for a place to attach .note.gnu.build-id
and .eh_frame_hdr sections. Delete dead code.
Simon Marchi [Sun, 25 Jun 2017 10:57:13 +0000 (12:57 +0200)]
main: Don't add int to string
clang shows this warning:
/home/emaisin/src/binutils-gdb/gdb/main.c:227:56: error: adding 'int' to a string does not append to the string [-Werror,-Wstring-plus-int]
char *tmp_sys_gdbinit = xstrdup (SYSTEM_GDBINIT + datadir_len);
~~~~~~~~~~~~~~~^~~~~~~~~~~~~
/home/emaisin/src/binutils-gdb/gdb/main.c:227:56: note: use array indexing to silence this warning
char *tmp_sys_gdbinit = xstrdup (SYSTEM_GDBINIT + datadir_len);
^
& [ ]
It's quite easy to get rid of it by using &foo[len] instead of foo + len.
I think this warning is relevant to keep enabled, because it can be an
easy mistake to do.
This warning is already discussed here in GCC bugzilla:
Simon Marchi [Sun, 25 Jun 2017 10:49:19 +0000 (12:49 +0200)]
dtrace-probe: Put semicolon after while on its own line
clang shows this warning.
/home/emaisin/src/binutils-gdb/gdb/dtrace-probe.c:424:52: error: while loop has empty body [-Werror,-Wempty-body]
while (*p++ != '\0' && p - strtab < strtab_size);
^
/home/emaisin/src/binutils-gdb/gdb/dtrace-probe.c:424:52: note: put the semicolon on a separate line to silence this warning
Putting the semicolon on its own line is not a big sacrifice to get rid of this
warning. I think it's also useful to keep this, because it can catch errors
like this:
while (something);
{
...
}
although gcc would warn about it in a different way (misleading indentation).
This warning is already discussed here in the GCC bugzilla:
Simon Marchi [Sun, 25 Jun 2017 10:38:59 +0000 (12:38 +0200)]
x86-dregs: Print debug registers one per line
This get around this warning given by clang...
/home/emaisin/src/binutils-gdb/gdb/nat/x86-dregs.c:209:7: error: variable 'i' is incremented both in the loop header and in the loop body [-Werror,-Wfor-loop-analysis]
i++;
^
/home/emaisin/src/binutils-gdb/gdb/nat/x86-dregs.c:199:32: note: incremented here
ALL_DEBUG_ADDRESS_REGISTERS (i)
^
... I decided in the end to simply print the debug registers one per
line. I don't think it particularly helps readability to have them two
per line anyway.
gdb/ChangeLog:
* nat/x86-dregs.c (x86_show_dr): Print registers one per line.
* d-demangle.c (dlang_call_convention_p): Move declaration
before dlang_type.
(dlang_type): Handle function types.
* testsuite/d-demangle-expected: Add tests.
* d-demangle.c (dlang_parse_real): Remove stack buffer, write
the demangled hexadecimal directly to string.
* testsuite/d-demangle-expected: Add tests.
* d-demangle.c (dlang_hexdigit): New function.
(ascii2hex): Remove function.
(dlang_parse_string): Update to call dlang_hexdigit.
* testsuite/d-demangle-expected: Add tests.
* d-demangle.c (strtol): Remove declaration.
Updated all callers to use dlang_number.
(dlang_number): New function.
(dlang_value): Moved check for ISDIGIT into dlang_parse_integer.
* testsuite/d-demangle-expected: Add tests.
* d-demangle.c (dlang_parse_symbol): Remove function.
(dlang_parse_qualified): New function.
(dlang_parse_mangle): New function.
(dlang_type): Update to call dlang_parse_qualified.
(dlang_identifier): Update to call either dlang_parse_qualified or
dlang_parse_mangle.
(dlang_type_modifier_p): Remove function.
(dlang_call_convention_p): Don't allow type modifiers in mangle.
(dlang_template_args): Update to call dlang_identifier.
(dlang_demangle): Update to call dlang_parse_mangle.
* testsuite/d-demangle-expected: Add tests.
* d-demangle.c (dlang_value): Add comment explaining why cases for
digits are required.
* testsuite/d-demangle-expected: Update integer value tests.
* d-demangle.c (dlang_identifier): Handle template constraint symbols.
(dlang_parse_template): Only advance if template symbol prefix is
followed by a digit.
* testsuite/d-demangle-expected: Add tests.
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARM Cortex-R52
processor.
=== Patch description ===
This patch adds support for Cortex-R52 as an ARMv8-R processor with CRC
extensions.
2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* NEWS: Mention support of ARM Cortex-R52 processor.
* config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
* doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in the linker.
=== Patch description ===
This patch is composed of 3 changes:
1) The main change is the addition of the logic for merging a file whose
Tag_CPU_arch build attribute is 15 (ARMv8-R). Namely, all pre-ARMv8 are
merged into ARMv8-R as well as ARMv8-R itself. ARMv8-A (14) merges into
ARMv8-A. ARMv8-M Baseline (16) and Mainline (17) are not allowed to
merge merge with ARMv8-R. Note that merging only occurs if the two
profiles are identical or one is S (Application or Realtime) and the
other is R.
2) using_thumb_only, using_thumb2_bl, using_thumb2 and arch_has_arm_nop
are updated according to capabilities of ARMv8-R and their BFD_ASSERT
updated to reflect that the logic is valid for ARMv8-R.
3) 2 build attribute merging tests are added to test the first change.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Update list of architectures in
BFD_ASSERT for which the logic is valid.
(using_thumb2_bl): Likewise.
(using_thumb2): Likewise and return true for ARMv8-R.
(arch_has_arm_nop): Likewise.
(tag_cpu_arch_combine): New v8r table for ARMv8-R Tag_CPU_arch
merging logic. Update commentis for value 15 of v8m_baseline,
v8m_mainline and v4t_plus_v6_m arrays. Use v8r array to decide
merging of value 15 of Tag_CPU_arch.
ld/
* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 11): New test.
(EABI attribute merging 12): Likewise.
* testsuite/ld-arm/attr-merge-11a.s: New file.
* testsuite/ld-arm/attr-merge-11b.s: New file.
* testsuite/ld-arm/attr-merge-11.attr: New file.
* testsuite/ld-arm/attr-merge-12a.s: New file.
* testsuite/ld-arm/attr-merge-12b.s: New file.
* testsuite/ld-arm/attr-merge-12.attr: New file.
[ARM] Add support for ARMv8-R in assembler and readelf
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to remove special casing for ARMv6S-M
autodetection.
=== Motivation ===
Currently, SWI and SVC mnemonics are enabled for ARMv4T and successor
architectures with extra checks in the handler function (do_t_swi) to
give an error message when ARMv6-M is targeted and some more special
casing in aeabi_set_public_attributes. This was made to exclude these
mnemonics for ARMv6-M unless the OS extension is in use.
However this logic is superfluous: there is already code to check
whether an instruction is available based on the feature bit it is part
of and whether the targeted architecture has that feature bit. This
patch aims at removing that unneeded complexity.
=== Patch description ===
The OS extension is already limited to the ARMv6-M architecture so all
this patch does is redefined availability of the ARM_EXT_OS feature bit
to not be present for ARM_ARCH_V6M. ARM_ARCH_V6SM does not need any
change either because it already includes ARM_EXT_OS.
The patch also make sure that the error message that was given by
do_t_swi when SWI/SVC is unavailable is still the same by detecting the
situation in md_assemble.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_ext_v6m): Delete.
(arm_ext_v7m): Delete.
(arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
profile.
(arm_arch_v6m_only): Delete.
(do_t_swi): Remove special case for ARMv6S-M.
(md_assemble): Display error message previously in do_t_swi when
SVC is not available.
(insns): Guard swi and svc by arm_ext_os for Thumb mode.
(aeabi_set_public_attributes): Remove special case for ARMv6S-M.
include/
* opcode/arm.h (ARM_AEXT_V4TxM): Add ARM_EXT_OS bit to the set.
(ARM_AEXT_V4T): Likewise.
(ARM_AEXT_V5TxM): Likewise.
(ARM_AEXT_V5T): Likewise.
(ARM_AEXT_V6M): Mask off ARM_EXT_OS bit.
elfcpp/
* elfcpp.h (DT_PPC64_OPT): Define.
* powerpc.h (PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC,
PPC64_OPT_LOCALENTRY): Define.
gold/
* options.h (General_options): Add plt_localentry.
* powerpc.cc (Target_powerpc::st_other): New function.
(Target_powerpc::plt_localentry0_, plt_localentry0_init_,
has_localentry0_): New vars.
(Target_powerpc::plt_localentry0, set_has_localentry0,
is_elfv2_localentry0): New functions.
(Target_powerpc::Branch_info::mark_pltcall): Don't set tocsave or
return true for localentry:0 calls.
(Stub_table::Plt_stub_ent::localentry0_): New var.
(Stub_table::add_plt_call_entry): Set localentry0_ and has_localentry0_.
Don't set r2save_ for localentry:0 calls.
(Output_data_glink::do_write): Save r2 in __glink_PLTresolve for elfv2.
(Target_powerpc::scan_relocs): Default plt_localentry0_.
(Target_powerpc::do_finalize_sections): Set DT_PPC64_OPT.
(Target_powerpc::Relocate::relocate): Don't require nop following
calls for localentry:0 plt calls, and don't change nop.
Alan Modra [Fri, 23 Jun 2017 11:07:34 +0000 (20:37 +0930)]
[GOLD] PowerPC64 tocsave
This adds support to gold for the tocsave relocs already supported by
ld.bfd. R_PPC64_TOCSAVE relocs are part of a scheme to move r2 saves
to the prologue of a function rather than in each plt call stub. We
don't want a compiler to always emit the r2 save, as this would be
wasted if the calls turned out to be local. See the tocsave*.s in
ld/testsuite/ld-powerpc/.
* powerpc.cc (Target_powerpc::tocsave_loc_): New var.
(Target_powerpc::mark_pltcall, add_tocsave, tocsave_loc): New functions.
(Target_powerpc::Branch_info::tocsave_): New var.
(Target_powerpc::Branch_info::mark_pltcall): New function.
(Target_powerpc::Branch_info::make_stub): Pass tocsave_ to
add_plt_call_entry.
(Stub_table::Plt_stub_ent): Make public. Add r2save_.
(Stub_table::add_plt_call_entry): Add bool tocsave_ param. Set
r2save_.
(Stub_table::find_plt_call_entry): Return Plt_stub_ent*. Adjust
use throughout.
(Stub_table::do_write): Conditionally output r2 save in plt stubs.
(Target_powerpc::Scan::local): Handle R_PPC64_TOCSAVE.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Skip r2 save in plt call stub
with tocsave reloc. Replace header tocsave nop with r2 save.
* symtab.h (struct Symbol_location_hash): Make public.
Andreas Krebbel [Thu, 8 Jun 2017 15:24:50 +0000 (17:24 +0200)]
S/390: Add support for pgste marker
This patch adds a new S/390 specific segment type: PT_S390_PGSTE. For
binaries marked with that segment the kernel will allocate 4k page
tables. The only user so far will be qemu.
ld/ChangeLog:
2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* Makefile.in: Add s390.em as build dependency.
* emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em.
* emultempl/s390.em: New file.
* gen-doc.texi: Add documentation for --s390-pgste option.
* ld.texinfo: Likewise.
include/ChangeLog:
2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* elf/s390.h (PT_S390_PGSTE): Define macro.
binutils/ChangeLog:
2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* readelf.c (get_s390_segment_type): Add support for the new
segment type PT_S390_PGSTE.
(get_segment_type): Call get_s390_segment_type.
elfcpp/ChangeLog:
2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* elfcpp.h (enum PT): Add PT_S390_PGSTE to enum.
bfd/ChangeLog:
2017-06-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* elf-s390.h: New file.
* elf64-s390.c (struct elf_s390_link_hash_table): Add params
field.
(elf_s390_additional_program_headers): New function.
(elf_s390_modify_segment_map): New function.
(bfd_elf_s390_set_options): New function.
(elf_backend_additional_program_headers)
(elf_backend_modify_segment_map): Add macro definitions.
H.J. Lu [Thu, 22 Jun 2017 19:53:39 +0000 (12:53 -0700)]
x86: Resolve local undefined weak symbol to 0
Local undefined weak symbol should always be resolved to 0.
* elf32-i386.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): Resolve
local undefined weak symbol to 0.
* elf64-x86-64.c (UNDEFINED_WEAK_RESOLVED_TO_ZERO): Likewise.
Yao Qi [Thu, 22 Jun 2017 12:41:27 +0000 (13:41 +0100)]
Regenerate two regformats/i386/.dat files
The self tests which compare pre-generated target descriptions and
dynamically created target descriptions fail, and it turns out that two
pre-generated target descriptions are wrong, so regenerate them.
is added to GNU program properties to indicate that all executable sections
are compatible with SHSTK where return address popped from shadow stack
always matches return address popped from normal stack.
GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all
relocatable inputs.
bfd/
* elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk
is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
(elf_i386_link_setup_gnu_properties): If info->shstk is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT.
* elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If
info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
(elf_x86_64_link_setup_gnu_properties): If info->shstk is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT.
are added to GNU program properties to indicate that all executable
sections are compatible with IBT when ENDBR instruction starts each
valid target where an indirect branch instruction can land.
GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on
all relocatable inputs.
The followings changes are made to the Procedure Linkage Table (PLT):
PLTn: endbr64 # endbr32 for i386.
jmp *GOT[namen_index]
nop
BND prefix isn't used since MPX isn't supported on x32 and BND registers
aren't used in parameter passing on i386.
GOT is an array of addresses. Initially, GOT[namen_index] is filled
with the address of the ENDBR instruction of the corresponding entry
in the first PLT section. The function, namen, is called via the
ENDBR instruction in the second PLT entry. GOT[namen_index] is updated
to the actual address of the function, namen, at run-time.
2 linker command line options are added:
1. -z ibtplt: Generate IBT-enabled PLT.
2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program
properties as well as IBT-enabled PLT.
bfd/
* elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New.
(elf_i386_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_lazy_ibt_plt0_entry): Likewise.
(elf_i386_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_pic_non_lazy_ibt_plt_entry): Likewise.
(elf_i386_eh_frame_lazy_ibt_plt): Likewise.
(elf_i386_lazy_plt_layout): Likewise.
(elf_i386_non_lazy_plt_layout): Likewise.
(elf_i386_link_hash_entry): Add plt_second.
(elf_i386_link_hash_table): Add plt_second and
plt_second_eh_frame.
(elf_i386_allocate_dynrelocs): Use the second PLT if needed.
(elf_i386_size_dynamic_sections): Use .plt.got unwind info for
the second PLT. Check the second PLT.
(elf_i386_relocate_section): Use the second PLT to resolve
PLT reference if needed.
(elf_i386_finish_dynamic_symbol): Fill and use the second PLT if
needed.
(elf_i386_finish_dynamic_sections): Set sh_entsize on the
second PLT. Generate unwind info for the second PLT.
(elf_i386_plt_type): Add plt_second.
(elf_i386_get_synthetic_symtab): Support the second PLT.
(elf_i386_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_i386_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_i386_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
* elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New.
(elf_x32_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_non_lazy_ibt_plt_entry): Likewise.
(elf_x32_non_lazy_ibt_plt_entry): Likewise.
(elf_x86_64_eh_frame_lazy_ibt_plt): Likewise.
(elf_x32_eh_frame_lazy_ibt_plt): Likewise.
(elf_x86_64_lazy_ibt_plt): Likewise.
(elf_x32_lazy_ibt_plt): Likewise.
(elf_x86_64_non_lazy_ibt_plt): Likewise.
(elf_x32_non_lazy_ibt_plt): Likewise.
(elf_x86_64_get_synthetic_symtab): Support the second PLT.
(elf_x86_64_parse_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND.
(elf_x86_64_merge_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_1_AND. If info->ibt is set, turn
on GNU_PROPERTY_X86_FEATURE_1_IBT
(elf_x86_64_link_setup_gnu_properties): If info->ibt is set,
turn on GNU_PROPERTY_X86_FEATURE_1_IBT. Use IBT-enabled PLT
for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
is set on all relocatable inputs.
Pedro Alves [Thu, 22 Jun 2017 08:31:20 +0000 (10:31 +0200)]
environ-selftests: Ignore -Wself-move warning
clang gives this warning:
..../gdb/unittests/environ-selftests.c:139:7: error: explicitly moving variable of type 'gdb_environ' to itself [-Werror,-Wself-move]
env = std::move (env);
~~~ ^ ~~~
Ignoring the warning locally is the right thing to do, since it warns
about behavior we want to unit test, while an explicit self-move in
real code would likely be a mistake that we'd want to catch.
To avoid cluttering the code with preprocessor conditionals, this
commit adds the file common/diagnostics.h, in which we can put macros
used to control compiler diagnostics.
Nick Clifton [Thu, 22 Jun 2017 09:33:56 +0000 (10:33 +0100)]
Fix address violation parsing a corrupt SOM binary.
PR binutils/21649
* som.c (setup_sections): NUL terminate the space_strings buffer.
Check that the space.name field does not index beyond the end of
the space_strings buffer.
Put into English, I wanted to make sure that the value of n passed to
do_something() is the same as the thread number shown in the "info
threads" Id column. (I've structured the test case so that this
*should* be the case.)
It didn't work though. It turned out that ($pattern) in the RE
noted above is capturing the attempted backreference. So, in this
case, the backreference does not refer to ([0-9]+) as intended, but
instead refers to ($pattern). This is wrong because it's not what I
intended, but is also wrong because, if allowed, it could only match a
string of infinite length.
This problem can be fixed by using parens for a "noncapturing
subpattern". The way that this is done, syntactically, is to use
(?:$pattern) instead of ($pattern).
My research shows that this feature has been present since tcl8.1 which
was released in 1999.
The current tcl version is 8.6 - at least that's what I have on my
machine. It appears to me that mingw uses some subversion of tcl8.4
which will also have this feature (since 8.4 > 8.1).
So it seems to me that any platform upon which we might wish to test
GDB will have a version of tcl which has this feature. That being the
case, my hope is that there won't be any objections to its use.
When I looked at the implementation of gdb_test, I wondered whether
the parens were needed at all. I've concluded that they are. In the
event that $pattern is an RE which uses alternation at the top level,
e.g. a|b, we need to make $pattern a subpattern (via parens) to limit
the extend of the alternation. I.e, we don't want the alternation to
extend to the other portions of the RE which gdb_test uses to match
potential blank lines at the beginning of the pattern or the gdb
prompt at the end.
gdb/testsuite/ChangeLog:
* gdb.exp (gdb_test): Using noncapturing parens for the $pattern
subpattern.
projects / thirdparty / binutils-gdb.git / log
