PR gold/21857
* compressed_output.cc (Output_compressed_section::set_final_data_size):
Call put_ch_reserved to clear the reserved field for 64-bit ELF.
Jiong Wang [Thu, 25 May 2017 09:40:07 +0000 (10:40 +0100)]
[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-A
Backport from mainline
2017-06-06 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
Han Shen [Mon, 10 Jul 2017 22:23:05 +0000 (15:23 -0700)]
Fixing for PR gold/21491 - Errata workaround can produce broken images.
The problem is caused by the fact that gold is relocating the stubs
for an entire output section when it processes the relocations for a
particular input section that happened to be designated as the stub
table "owner". The Relocate_task for that input section may or may not
run before the Relocate_task for another input section that contains
the code that needs the erratum fix, but doesn't "own" the stub
table. If it runs before (or might even race with) that other task, it
ends up with a copy of the unrelocated original instruction.
In other words - when calling fix_errata() from
do_relocate_sections(), gold is going through the list of errata stubs
that are associated only with that object. This routine updates the
stored original instruction and replaces it in the output view with a
branch to the stub. Later, as gold is going through the object file's
input sections, it then checks for stub tables "owned" by each input
section, and writes out all the stubs from that stub table, regardless
of what object file each stub is associated with.
Fixed by relocating the erratum stub only after the corresponding
errata spot is fixed. That is to have fix_errata() call
Stub_table::relocate_erratum_stub() for each stub.
gold/ChangeLog
2017-07-06 Han Shen <shenhan@google.com>
PR gold/21491
* aarch64.cc (Erratum_stub::invalidate_erratum_stub): New method.
(Erratum_stub::is_invalidated_erratum_stub): New method.
(Stub_table::relocate_reloc_stub): Renamed from "relocate_stub".
(Stub_table::relocate_reloc_stubs): Renamed from "relocate_stubs".
(Stub_table::relocate_erratum_stub): New method.
(AArch64_relobj::fix_errata_and_relocate_erratum_stubs): Renamed from
"fix_errata".
(Target_aarch64::relocate_reloc_stub): Renamed from "relocate_stub".
[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Eric Christopher [Tue, 20 Jun 2017 23:18:58 +0000 (16:18 -0700)]
2017-06-21 Eric Christopher <echristo@gmail.com>
Apply from master
2017-06-20 Eric Christopher <echristo@gmail.com>
* aarch64.cc (scan_reloc_for_stub): Use plt_address_for_global to
calculate the symbol value.
(scan_reloc_section_for_stubs): Allow stubs to be created for
section symbols.
(maybe_apply_stub): Handle creating stubs for weak symbols to
match the code in scan_reloc_for_stub.
Apply from master
2017-06-07 Eric Christopher <echristo@gmail.com>
* aarch64.cc (maybe_apply_stub): Add debug logging for looking
up stubs to undefined symbols and early return rather than
fail to look them up.
(scan_reloc_for_stub): Add debug logging for no stub creation
for undefined symbols.
The LDR rX, =cst pseudo-instruction suffers from two issues for loading
integer constants in Thumb mode:
- movs is used if the constant and register can be encoded using that
instruction which leads to unexpected behavior due to its flag-setting
behavior
- mov.w, movw and mvn are used for r13 (sp) and r15 (pc) but these
encoding are marked as UNPREDICTABLE
This patch fixes those issues and update testing accordingly.
2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
Backport from mainline
2017-04-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Remove code generating MOVS.
Forbid MOV.W and MOVW if destination is SP or PC.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: Explain
expectation of LDR not generating a MOVS for low registers and small
constants. Add tests of MOVW generation.
* testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: Update
expected disassembly.
For ELF targets --out-implib currently generates an executable file
(e_type is ET_EXEC) despite the file being expected to be linked against
some other object file to make an executable later. It seems therefore
more sensible to make the import library a relocatable object file
(e_type set to ET_REL).
Incidentally, as dicted by requirement 8 of
"ARM v8-M Security Extensions: Requirements on Development Tools"
(document ARM-ECM-0359818) version 1.0, import libraries generated when
using --cmse-implib *must* be relocatable object file so this commit
also adds an assert there in case the type of ELF import library is
changed again in the future.
2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
Backport from mainline
2017-05-08 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elflink.c (elf_output_implib): Remove executable flag from import
library bfd.
* elf32-arm.c (elf32_arm_filter_implib_symbols): Assert that the import
library is a relocatable object file.
gas/
* testsuite/ld-arm/arm-elf.exp
(Secure gateway import library generation): Check e_type field
of import library and executable produced.
* testsuite/ld-arm/cmse-implib.type: Expectations for e_type field.
James Clarke [Tue, 20 Jun 2017 08:31:52 +0000 (18:01 +0930)]
[GOLD] Avoid duplicate PLT stub symbols on ppc32
If two objects are compiled with -fPIC or -fPIE and call the same
function, two different PLT entries are created, one for each object,
but the same stub symbol name is used for both.
* powerpc.cc (Stub_table::define_stub_syms): Always include object's
uniq_ value.
Alan Modra [Wed, 17 May 2017 23:38:55 +0000 (09:08 +0930)]
PowerPC: incorrect library search order
First, need to match against just the CPU name, not the whole triplet.
Otherwise, the test picks up "*le-*" pattern from x86_64-apple-darwin
triplet.
Second, it should be testing for $target, not $host. Host may be
little endian by default, and the sysroot directory layout shouldn't
depend on whether it is built on LE or BE machine.
* emulparams/elf32ppccommon.sh (LIBPATH_SUFFIX): Set from target
cpu, not host.
James Clarke [Sat, 13 May 2017 15:01:15 +0000 (08:01 -0700)]
Fix assertion failure relaxing TLS for position-independent executables.
gold/
PR gold/21444
* gold.cc (Target_sparc::Relocate::relocate_tls): Local
variables are final for position-independent executables. This
has to be consistent with Target_sparc::Scan::local otherwise
they will disagree as to whether local-exec is used.
Fix PR21404 - assertion fail when calculating symbol size
Fix a host of problems related to adjustment of
symbol values and sizes when relaxing for avr.
1. Adjust symbol size first before adjusting symbol
value. Otherwise, a symbol whose value just got adjusted to the
relaxed address also ends up getting resized. See pr21404-1.s.
2. Reduce symbol sizes only if their span is below an
alignment boundary. Otherwise, the size gets decremented once when the
actual instruction is relaxed and padding bytes are added, and again
when the padding bytes are deleted (if padding ends up being unnecessary).
pr21404-2.s addresses that, and this bug is really the root cause of PR21404.
3. Adjust all symbol values before an alignment boundary.
Previous code did not adjust symbol values if they fell in the
would-be padded area, resulting in incorrect symbol values in some
cases (see pr21404-3.s).
4. Increase symbol sizes if alignment directives require so.
As pr21404-4.s shows
.global nonzero_sym
L1:
jmp L1
nonzero_sym:
nop
nop
.p2align 2
.size nonzero_sym, .-nonzero_sym
The two nops satisfy the 4 byte alignment at assembly time and
therefore the size of nonzero_sym is 4. Relaxation shortens
the 4 byte jmp to a 2 byte rjmp, and to satisfy 4 byte alignment
the code places 2 extra padding bytes after the nops, increasing
nonzero_sym's size by 2. This wasn't handled before.
If the assembly code does not have any align directives, then the
boundary is the section size, and symbol values and sizes == boundary
should also get adjusted. To handle that case, add a did_pad variable
and use that to determine whether it should use < boundary or <= boundary.
Also get rid of reloc_toaddr, which is now redundant. toaddr is now not
adjusted to handle the above case - the newly added
did_pad variable does the job.
pr21404-{5,6,7,8} are the same testcases written for local symbols, as
the code handles them slightly differently.
PR ld/21404
* elf32-avr.c (avr_should_move_sym): New function.
(avr_should_reduce_sym_size): Likewise.
(avr_should_increase_sym_size): Likewise.
(elf32_avr_relax_delete_bytes): Adjust symbol values
and sizes by calling new functions.
PR ld/21404
* testsuite/ld-avr/pr21404-1.d: New test.
* testsuite/ld-avr/pr21404-1.s: New test.
* testsuite/ld-avr/pr21404-2.d: New test.
* testsuite/ld-avr/pr21404-2.s: New test.
* testsuite/ld-avr/pr21404-3.d: New test.
* testsuite/ld-avr/pr21404-3.s: New test.
* testsuite/ld-avr/pr21404-4.d: New test.
* testsuite/ld-avr/pr21404-4.s: New test.
* testsuite/ld-avr/pr21404-5.d: New test.
* testsuite/ld-avr/pr21404-5.s: New test.
* testsuite/ld-avr/pr21404-6.d: New test.
* testsuite/ld-avr/pr21404-6.s: New test.
* testsuite/ld-avr/pr21404-7.d: New test.
* testsuite/ld-avr/pr21404-7.s: New test.
* testsuite/ld-avr/pr21404-8.d: New test.
* testsuite/ld-avr/pr21404-8.s: New test.
The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.
Palmer Dabbelt [Mon, 1 May 2017 17:26:32 +0000 (10:26 -0700)]
RISC-V: Allow 32-bit BFD to handle 64-bit objects
We've been telling people that the riscv32-* and riscv64-* toolchains
are exactly the same, but it turns out we were lying: the riscv32-* BFD
doesn't handle 64-bit objects. This fixes that difference, so the ports
are actually the same.
projects / thirdparty / binutils-gdb.git / log
