Bin Cheng [Mon, 17 Jul 2017 11:34:30 +0000 (11:34 +0000)]
re PR tree-optimization/81374 (ICE in bb_top_order_cmp, at tree-loop-distribution.c:391)
PR tree-optimization/81374
* tree-loop-distribution.c (pass_loop_distribution::execute): Record
the max index of basic blocks, rather than number of basic blocks.
This patch refactors a number of functions and compiler hooks into using a
single function which checks if a rtx is suited for pic or not. Removed
functions are arc_legitimate_pc_offset_p and arc_legitimate_pic_operand_p
beeing replaced by calls to arc_legitimate_pic_addr_p. Thus we have an
unitary way of checking a rtx beeing pic.
* config/arc/arc-protos.h (arc_legitimate_pc_offset_p): Remove
proto.
(arc_legitimate_pic_operand_p): Likewise.
* config/arc/arc.c (arc_legitimate_pic_operand_p): Remove
function.
(arc_needs_pcl_p): Likewise.
(arc_legitimate_pc_offset_p): Likewise.
(arc_legitimate_pic_addr_p): Remove LABEL_REF case, as this
function is also used in constrains.md.
(arc_legitimate_constant_p): Use arc_legitimate_pic_addr_p to
validate pic constants. Handle CONST_INT, CONST_DOUBLE, MINUS and
PLUS. Only return true/false in known cases, otherwise assert.
(arc_legitimate_address_p): Remove arc_legitimate_pic_addr_p as it
is already called in arc_legitimate_constant_p.
* config/arc/arc.h (CONSTANT_ADDRESS_P): Consider also LABEL for
pic addresses.
(LEGITIMATE_PIC_OPERAND_P): Use
arc_raw_symbolic_reference_mentioned_p function.
* config/arc/constraints.md (Cpc): Use arc_legitimate_pic_addr_p
function.
(Cal): Likewise.
(C32): Likewise.
Jakub Jelinek [Mon, 17 Jul 2017 09:10:23 +0000 (11:10 +0200)]
re PR tree-optimization/81365 (GCC miscompiles swap)
PR tree-optimization/81365
* tree-ssa-phiprop.c (propagate_with_phi): When considering hoisting
aggregate moves onto bb predecessor edges, make sure there are no
loads that could alias the lhs in between the start of bb and the
loads from *phi.
Jakub Jelinek [Mon, 17 Jul 2017 08:14:16 +0000 (10:14 +0200)]
re PR tree-optimization/81396 (Optimization of reading Little-Endian 64-bit number with portable code has a regression)
PR tree-optimization/81396
* tree-ssa-math-opts.c (struct symbolic_number): Add n_ops field.
(init_symbolic_number): Initialize it to 1.
(perform_symbolic_merge): Add n_ops from both operands into the new
n_ops.
(find_bswap_or_nop): Don't consider n->n == cmpnop computations
without base_addr as useless if they need more than one operation.
(bswap_replace): Handle !bswap case for NULL base_addr.
Sebastian Huber [Mon, 17 Jul 2017 05:27:13 +0000 (05:27 +0000)]
[SPARC/RTEMS] Add __FIX_LEON3FT_B2BST
In case the LEON3FT back-to-back store workaround is active
(sparc_fix_b2bst), then define the builtin define __FIX_LEON3FT_B2BST on
RTEMS. The intended use case for this is operating system code in
assembly language. See also:
Eric Botcazou [Sun, 16 Jul 2017 22:03:54 +0000 (22:03 +0000)]
re PR rtl-optimization/81424 (internal error on GPRbuild with -O2)
PR rtl-optimization/81424
* optabs.c (prepare_cmp_insn): Use copy_to_reg instead of force_reg
to remove potential trapping from operands if -fnon-call-exceptions.
* parser.c (cp_parser_cast_expression): Use %q#T instead of %qT
in old-style cast diagnostic.
* typeck.c (maybe_warn_about_useless_cast): Use %q#T instead of %qT
in useless cast diagnostic.
* error.c (type_to_string): Remove enum special handling.
* g++.dg/cpp1z/direct-enum-init1.C: Revert special enum handling.
* g++.dg/warn/pr12242.C: Likewise.
parser.c (cp_parser_cast_expression): Use %q#T instead of %qT in old-style cast diagnostic.
* parser.c (cp_parser_cast_expression): Use %q#T instead of %qT
in old-style cast diagnostic.
* typeck.c (maybe_warn_about_useless_cast): Use %q#T instead of %qT
in useless cast diagnostic.
* error.c (type_to_string): Remove enum special handling.
* g++.dg/cpp1z/direct-enum-init1.C: Revert special enum handling.
* g++.dg/warn/pr12242.C: Likewise.
Ian Lance Taylor [Fri, 14 Jul 2017 22:25:26 +0000 (22:25 +0000)]
libgo: don't copy semt into runtime.inc
https://gcc.gnu.org/PR81449 reports a problem with the definition semt
in runtime.inc on some systems. Since the C code in libgo/runtime
doesn't need semt, just don't copy it into runtime.inc.
rs6000-c.c (altivec_overloaded_builtins): Add array entries to represent __ieee128 versions of the scalar_test_data_class...
gcc/ChangeLog:
2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
array entries to represent __ieee128 versions of the
scalar_test_data_class, scalar_test_neg, scalar_extract_exp,
scalar_extract_sig, and scalar_insert_exp built-in functions.
(altivec_resolve_overloaded_builtin): Add special case handling
for the __builtin_scalar_insert_exp function, as represented by
the P9V_BUILTIN_VEC_VSIEDP constant.
* config/rs6000/rs6000-builtin.def (VSEEQP): Add scalar extract
exponent support for __ieee128 argument.
(VSESQP): Add scalar extract signature support for __ieee128
argument.
(VSTDCNQP): Add scalar test negative support for __ieee128
argument.
(VSIEQP): Add scalar insert exponent support for __int128 argument
with __ieee128 result.
(VSIEQPF): Add scalar insert exponent support for __ieee128
argument with __ieee128 result.
(VSTDCQP): Add scalar test data class support for __ieee128
argument.
(VSTDCNQP): Add overload support for scalar test negative with
__ieee128 argument.
(VSTDCQP): Add overload support for scalar test data class
__ieee128 argument.
* config/rs6000/vsx.md (UNSPEC_VSX_SXSIG) Replace
UNSPEC_VSX_SXSIGDP.
(UNSPEC_VSX_SIEXPQP): New constant.
(xsxexpqp): New insn for VSX scalar extract exponent quad
precision.
(xsxsigqp): New insn for VSX scalar extract significand quad
precision.
(xsiexpqpf): New insn for VSX scalar insert exponent quad
precision with floating point argument.
(xststdcqp): New expand for VSX scalar test data class quad
precision.
(xststdcnegqp): New expand for VSX scalar test negative quad
precision.
(xststdcqp): New insn to match expansions for VSX scalar test data
class quad precision and VSX scalar test negative quad precision.
* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add
special case operand checking to enforce that second operand of
VSX scalar test data class with quad precision argument is a 7-bit
unsigned literal.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Add
prototypes and descriptions of __ieee128 versions of
scalar_extract_exp, scalar_extract_sig, scalar_insert_exp,
scalar_test_data_class, and scalar_test_neg built-in functions.
gcc/testsuite/ChangeLog:
2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-14.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-15.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-10.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-11.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-12.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-13.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-14.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-15.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-4.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-6.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-7.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-8.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-9.c: New test.
Jason Merrill [Fri, 14 Jul 2017 19:13:49 +0000 (15:13 -0400)]
Constrain std::variant constructor for class template argument deduction
2017-07-14 Jason Merrill <jason@redhat.com>
Jonathan Wakely <jwakely@redhat.com>
* include/std/variant (variant::variant(_Tp&&)): Constrain to remove
the constructor for empty variants from the candidate functions
during class template argument deduction.
* testsuite/20_util/variant/deduction.cc: New.
Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>
From-SVN: r250213
[ARM] Fix definition of __ARM_FEATURE_NUMERIC_MAXMIN
Definition of __ARM_FEATURE_NUMERIC_MAXMIN checks for
TARGET_ARM_ARCH >= 8 and TARGET_NEON being true in addition to
TARGET_VFP5. However, instructions covered by this macro are part of
FPv5 which is available in ARMv7E-M architecture. This commit fixes the
macro to only check for TARGET_VFP5.
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_NUMERIC_MAXMIN solely based on TARGET_VFP5.
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-cpus.in (cortex-r52): Add new entry.
(armv8-r): Set ARM Cortex-R52 as default CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
Cortex-R52.
* doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
extension for -mcpu=cortex-r52.
fp-armv8 is currently defined as a double precision FPv5 with 32 D
registers *and* a special FP_ARMv8 bit. However FP for ARMv8 should only
bring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is
spurious. As a consequence, many instruction patterns which are guarded
by TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.
This commit gets rid of TARGET_FPU_ARMV8 and rewire all uses to
expressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.
It also redefine ISA_FP_ARMv8 to include the D32 capability to
distinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to
enable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D
registers).
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
(ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
* config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
(fp-armv8): Define it as FP_ARMv8 only.
config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
(TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
TARGET_FPU_ARMV8.
config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
* config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
than TARGET_FPU_ARMV8.
* config/arm/arm-c.c (arm_cpu_builtins): Likewise for
__ARM_FEATURE_NUMERIC_MAXMIN macro definition.
* config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
TARGET_FPU_ARMV8.
* config/arm/neon.md (neon_vrint): Likewise.
(neon_vcvt): Likewise.
(neon_<fmaxmin_op><mode>): Likewise.
(<fmaxmin><mode>3): Likewise.
* config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
* config/arm/predicates.md (arm_cond_move_operator): Check against
TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.
David Malcolm [Fri, 14 Jul 2017 15:09:00 +0000 (15:09 +0000)]
c/c++: Add fix-it hints for suggested missing #includes
gcc/c-family/ChangeLog:
* c-common.c (try_to_locate_new_include_insertion_point): New
function.
(per_file_includes_t): New typedef.
(added_includes_t): New typedef.
(added_includes): New variable.
(maybe_add_include_fixit): New function.
* c-common.h (maybe_add_include_fixit): New decl.
gcc/c/ChangeLog:
* c-decl.c (implicitly_declare): When suggesting a missing
#include, provide a fix-it hint.
gcc/cp/ChangeLog:
* name-lookup.c (get_std_name_hint): Add '<' and '>' around
the header names.
(maybe_suggest_missing_header): Update for addition of '<' and '>'
to above. Provide a fix-it hint.
* pt.c: Include "gcc-rich-location.h"
(listify): Attempt to add fix-it hint for missing
#include <initializer_list>.
* rtti.c: Include "gcc-rich-location.h".
(typeid_ok_p): Attempt to add fix-it hint for missing
#include <typeinfo>.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/missing-initializer_list-include.C: New test case.
* g++.dg/lookup/missing-std-include-2.C: New test case.
* g++.dg/lookup/missing-std-include-3.C: New test case.
* g++.dg/rtti/missing-typeinfo-include.C: New test case.
* gcc.dg/missing-header-fixit-1.c: New test case.
* gcc.dg/missing-header-fixit-2.c: New test case.
* gcc.dg/missing-header-fixit-2.h: New header.
Jakub Jelinek [Fri, 14 Jul 2017 09:10:45 +0000 (11:10 +0200)]
re PR sanitizer/81066 (sanitizer_stoptheworld_linux_libcdep.cc:276:22: error: aggregate ‘sigaltstack handler_stack’ has incomplete type and cannot be defined)
Martin Liska [Fri, 14 Jul 2017 07:44:33 +0000 (09:44 +0200)]
Remove Java references in source code.
2017-07-14 Martin Liska <mliska@suse.cz>
* cfgexpand.c (expand_gimple_basic_block): Remove dead comment.
* dwarf2out.c (is_java): Remove the function.
(output_pubname): Remove usage of the function.
(lower_bound_default): Remove usage of DW_LANG_Java.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove compiler defaults for .java and .zip files.
* gimple-expr.c (remove_suffix): Change as there's no longer
extension than 4-letter one.
* gimplify.c (mostly_copy_tree_r): Remove Java-special part.
(gimplify_save_expr): Likewise.
* ipa-utils.h (polymorphic_type_binfo_p): Remove the comment
as it's possible even for other languages than Java.
* langhooks.h (struct lang_hooks): Remove Java from a comment.
* lto-opts.c (lto_write_options): Remove reference to Java.
* opts.c (strip_off_ending): Update file extension handling.
* tree-cfg.c (verify_gimple_call): Remove comment with Java.
* tree-eh.c (lower_resx): Likewise.
* tree.c (free_lang_data_in_type): Remove dead code.
(find_decls_types_r): Likewise.
(build_common_builtin_nodes): Remove Java from a comment.
(verify_type): Remove dead code.
* varasm.c (assemble_external): Remove Java from a comment.
Martin Liska [Fri, 14 Jul 2017 07:05:27 +0000 (09:05 +0200)]
Remove Pascal language in source code.
2017-07-14 Martin Liska <mliska@suse.cz>
* dbxout.c (get_lang_number): Do not handle GNU Pascal.
* dbxout.h (extern void dbxout_stab_value_internal_label_diff):
Remove N_SO_PASCAL.
* dwarf2out.c (lower_bound_default): Do not handle
DW_LANG_Pascal83.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove default extension binding for GNU Pascal.
* stmt.c: Remove Pascal language from a comment.
* xcoffout.c: Likewise.
David Malcolm [Thu, 13 Jul 2017 19:30:42 +0000 (19:30 +0000)]
diagnostics: fix crash when consolidating out-of-order fix-it hints (PR c/81405)
PR c/81405 identifies a crash when printing fix-it hints from
-Wmissing-braces when there are excess elements.
The fix-it hints are bogus (which I've filed separately as PR c/81432),
but they lead to a crash within the fix-it consolidation logic I added
in r247548, in line_corrections::add_hint.
The root cause is that some of the fix-it hints are out-of-order
with respect to the column numbers they affect, which can lead to negative
values when computing the gap between the fix-it hints, leading to bogus
memcpy calls that generate out-of-bounds buffer accesses.
The fix is to sort the fix-it hints after filtering them, ensuring that
the gap >= 0. The patch also adds numerous assertions to the code, both
directly, and by moving the memcpy calls and their args behind
interfaces (themselves containing gcc_assert).
This fixes the crash; it doesn't fix the bug in -Wmissing-braces that
leads to the bogus hints.
gcc/ChangeLog:
PR c/81405
* diagnostic-show-locus.c (fixit_cmp): New function.
(layout::layout): Sort m_fixit_hints.
(column_range::column_range): Assert that the values are valid.
(struct char_span): New struct.
(correction::overwrite): New method.
(struct source_line): New struct.
(line_corrections::add_hint): Add assertions. Reimplement memcpy
calls in terms of classes source_line and char_span, and
correction::overwrite.
(selftest::test_overlapped_fixit_printing_2): New function.
(selftest::diagnostic_show_locus_c_tests): Call it.
Richard Earnshaw [Thu, 13 Jul 2017 10:01:55 +0000 (10:01 +0000)]
[ARM, VXworks] Fix build
My patch last week to address selection of be8 linking mode broke the
build for vxworks. It turns out that this port is one of the few
remaining that is still not based on the EABI/AAPCS.
This patch fixes the build, but I've not really tested it beyond
building the core compiler binaries. Building a workable compiler
entails downloading a load of vxworks stuff that I'm not sure where to
find.
Michael Meissner [Wed, 12 Jul 2017 23:07:50 +0000 (23:07 +0000)]
re PR target/81193 (PowerPC GCC __builtin_cpu_is and __builtin_cpu_supports should warn about old libraries)
[gcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
provides the hardware capability bits, define the macro
__BUILTIN_CPU_SUPPORTS__.
* config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
if GLIBC does not provide the hardware capability bits. Add a
gcc_unreachable call if the built-in cpu function is neither
__builtin_cpu_is nor __builtin_cpu_supports.
(rs6000_get_function_versions_dispatcher): Change the warning
that an old GLIBC is used which does not export the capability
bits to be an error.
* doc/extend.texi (target_clones attribute): Document the
restriction that GLIBC 2.23 or newer is needed on the PowerPC.
(PowerPC built-in functions): Document that GLIBC 2.23 or newer is
needed by __builtin_cpu_is and __builtin_cpu_supports. Document
the macros defined by GCC if the newer GLIBC is available.
[gcc/testsuite]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
[libgcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* configure.ac (PowerPC float128 hardware support): Test whether
we can use __builtin_cpu_supports before enabling the ifunc
handler.
* configure: Regenerate.
re PR target/79883 (avr i18n: untranslated "interrupt" or "signal")
PR target/79883
* config/avr/avr.c (avr_set_current_function): In diagnostic
messages: Quote keywords and (parts of) identifiers.
[WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or
"INTERUPT".
Carl Love [Wed, 12 Jul 2017 15:10:21 +0000 (15:10 +0000)]
rs6000-c.c: Add support for built-in functions vector bool char vec_revb (vector bool char)...
gcc/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_revb (vector bool char);
vector bool short vec_revb (vector short char);
vector bool int vec_revb (vector bool int);
vector bool long long vec_revb (vector bool long long);
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/p9-xxbr-1.c (rev_bool_char, rev_bool_short,
rev_bool_int): Add test cases for builtins.
* gcc.target/powerpc/p9-xxbr-2.c (rev_long_long, rev_ulong_ulong): Add
test cases for builtins.
Andreas Krebbel [Wed, 12 Jul 2017 15:00:58 +0000 (15:00 +0000)]
S/390: Remove loc splitter
The backend splitter splitting a 3 operand load on condition into 2 is
wrong. The S/390 load on condition instruction might trap on the
memory operand even if the condition is false. So if the first load
on condition overwrites a register used as part of the memory address
of the second the second might trigger a segfault even if it does not
actually perform the load.
Trying to fix this I noticed that the generated code looks anyway
better without the splitter. So removing the splitter entirely is the
way to go here.
gcc/ChangeLog:
2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Carl Love [Tue, 11 Jul 2017 14:53:06 +0000 (14:53 +0000)]
rs6000-c.c: Add support for builtins vector unsigned int vec_parity_lsbb (vector signed int)...
gcc/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for builtins
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
vector unsigned long long vec_parity_lsbb (vector signed long long);
vector unsigned long long vec_parity_lsbb (vector unsigned long long);
* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
test cases for the builtins.
David Malcolm [Tue, 11 Jul 2017 13:43:31 +0000 (13:43 +0000)]
diagnostics: support compact printing of secondary locations
gcc/ChangeLog:
* diagnostic-show-locus.c: Include "gcc-rich-location.h".
(layout::m_primary_loc): New field.
(layout::layout): Initialize new field. Move location filtering
logic from here to...
(layout::maybe_add_location_range): ...this new method. Add
support for filtering to just the lines already specified by other
locations.
(layout::will_show_line_p): New method.
(selftest::test_add_location_if_nearby): New test function.
(selftest::diagnostic_show_locus_c_tests): Call it.
* gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
New method.
Tom de Vries [Tue, 11 Jul 2017 12:25:01 +0000 (12:25 +0000)]
Add extra initialization of broadcasted condition variables
2017-07-11 Tom de Vries <tom@codesourcery.com>
* config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG): New macro.
(bb_first_real_insn): New function.
(nvptx_single): Add extra initialization of broadcasted condition
variables.
Daniel Cederman [Tue, 11 Jul 2017 07:18:50 +0000 (07:18 +0000)]
sparc.opt (mfix-ut700): New option.
* config/sparc/sparc.opt (mfix-ut700): New option.
(mfix-gr712rc): Likewise.
(sparc_fix_b2bst): New variable.
* doc/invoke.texi (SPARC options): Document them.
(ARM options): Fix warnings.
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(pass_work_around_errata::gate): Also test sparc_fix_b2bst.
(sparc_option_override): Set sparc_fix_b2bst appropriately.
* config/sparc/sparc.md (fix_b2bst): New attribute.
(in_branch_delay): Prevent stores in delay slot if fix_b2bst.
projects / thirdparty / gcc.git / log
