doesn't with i686-elf cross binutils on 64-bit hosts:
evex-no-scale.s: Assembler messages:
evex-no-scale.s:10: Error: bad register name `%rip)'
evex-no-scale.s:11: Error: bad register name `%rax)'
evex-no-scale.s:12: Error: bad register name `%riz)'
This patch replaces evex-no-scale.s with evex-no-scale-32.s and
evex-no-scale-64.s.
* testsuite/gas/i386/evex-no-scale-32.d: Don't use
evex-no-scale.s.
* testsuite/gas/i386/evex-no-scale-64.d: Likewise.
* testsuite/gas/i386/evex-no-scale-32.s: New file.
* testsuite/gas/i386/evex-no-scale-64.s: Likewise.
* testsuite/gas/i386/evex-no-scale.s: Removed.
H.J. Lu [Wed, 8 Aug 2018 13:09:15 +0000 (06:09 -0700)]
x86: Properly merge GNU_PROPERTY_X86_ISA_1_USED
Without the GNU_PROPERTY_X86_ISA_1_USED property, all ISAs may be used.
If a bit in the GNU_PROPERTY_X86_ISA_1_USED property is unset, the
corresponding x86 instruction set isn’t used. When merging properties
from 2 input files and one input file doesn't have the
GNU_PROPERTY_X86_ISA_1_USED property, the output file shouldn't have
it neither. This patch removes the GNU_PROPERTY_X86_ISA_1_USED
property if an input file doesn't have it.
This patch replaces the GNU_PROPERTY_X86_ISA_1_USED property with the
GNU_PROPERTY_X86_ISA_1_NEEDED property which is the minimum ISA
requirement.
bfd/
PR ld/23486
* elfxx-x86.c (_bfd_x86_elf_merge_gnu_properties): Remove
GNU_PROPERTY_X86_ISA_1_USED if an input file doesn't have it.
(_bfd_x86_elf_link_setup_gnu_properties): Adding the
GNU_PROPERTY_X86_ISA_1_NEEDED, instead of
GNU_PROPERTY_X86_ISA_1_USED, property.
Alan Modra [Sun, 5 Aug 2018 10:14:03 +0000 (19:44 +0930)]
__tls_get_addr_opt stubs and tocsave optimization
This patch fixes a bug in the handling of the __tls_get_addr_opt
stub. Calls via this stub don't have a toc restoring instruction
following the "bl", and the stub itself doesn't have an initial toc
save instruction. Thus it is incorrect to skip over the first
instruction when a __tls_get_addr call is marked with a tocsave
reloc.
* elf64-ppc.c (ppc64_elf_relocate_section): Don't skip first
instruction of __tls_get_addr_opt stub.
(plt_stub_size): Omit ALWAYS_EMIT_R2SAVE condition when
dealing with __tls_get_addr_opt stub.
(build_tls_get_addr_stub, ppc_size_one_stub): Likewise.
The modified test failed on some powerpc targets due to differences in
default hash style. If the default hash style is both, then more
sections are created, bumping section ids. Section id is used in stub
symbols and although the test is careful to not depend on id in
labels, the stub hash traversal order changes when stub names change.
That lead to the stubs being emitted in a different order and thus not
matching expected output.
* testsuite/ld-powerpc/powerpc.exp: Run tlsopt5 with hash-style
specified.
Alan Modra [Wed, 1 Aug 2018 02:44:22 +0000 (12:14 +0930)]
PowerPC64 __tls_get_addr_opt stub .eh_frame fix
This patch sets stub_offset in ppc_size_one_stub rather than in
ppc_build_one_stub. That allows the plt stub alignment to be done in
just ppc_size_one_stub rather than both functions. The patch also
corrects the place where the alignment was done, fixing a possible
error in .eh_frame data, and tidies some offset calculations.
bfd/
* elf64-ppc.c (plt_stub_pad): Delay plt_stub_size call until needed.
(ppc_build_one_stub): Don't set stub_offset, instead assert that
it is sane. Don't adjust stub_offset for alignment. Adjust size
calculation. Use "targ" temp when calculating offsets.
(ppc_size_one_stub): Set stub_offset here. Use "targ" temp when
calculating offsets. Adjust for alignment before setting
tls_get_addr_opt_bctrl.
ld/
* testsuite/ld-powerpc/powerpc.exp: Run tlsopt5 with plt alignment.
* testsuite/ld-powerpc/tlsopt5.s: Add extra call.
* testsuite/ld-powerpc/tlsopt5.wf: Adjust expected output.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
Cary Coutant [Mon, 6 Aug 2018 20:36:42 +0000 (13:36 -0700)]
Fix type checking errors.
gold/
* target.h (Sized_target::record_gnu_property): Change first two
parameters to unsigned int.
* x86_64.cc (Target_x86_64::record_gnu_property): Likewise.
This patch fixes some ifunc testisms after H.J. Lu's patch to enable the
use of IFUNC pointers in position dependent code for binutils. See PR
LD/23169 in binutils bugzilla.
The aarch64 ifunc error message test was changed to no longer expect
this error message as this is now an accepted combination. This patch
also disables the executable tests added by H.J. Lu for aarch64, just as
Alan Modra did with his patch, as these tests only seem to work on some
architectures.
ld/ChangeLog:
2018-07-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/ld-aarch64/ifunc-9.d: Remove no longer expected error.
* testsuite/ld-ifunc/ifunc.exp: Disable tests for aarch64.
In commit b5014f7af2 I've removed (instead of replaced) a conditional,
resulting in addressing forms not allowing 8-bit displacements to now
get their displacements scaled under certain circumstances. Re-add the
missing conditional.
* config/tc-hppa.c: Include "struc-symbol.h".
(pa_build_unwind_subspace): Use call_info->start_symbol->sy_frag
instead of frag_now for local symbol replacement.
H.J. Lu [Fri, 20 Jul 2018 16:18:47 +0000 (09:18 -0700)]
x86: Add a GNU_PROPERTY_X86_ISA_1_USED note if needed
When -z separate-code, which is enabled by default for Linux/x86, is
used to create executable, ld won't place any data in the code-only
PT_LOAD segment. If there are no data sections placed before the
code-only PT_LOAD segment, the program headers won't be mapped into
any PT_LOAD segment. When the executable tries to access it (based
on the program header address passed in AT_PHDR), it will lead to
segfault. This patch inserts a GNU_PROPERTY_X86_ISA_1_USED note if
there may be no data sections before the text section so that the
first PT_LOAD segment won't be code-only and will contain the program
header.
Testcases are adjusted to either pass "-z noseparate-code" to ld or
discard the .note.gnu.property section. A Linux/x86 run-time test is
added.
bfd/
PR ld/23428
* elfxx-x86.c (_bfd_x86_elf_link_setup_gnu_properties): If the
separate code program header is needed, make sure that the first
read-only PT_LOAD segment has no code by adding a
GNU_PROPERTY_X86_ISA_1_USED note.
ld/
PR ld/23428
* testsuite/ld-elf/linux-x86.S: New file.
* testsuite/ld-elf/linux-x86.exp: Likewise.
* testsuite/ld-elf/pr23428.c: Likewise.
* testsuite/ld-elf/sec64k.exp: Pass "-z noseparate-code" to ld
for Linux/x86 targets.
* testsuite/ld-i386/abs-iamcu.d: Likewise.
* testsuite/ld-i386/abs.d: Likewise.
* testsuite/ld-i386/pr12718.d: Likewise.
* testsuite/ld-i386/pr12921.d: Likewise.
* testsuite/ld-x86-64/abs-k1om.d: Likewise.
* testsuite/ld-x86-64/abs-l1om.d: Likewise.
* testsuite/ld-x86-64/abs.d: Likewise.
* testsuite/ld-x86-64/pr12718.d: Likewise.
* testsuite/ld-x86-64/pr12921.d: Likewise.
* testsuite/ld-linkonce/zeroeh.ld: Discard .note.gnu.property
section.
* testsuite/ld-scripts/print-memory-usage.t: Likewise.
* testsuite/ld-scripts/size-2.t: Likewise.
* testsuite/lib/ld-lib.exp (run_ld_link_exec_tests): Use ld
to create executable if language is "asm".
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these
RegXMM|...|Xmmword|...
and
RegXMM|...
The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.
gas/
PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.
Nick Clifton [Mon, 16 Jul 2018 13:29:26 +0000 (14:29 +0100)]
Import patch from mainline to fix gold's handling of already versioned symbols.
gold PR gold/23409
* symtab.cc (Symbol_table::define_special_symbol): Add check for
version name on existing symbol.
* testsuite/Makefile.am (ver_test_pr23409): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/ver_test_pr23409.sh: New test script.
* testsuite/ver_test_pr23409_1.script: New version script.
* testsuite/ver_test_pr23409_2.script: New version script.
Nick Clifton [Fri, 13 Jul 2018 10:44:49 +0000 (11:44 +0100)]
Allow bit-patterns in the immediate field of ARM neon mov instructions.
* config/tc-arm.c (do_neon_mov): When converting an integer
immediate into a floating point value, check that the conversion
is valid. Also warn if the immediate is valid as both a floating
point value and a bit pattern.
* testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use
floating point bit patterns.
* testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly
of the new insns.
Alan Modra [Tue, 3 Jul 2018 02:48:10 +0000 (12:18 +0930)]
Hide dynamic symbols in discarded sections
This is a followup to git commit 97196564c7 "Strip global symbol
defined in discarded section". If a symbol defined in a discarded
section was dynamic, that patch left .dynsym with holes (ie. all zero
entries). For example, the following from libstdc++.so:
Symbol table '.dynsym' contains 6090 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000000a74e0 0 SECTION LOCAL DEFAULT 10
2: 0000000000264180 0 SECTION LOCAL DEFAULT 17
3: 0000000000000000 0 NOTYPE WEAK DEFAULT UND _ITM_addUserCommitAction
4: 0000000000000000 0 NOTYPE WEAK DEFAULT UND _ITM_memcpyRtWn
5: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
readelf: Warning: local symbol 5 found at index >= .dynsym's sh_info value of 3
6: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
readelf: Warning: local symbol 6 found at index >= .dynsym's sh_info value of 3
[snip]
Tamar Christina [Thu, 12 Jul 2018 09:28:46 +0000 (10:28 +0100)]
Add remainder of Em16 restrictions for AArch64 gas.
This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.
The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.
The list has been cross checked (by hand) through the Arm ARM version Ca.
Max Filippov [Mon, 2 Jul 2018 18:12:44 +0000 (11:12 -0700)]
xtensa: don't emit dynamic relocation for weak undefined symbol
Resolved reference to a weak undefined symbol in PIE must not have
a dynamic relative relocation against itself, otherwise the value of a
reference will be changed from 0 to the base of executable, breaking
code like the following:
void weak_function (void);
if (weak_function)
weak_function ();
This fixes tests for PR ld/22269 and a number of PIE tests in xtensa gcc
testsuite.
bfd/
2018-07-11 Max Filippov <jcmvbkbc@gmail.com>
* elf32-xtensa.c (elf_xtensa_allocate_dynrelocs): Don't allocate
space for dynamic relocation for undefined weak symbol.
(elf_xtensa_relocate_section): Don't emit R_XTENSA_RELATIVE
relocation for undefined weak symbols.
(shrink_dynamic_reloc_sections): Don't shrink dynamic relocation
section for relocations against undefined weak symbols.
Franz Sirl [Wed, 24 Jan 2018 13:39:11 +0000 (13:39 +0000)]
Fix printing the size of GOLD's memory areana on Cygwin based systems.
I just stumbled over this with 2.29.1 while building a cross-toolchain, on Cygwin64, but it's still the same for 2.30. m.arena has size_t on Cygwin64 and thus errors out due to -Werror=format.
BFD/ELF: Correct a `remove' global shadowing error for pre-4.8 GCC
Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../bfd/elflink.c: In function 'bfd_elf_final_link':
.../bfd/elflink.c:11722: error: declaration of 'remove' shadows a global declaration
/usr/include/stdio.h:154: error: shadowed declaration is here
which for versions of GCC before 4.8 prevent support for ELF targets
from being built. See also GCC PR c/53066.
bfd/
* elflink.c (bfd_elf_final_link): Rename `remove' local variable
to `remove_section'.
Testing for the GCC version 5 or later isn't right, since C++ 11 support
wasn't enabled by default until later. This patch tests the C++ standard
support directly instead of inferring it from the GCC version.
gold/
* incremental.cc (Sized_incremental_binary::setup_readers): Use
emplace_back for C++ 11 or later.
Alan Modra [Fri, 6 Jul 2018 05:37:08 +0000 (15:07 +0930)]
Fix diagnostic errors
Fixes a number of build errors like the following
.../elf32-arm.c: In function 'elf32_arm_nabi_write_core_note':
.../elf32-arm.c:2177: error: #pragma GCC diagnostic not allowed inside functions
.../elf32-arm.c:2186: error: #pragma GCC diagnostic not allowed inside functions
See the comment in diagnostics.h.
Tamar Christina [Fri, 6 Jul 2018 15:15:41 +0000 (16:15 +0100)]
Fix the read/write flag for these registers on AArch64
The previous constraints were based on information already in opcodes and it
seems that a few of them were wrong. I have now hand verified the ones changed
by the previous patch and corrected where needed.
This prevents a warning to be issued when one shouldn't be.
projects / thirdparty / binutils-gdb.git / log
