Add nodes for four WSA8845 speakers. Unlike previous boards like
SM8550-QRD, this board has four speakers spread over two Soundwire buses
instead of two speakers on one bus. Each pair of speakers shares the
reset GPIO thus pinctrl property is only in one of them.
Add nodes for LPASS Soundwire v2.0.0 controllers. Difference against
SM8550:
1. Update port configs to match reference implementation,
2. LPASS TLMM GPIO14 is not used as WCD_SR_TX_DATA2 pin but as GPIO
(camera).
Isaev Ruslan [Wed, 15 Nov 2023 15:38:53 +0000 (18:38 +0300)]
arm64: dts: qcom: ipq6018: add QUP5 I2C node
Add node to support this bus inside of IPQ6018.
For example, this bus is used to work with the
voltage regulator (mp5496) on the Yuncore AX840 wireless AP.
Ninad Naik [Thu, 25 Jan 2024 05:51:34 +0000 (11:21 +0530)]
arm64: dts: qcom: sa8775p: Add new memory map updates to SA8775P
New memory map layout changes (by Qualcomm firmware) have brought
in updates to base addresses and/or size for different memory regions
like cpcucp_fw, tz-stat, and also introduces new memory regions for
resource manager firmware. The updated memory map also fixes existing
issues pertaining to boot up failure while running memtest, thus
improving stability.
This change brings in these corresponding memory map updates to the
device tree for SA8775P SoC platform, which currently is in its
development stage.
Neil Armstrong [Thu, 25 Jan 2024 16:55:04 +0000 (17:55 +0100)]
arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.
The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.
Like SM8450 & SM8550, the IDs are swapped, but works fine on PCIe0 and PCIe1.
Neil Armstrong [Tue, 23 Jan 2024 13:21:15 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8650-qrd: add USB-C Altmode Support
Add the necessary nodes to support the USB-C Altmode path by
adding the following
- WCD939x USBSS Mux I2C device
- nb7vpq904m Redriver I2C device
- Port/Endpoint graph links bettween PMIC-Glink, Mux, Redriver and USB PHY nodes.
WCD939x USBSS port 2 Path to Codec will be added later when Audio support
is added.
Dmitry Baryshkov [Tue, 16 Jan 2024 01:10:57 +0000 (03:10 +0200)]
arm64: dts: qcom: sdm630: add USB QMP PHY support
Define USB3 QMP PHY presend on the SDM630 / SDM660 platforms. Enable it by
default in the USB3 host, but (for compatibility), force USB 2.0 mode
for all defined boards. The boards should opt-in to enable USB 3.0
support.
Bjorn Andersson [Thu, 25 Jan 2024 21:05:13 +0000 (13:05 -0800)]
arm64: dts: qcom: sa8295p-adp: Enable GPU
With the necessary support in place for supplying VDD_GFX from the
MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU
and the GPU on the SA8295P ADP.
Bjorn Andersson [Thu, 25 Jan 2024 21:05:11 +0000 (13:05 -0800)]
arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc
The SA8295P and SA8540P uses an external regulator (max20411), and
gfx.lvl is not provided by rpmh. Drop the power-domains property of the
gpucc node to reflect this.
Luca Weiss [Wed, 10 Jan 2024 15:21:19 +0000 (16:21 +0100)]
arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbn
Specify the file name for the squashed/non-split firmware with the .mbn
extension instead of the split .mdt. The kernel can load both but the
squashed version is preferred in dts nowadays.
Dmitry Baryshkov [Sun, 28 Jan 2024 01:32:45 +0000 (03:32 +0200)]
arm64: dts: qcom: rename PM2250 to PM4125
It seems, the only actual mentions of PM2250 can be found are related to
the Qualcomm RB1 platform. However even RB1 schematics use PM4125 as a
PMIC name. Rename PM2250 to PM4125 to follow the documentation.
Note, this doesn't change the compatible strings. There was a previous
argument regarding renaming of compat strings.
Via the PMIC GLINK driver we can get info about fuel gauge, charger and
USB connector events. Add the node to the dts and configure USB so that
role switching works.
David Heidelberg [Fri, 29 Dec 2023 20:02:33 +0000 (21:02 +0100)]
arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming
Make it easier to understand what the reg in those nodes is by using the
constants provided by qcom,q6dsp-lpass-ports.h.
Name nodes according to dt-binding expectations.
Fix for
```
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb: service@4: dais: Unevaluated properties are not allowed ('qi2s@22', 'qi2s@23' were unexpected)
```
Luca Weiss [Fri, 29 Dec 2023 08:51:37 +0000 (09:51 +0100)]
arm64: dts: qcom: sc7280: Add static properties to cryptobam
When the properties num-channels & qcom,num-ees are not specified, the
driver tries to read the values from registers, but this read fails and
resets the device if the interconnect from the qcom,qce node is not
already active when that happens.
Add the static properties to not touch any registers during probe, the
rest of the time when the BAM is used by QCE then the interconnect will
be active already.
Stephan Gerhold [Fri, 22 Sep 2023 15:11:56 +0000 (17:11 +0200)]
arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node names
Add "regulator" to the node names of the fixed regulators, and drop the
"_rear" part of the camera node name since it is not part of the class
of the device (which is simply "camera").
arm64: dts: qcom: sm8650: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.
arm64: dts: qcom: sm8550: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Only
boot tested on hardware.
arm64: dts: qcom: sm8450: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Only
boot tested on hardware.
arm64: dts: qcom: sm8350: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.
arm64: dts: qcom: sm8250: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.
PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom:
sm8250: provide additional MSI interrupts").
arm64: dts: qcom: sm8150: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.
arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones
Due to lack of documentation the AMIC4 and AMIC5 analogue microphones
were never actually working, so the audio routing for them was added
hoping it is correct. It turned out not correct - their routing should
point to SWR_INPUT0 (so audio mixer TX SMIC MUX0 = SWR_MIC0) and
SWR_INPUT1 (so audio mixer TX SMIC MUX0 = SWR_MIC1), respectively. With
proper mixer settings and fixed LPASS TX macr codec TX SMIC MUXn
widgets, this makes all microphones working on HDK8450.
Konrad Dybcio [Tue, 2 Jan 2024 13:34:15 +0000 (14:34 +0100)]
arm64: dts: qcom: sm8550: Hook up GPU cooling device
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, unify the naming scheme of the
thermal zones across the tree while at it.
Konrad Dybcio [Tue, 2 Jan 2024 13:34:14 +0000 (14:34 +0100)]
arm64: dts: qcom: sm8450: Hook up GPU cooling device
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.
Konrad Dybcio [Tue, 2 Jan 2024 13:34:13 +0000 (14:34 +0100)]
arm64: dts: qcom: sm8350: Hook up GPU cooling device
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.
Konrad Dybcio [Tue, 2 Jan 2024 13:34:12 +0000 (14:34 +0100)]
arm64: dts: qcom: sm8250: Hook up GPU cooling device
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.
Konrad Dybcio [Tue, 2 Jan 2024 13:34:11 +0000 (14:34 +0100)]
arm64: dts: qcom: sm8150: Hook up GPU cooling device
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.
Konrad Dybcio [Tue, 2 Jan 2024 18:29:50 +0000 (19:29 +0100)]
arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes
The RPMh driver will cache sleep and wake votes until the cluster
power-domain is about to enter idle, to avoid unnecessary writes. So
associate the apps_rsc with the cluster pd, so that it can be notified
about this event.
Without this, only AMC votes are being committed.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Konrad Dybcio [Tue, 2 Jan 2024 18:29:49 +0000 (19:29 +0100)]
arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain
Previous Qualcomm SoCs over the past couple years have used the Arm DSU
architecture, which basically unified the meaning of the "cluster" and
"system". This is however clearly not the case on X1E, as can be seen
by three separate cluster power domains.
Add the lacking system-level power domain. For now it's going to be
always-on, as no system-wide idle states are defined at the moment.
Krishna Kurapati [Thu, 25 Jan 2024 18:59:20 +0000 (00:29 +0530)]
arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm
interrupts are used for wakeup instead of qusb2_phy irq. These targets
were part of a generation that were the last ones to implement QUSB2 PHY
and the design incorporated dedicated DP/DM interrupts which eventually
carried forward to the newer femto based targets.
Add the missing pwr_event irq for these targets. Also modify order of
interrupts in accordance to bindings update. Modifying the order of these
interrupts is harmless as the driver tries to get these interrupts from DT
by name and not by index.
Krishna Kurapati [Thu, 25 Jan 2024 18:59:19 +0000 (00:29 +0530)]
arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2
phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or
pwr_event. In one case, the hs_phy_irq was incorrectly defined with the
latter's IRQ number. Since the DT must describe the hw whether or not
the driver uses these interrupts, fix and add the missing entries in order
to describe the HW completely and accurately.
Also modify order of interrupts in accordance to bindings update.
Krishna Kurapati [Thu, 25 Jan 2024 18:59:18 +0000 (00:29 +0530)]
arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.
In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.
Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.
Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.
Luca Weiss [Fri, 1 Dec 2023 09:33:19 +0000 (10:33 +0100)]
arm64: dts: qcom: sc7280: Move video-firmware to chrome-common
If the video-firmware node is present, the venus driver assumes we're on
a system that doesn't use TZ for starting venus, like on ChromeOS
devices.
Move the video-firmware node to chrome-common.dtsi so we can use venus
on a non-ChromeOS devices. We also need to move the secure SID 0x2184
for iommu since (on some boards) we cannot touch that.
At the same time also disable the venus node by default in the dtsi,
like it's done on other SoCs.
Linus Torvalds [Sun, 21 Jan 2024 22:01:12 +0000 (14:01 -0800)]
Merge tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs
Pull more bcachefs updates from Kent Overstreet:
"Some fixes, Some refactoring, some minor features:
- Assorted prep work for disk space accounting rewrite
- BTREE_TRIGGER_ATOMIC: after combining our trigger callbacks, this
makes our trigger context more explicit
- A few fixes to avoid excessive transaction restarts on
multithreaded workloads: fstests (in addition to ktest tests) are
now checking slowpath counters, and that's shaking out a few bugs
- Assorted tracepoint improvements
- Starting to break up bcachefs_format.h and move on disk types so
they're with the code they belong to; this will make room to start
documenting the on disk format better.
- A few minor fixes"
* tag 'bcachefs-2024-01-21' of https://evilpiepirate.org/git/bcachefs: (46 commits)
bcachefs: Improve inode_to_text()
bcachefs: logged_ops_format.h
bcachefs: reflink_format.h
bcachefs; extents_format.h
bcachefs: ec_format.h
bcachefs: subvolume_format.h
bcachefs: snapshot_format.h
bcachefs: alloc_background_format.h
bcachefs: xattr_format.h
bcachefs: dirent_format.h
bcachefs: inode_format.h
bcachefs; quota_format.h
bcachefs: sb-counters_format.h
bcachefs: counters.c -> sb-counters.c
bcachefs: comment bch_subvolume
bcachefs: bch_snapshot::btime
bcachefs: add missing __GFP_NOWARN
bcachefs: opts->compression can now also be applied in the background
bcachefs: Prep work for variable size btree node buffers
bcachefs: grab s_umount only if snapshotting
...
Linus Torvalds [Sun, 21 Jan 2024 19:14:40 +0000 (11:14 -0800)]
Merge tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"Updates for time and clocksources:
- A fix for the idle and iowait time accounting vs CPU hotplug.
The time is reset on CPU hotplug which makes the accumulated
systemwide time jump backwards.
- Assorted fixes and improvements for clocksource/event drivers"
* tag 'timers-core-2024-01-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
tick-sched: Fix idle and iowait sleeptime accounting vs CPU hotplug
clocksource/drivers/ep93xx: Fix error handling during probe
clocksource/drivers/cadence-ttc: Fix some kernel-doc warnings
clocksource/drivers/timer-ti-dm: Fix make W=n kerneldoc warnings
clocksource/timer-riscv: Add riscv_clock_shutdown callback
dt-bindings: timer: Add StarFive JH8100 clint
dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs
projects / thirdparty / linux.git / log
