ian [Fri, 16 Aug 2019 22:49:23 +0000 (22:49 +0000)]
compiler: print runtime.hex in hex
The gc compiler recognizes the type runtime.hex and prints values
in this type as hex. Do the same here. This makes debugging
runtime crashes slightly better.
uros [Fri, 16 Aug 2019 14:28:12 +0000 (14:28 +0000)]
* config/i386/mmx.md (mmxdoublemode): New mode attribute.
(mmx_uavg<mode>3): Macroize expaner from mmx_uavgv8qi3 and
mmx_uavgv4hi3 using MMXMODE12 mode iterator.
(uavg<mode>3_ceil): New expander.
* config/i386/sse.md (uavg<mode>3_ceil): Use ssedoublemode
mode iterator when creating CONST1_RTX.
(<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
(*<sse2_avx2>_uavg<mode>3<mask_name>): Use ssedoublemode
mode iterator for const1_operand predicate.
ktkachov [Fri, 16 Aug 2019 09:32:36 +0000 (09:32 +0000)]
[gensupport] PR 91255: Do not error out immediately on set_attr_alternative with define_subst
I'm trying to add a define_subst use in the arm backend but am getting many build errors complaining about:
`set_attr_alternative' is unsupported by `define_subst'
Looking at the gensupport.c code it iterates over all define_insns and errors if any of them have set_attr_alternative.
The usecase I'm targetting doesn't involve patterns with set_attr_alternative, so I would like to make the define_subst handling
more robust to only error out if the define_subst is actually attempted on a set_attr_alternative.
This patch produces the error only if the set_attr_alternative attr matches the subst name.
This allows a build of the arm backend with a define_subst usage to succeed.
PR other/91255
* gensupport.c (has_subst_attribute): Error out on set_attr_alternative
only if subst_name matches curr_attr string.
rguenth [Fri, 16 Aug 2019 09:27:34 +0000 (09:27 +0000)]
2019-08-16 Richard Biener <rguenther@suse.de>
* tree-ssa-forwprop.c (simplify_builtin_call): Do not remove
stmt at gsi_p, instead replace it with a NOP removed later.
(pass_forwprop::execute): Fully propagate lattice, DCE stmts
that became dead because of that.
aoliva [Fri, 16 Aug 2019 03:38:49 +0000 (03:38 +0000)]
i386/asm-4 test: use amd64's natural addressing mode on all OSs
gcc.target/i386/asm-4.c uses amd64's natural PC-relative addressing
mode on a single platform, using the 32-bit absolute addressing mode
elsewhere. There's no point in giving up amd64's natural addressing
mode and insisting on the 32-bit one when we're targeting amd64, and
having to make explicit exceptions for systems where that's found not
to work for whatever reason. If we just use the best-suited way to
take the address of a function behind the compiler's back on each
target variant, we're less likely to hit unexpected failures.
for gcc/testsuite/ChangeLog
* gcc.target/i386/asm-4.c: Use amd64 natural addressing mode
on all __LP64__ targets.
aoliva [Fri, 16 Aug 2019 03:38:36 +0000 (03:38 +0000)]
use __builtin_alloca, drop non-standard alloca.h
Since alloca.h is not ISO C, most of our alloca-using tests seem to
rely on __builtin_alloca instead of including the header and calling
alloca. This patch extends this practice to some of the exceptions I
found in gcc.target, marking them as requiring a functional alloca
while at that.
for gcc/testsuite/ChangeLog
* gcc.target/arc/interrupt-6.c: Use __builtin_alloca, require
effective target support for alloca, drop include of alloca.h.
* gcc.target/i386/pr80969-3.c: Likewise.
* gcc.target/sparc/setjmp-1.c: Likewise.
* gcc.target/x86_64/abi/ms-sysv/gen.cc: Likewise.
* gcc.target/x86_64/abi/ms-sysv/ms-sysv.c: Likewise.
aoliva [Fri, 16 Aug 2019 03:38:23 +0000 (03:38 +0000)]
Match ld besides collect2 in gcov test
The regexp that checks that -lgcov is linked in when --coverage is
passed to the compiler driver requires the command line to match
'/collect2'. Some of our targets don't match that, but they match /ld
or ${target_alias}-ld depending on the testing scenario, so I'd like
to tweak the test to match those as well.
for gcc/testsuite/ChangeLog
* gcc.misc-tests/options.exp: Match /ld and -ld besides
/collect2.
aoliva [Fri, 16 Aug 2019 03:38:09 +0000 (03:38 +0000)]
address change
Oops, I forgot to update the MAINTAINERS file a couple of months ago,
when the address there stopped working.
Honestly, I haven't really had much involvement with the frv, mn10300
or sh ports for almost 15 years, so I wouldn't mind if someone else
stepped up and took over, but until someone does, I don't mind
reviewing the occasional patch, so it's best if it can reach me ;-)
for ChangeLog
* MAINTAINERS: aoliva from @redhat.com to @gcc.gnu.org.
tkoenig [Thu, 15 Aug 2019 22:52:40 +0000 (22:52 +0000)]
2019-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91443
* frontend-passes.c (check_externals_expr): New function.
(check_externals_code): New function.
(gfc_check_externals): New function.
* gfortran.h (debug): Add prototypes for gfc_symbol * and
gfc_expr *.
(gfc_check_externals): Add prototype.
* interface.c (compare_actual_formal): Do not complain about
alternate returns if the formal argument is optional.
(gfc_procedure_use): Handle cases when an error has been issued
previously. Break long line.
* parse.c (gfc_parse_file): Call gfc_check_externals for all
external procedures.
* resolve.c (resolve_global_procedure): Remove checking of
argument list.
2019-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91443
* gfortran.dg/argument_checking_19.f90: New test.
* gfortran.dg/altreturn_10.f90: Change dg-warning to dg-error.
* gfortran.dg/dec_union_11.f90: Add -std=legacy.
* gfortran.dg/hollerith8.f90: Likewise. Remove warning for
Hollerith constant.
* gfortran.dg/integer_exponentiation_2.f90: New subroutine gee_i8;
use it to avoid type mismatches.
* gfortran.dg/pr41011.f: Add -std=legacy.
* gfortran.dg/whole_file_1.f90: Change warnings to errors.
* gfortran.dg/whole_file_2.f90: Likewise.
jason [Thu, 15 Aug 2019 21:55:19 +0000 (21:55 +0000)]
PR c++/90393 - ICE with thow in ?:
My previous patch for 64372 was incomplete: it only stopped making the
non-throw argument into an rvalue, lvalue_kind still considered the ?:
expression to be an rvalue, leaving us worse than before.
PR c++/64372, DR 1560 - Gratuitous lvalue-to-rvalue conversion in ?:
* tree.c (lvalue_kind): Handle throw in one arm.
* typeck.c (rationalize_conditional_expr): Likewise.
(cp_build_modify_expr): Likewise.
hjl [Thu, 15 Aug 2019 18:15:33 +0000 (18:15 +0000)]
i386: Separate costs of pseudo registers from hard registers
processor_costs has costs of RTL expressions with pseudo registers and
and costs of hard register moves:
1. Costs of RTL expressions are used to generate the most efficient RTL
operations with pseudo registers.
2. Costs of hard register moves are used by register allocator to
decide how to allocate and move hard registers.
Since relative costs of pseudo register load and store versus pseudo
register moves in RTL expressions can be different from relative costs
of hard registers, we should separate costs of RTL expressions with
pseudo registers from costs of hard registers so that register allocator
and RTL expressions can be improved independently.
This patch moves costs of hard register moves to the new hard_register
field and duplicates costs of moves which are also used for costs of RTL
expressions.
PR target/90878
* config/i386/i386.c (inline_memory_move_cost): Use hard_register
for costs of hard register moves.
(ix86_register_move_cost): Likewise.
* config/i386/i386.h (processor_costs): Move costs of hard
register moves to hard_register. Add int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store, sse_unaligned_load and sse_unaligned_store
for costs of RTL expressions.
* config/i386/x86-tune-costs.h: Move costs of hard register
moves to hard_register. Duplicate int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store for costs of RTL expressions.
redi [Thu, 15 Aug 2019 16:07:27 +0000 (16:07 +0000)]
PR libstdc++/91456 make INVOKE<R> work with uncopyable prvalues
In C++17 a function can return a prvalue of a type that cannot be moved
or copied. The current implementation of std::is_invocable_r uses
std::is_convertible to test the conversion to R required by INVOKE<R>.
That fails for non-copyable prvalues, because std::is_convertible is
defined in terms of std::declval which uses std::add_rvalue_reference.
In C++17 conversion from R to R involves no copies and so is not the
same as conversion from R&& to R.
This commit changes std::is_invocable_r to check the conversion without
using std::is_convertible.
std::function also contains a similar check using std::is_convertible,
which can be fixed by simply reusing std::is_invocable_r (but because
std::is_invocable_r is not defined for C++11 it uses the underlying
std::__is_invocable_impl trait directly).
PR libstdc++/91456
* include/bits/std_function.h (__check_func_return_type): Remove.
(function::_Callable): Use std::__is_invocable_impl instead of
__check_func_return_type.
* include/std/type_traits (__is_invocable_impl): Add another defaulted
template parameter. Define a separate partial specialization for
INVOKE and INVOKE<void>. For INVOKE<R> replace is_convertible check
with a check that models delayed temporary materialization.
* testsuite/20_util/function/91456.cc: New test.
* testsuite/20_util/is_invocable/91456.cc: New test.
jozefl [Thu, 15 Aug 2019 12:55:33 +0000 (12:55 +0000)]
2019-08-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
MSP430: Fix whitespace errors and incorrect indentation in
config/msp430/*.{c,h} files
* config/msp430/driver-msp430.c (msp430_select_cpu): Fix indentation.
(msp430_select_hwmult_lib): Likewise.
* config/msp430/msp430-devices.c (parse_devices_csv_1): Likewise.
(msp430_extract_mcu_data): Likewise.
(struct t_msp430_mcu_data): Likewise.
* config/msp430/msp430.c (struct machine_function): Remove whitespace
before left square bracket.
(msp430_option_override): Fix indentation.
(msp430_hard_regno_nregs_with_padding): Likewise.
(msp430_initial_elimination_offset): Likewise.
(msp430_special_register_convention_p): Remove whitespace before left
square bracket and after exclamation mark.
(msp430_evaluate_arg): Likewise.
(msp430_callee_copies): Fix indentation.
(msp430_gimplify_va_arg_expr): Likewise.
(msp430_function_arg_advance): Remove whitespace before left square
bracket.
(reg_ok_for_addr): Likewise.
(msp430_preserve_reg_p): Likewise.
(msp430_compute_frame_info): Likewise.
(msp430_asm_output_addr_const_extra): Add space between function name
and open parenthesis.
(has_section_name): Fix indentation.
(msp430_attr): Remove trailing whitespace.
(msp430_section_attr): Likewise.
(msp430_data_attr): Likewise.
(struct msp430_attribute_table): Fix comment and whitespace.
(msp430_start_function): Remove whitespace before left square bracket.
Add space between function name and open parenthesis.
(msp430_select_section): Remove trailing whitespace.
(msp430_section_type_flags): Remove trailing whitespace.
(msp430_unique_section): Remove space before closing parenthesis.
(msp430_output_aligned_decl_common): Change 8 spaces to a tab.
(msp430_builtins): Remove whitespace before left square bracket.
(msp430_init_builtins): Fix indentation.
(msp430_expand_prologue): Remove whitespace before left square bracket.
Remove space before closing parenthesis.
(msp430_expand_epilogue): Remove whitespace before left square bracket.
(msp430_split_movsi): Remove space before closing parenthesis.
(helper_function_name_mappings): Fix indentation.
(msp430_use_f5_series_hwmult): Fix whitespace.
(use_32bit_hwmult): Likewise.
(msp430_no_hwmult): Likewise.
(msp430_output_labelref): Remove whitespace before left square bracket.
(msp430_print_operand_raw): Likewise.
(msp430_print_operand_addr): Likewise.
(msp430_print_operand): Add two spaces after '.' in comment.
Fix trailing whitespace.
(msp430x_extendhisi): Fix indentation.
* config/msp430/msp430.h (TARGET_CPU_CPP_BUILTINS): Change 8 spaces to
tab.
(PC_REGNUM): Likewise.
(STACK_POINTER_REGNUM): Likewise.
(CC_REGNUM): Likewise.
jason [Thu, 15 Aug 2019 12:38:50 +0000 (12:38 +0000)]
Implement P0848R3, Conditionally Trivial Special Member Functions.
With Concepts, overloads of special member functions can differ in
constraints, and this paper clarifies how that affects class properties: if
a class has a more constrained trivial copy constructor and a less
constrained non-trivial copy constructor, it is still trivially copyable.
* tree.c (special_memfn_p): New.
* class.c (add_method): When overloading, hide ineligible special
member fns.
(check_methods): Set TYPE_HAS_COMPLEX_* here.
* decl.c (grok_special_member_properties): Not here.
* name-lookup.c (push_class_level_binding_1): Move overloaded
functions case down, accept FUNCTION_DECL as target_decl.
rsandifo [Thu, 15 Aug 2019 09:23:06 +0000 (09:23 +0000)]
Add missing check for BUILT_IN_MD (PR 91444)
In this PR we were passing an ordinary non-built-in function to
targetm.vectorize.builtin_md_vectorized_function, which is only
supposed to handle BUILT_IN_MD.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR middle-end/91444
* tree-vect-stmts.c (vectorizable_call): Check that the function
is a BUILT_IN_MD function before passing it to
targetm.vectorize.builtin_md_vectorized_function.
rsandifo [Thu, 15 Aug 2019 09:00:22 +0000 (09:00 +0000)]
[AArch64] Add a aarch64_sve_mode_p query
This patch adds an exported function for testing whether a mode is
an SVE mode. The ACLE will make more use of it, but there's already
one place that can benefit.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_sve_mode_p): Declare.
* config/aarch64/aarch64.c (aarch64_sve_mode_p): New function.
(aarch64_select_early_remat_modes): Use it.
rsandifo [Thu, 15 Aug 2019 08:57:29 +0000 (08:57 +0000)]
[AArch64] Fix predicate alignment for fixed-length SVE
aarch64_simd_vector_alignment was only giving predicates 16-bit
alignment in VLA mode, not VLS mode. I think the problem is latent
because we can't yet create an ABI predicate type, but it seemed worth
fixing in a standalone patch rather than as part of the main ACLE series.
The ACLE patches have tests for this.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_simd_vector_alignment): Return
16 for SVE predicates even if they are fixed-length.
rsandifo [Thu, 15 Aug 2019 08:52:28 +0000 (08:52 +0000)]
[AArch64] Pass a pattern to aarch64_output_sve_cnt_immediate
This patch makes us always pass an explicit vector pattern to
aarch64_output_sve_cnt_immediate, rather than assuming it's ALL.
The ACLE patches need to be able to pass in other values.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take
the vector pattern as an aarch64_svpattern argument. Update the
overloaded caller accordingly.
(aarch64_output_sve_scalar_inc_dec): Update call accordingly.
(aarch64_output_sve_vector_inc_dec): Likewise.
rsandifo [Thu, 15 Aug 2019 08:50:00 +0000 (08:50 +0000)]
[AArch64] Optimise aarch64_add_offset for SVE VL constants
aarch64_add_offset contains code to decompose all SVE VL-based constants
into native operations. The worst-case fallback is to load the number
of SVE elements into a register and use a general multiplication.
This patch improves that fallback by reusing expand_mult if
can_create_pseudo_p, rather than emitting a MULT pattern directly.
In order to increase the chances of being able to use a simple
add-and-shift, the patch also tries to compute VG * the lowest set
bit of the multiplier, rather than always using CNTD as the basis
for the multiplication path.
This is tested by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_add_offset): In the fallback
multiplication case, try to compute VG * (lowest set bit) directly
rather than always basing the multiplication on VG. Use
expand_mult for the multiplication if we can.
gcc/testsuite/
* gcc.target/aarch64/sve/loop_add_4.c: Expect 10 INCWs and
INCDs rather than 8.
rsandifo [Thu, 15 Aug 2019 08:47:25 +0000 (08:47 +0000)]
[AArch64] Rework SVE INC/DEC handling
The scalar addition patterns allowed all the VL constants that
ADDVL and ADDPL allow, but wrote the instructions as INC or DEC
if possible (i.e. adding or subtracting a number of elements * [1, 16]
when the source and target registers the same). That works for the
cases that the autovectoriser needs, but there are a few constants
that INC and DEC can handle but ADDPL and ADDVL can't. E.g.:
inch x0, all, mul #9
is not a multiple of the number of bytes in an SVE register, and so
can't use ADDVL. It represents 36 times the number of bytes in an
SVE predicate, putting it outside the range of ADDPL.
This patch therefore adds separate alternatives for INC and DEC,
tied to a new Uai constraint. It also adds an explicit "scalar"
or "vector" to the function names, to avoid a clash with the
existing support for vector INC and DEC.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
(aarch64_output_sve_scalar_inc_dec): Declare.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.
* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
(aarch64_output_sve_scalar_inc_dec): New functions.
(aarch64_output_sve_addvl_addpl): Remove the base and offset
arguments. Only handle true ADDVL and ADDPL instructions;
don't emit an INC or DEC.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
(aarch64_sve_plus_immediate): New predicates.
(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
rather than aarch64_sve_addvl_addpl_immediate.
(aarch64_sve_inc_dec_immediate): Rename to...
(aarch64_sve_vector_inc_dec_immediate): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
(aarch64_sve_add_operand): Update accordingly.
* config/aarch64/constraints.md (Uai): New constraint.
(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
operand into a register if it satisfies aarch64_sve_plus_immediate.
(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
for Uai. Update calls to aarch64_output_sve_addvl_addpl.
* config/aarch64/aarch64-sve.md (add<mode>3): Call
aarch64_output_sve_vector_inc_dec instead of
aarch64_output_sve_inc_dec_immediate.
rsandifo [Thu, 15 Aug 2019 08:43:36 +0000 (08:43 +0000)]
[AArch64] Rework SVE REV[BHW] patterns
The current SVE REV patterns follow the AArch64 scheme, in which
UNSPEC_REV<NN> reverses elements within an <NN>-bit granule.
E.g. UNSPEC_REV64 on VNx8HI reverses the four 16-bit elements
within each 64-bit granule.
The native SVE scheme is the other way around: UNSPEC_REV64 is seen
as an operation on 64-bit elements, with REVB swapping bytes within
the elements, REVH swapping halfwords, and so on. This fits SVE more
naturally because the operation can then be predicated per <NN>-bit
granule/element.
Making the patterns use the Advanced SIMD scheme was more natural
when all we cared about were permutes, since we could then use
the source and target of the permute in their original modes.
However, the ACLE does need patterns that follow the native scheme,
treating them as operations on integer elements. This patch defines
the patterns that way instead and updates the existing uses to match.
This also brings in a couple of helper routines from the ACLE branch.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (UNSPEC_REVB, UNSPEC_REVH)
(UNSPEC_REVW): New constants.
(elem_bits): New mode attribute.
(SVE_INT_UNARY): New int iterator.
(optab): Handle UNSPEC_REV[BHW].
(sve_int_op): New int attribute.
(min_elem_bits): Handle VNx16QI and the predicate modes.
* config/aarch64/aarch64-sve.md (*aarch64_sve_rev64<mode>)
(*aarch64_sve_rev32<mode>, *aarch64_sve_rev16vnx16qi): Delete.
(@aarch64_pred_<SVE_INT_UNARY:optab><SVE_I:mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_sve_data_mode): New function.
(aarch64_sve_int_mode, aarch64_sve_rev_unspec): Likewise.
(aarch64_split_sve_subreg_move): Use UNSPEC_REV[BHW] instead of
unspecs based on the total width of the reversed data.
(aarch64_evpc_rev_local): Likewise (for SVE only). Use a
reinterpret followed by a subreg on big-endian targets.
gcc/testsuite/
* gcc.target/aarch64/sve/revb_1.c: Restrict to little-endian targets.
Avoid including stdint.h.
* gcc.target/aarch64/sve/revh_1.c: Likewise.
* gcc.target/aarch64/sve/revw_1.c: Likewise.
* gcc.target/aarch64/sve/revb_2.c: New big-endian test.
* gcc.target/aarch64/sve/revh_2.c: Likewise.
* gcc.target/aarch64/sve/revw_2.c: Likewise.
rsandifo [Thu, 15 Aug 2019 08:39:42 +0000 (08:39 +0000)]
[AArch64] Add more SVE FMLA and FMAD /z alternatives
This patch makes the floating-point conditional FMA patterns provide the
same /z alternatives as the integer patterns added by a previous patch.
We can handle cases in which individual inputs are allocated to the same
register as the output, so we don't need to force all registers to be
different.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
alternatives in which one of the inputs is in the same register
as the output.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
and FMSB as well as FMLS.
rsandifo [Thu, 15 Aug 2019 08:37:14 +0000 (08:37 +0000)]
[AArch64] Add MOVPRFX alternatives for SVE EXT patterns
We use EXT both to implement vec_extract for large indices and as a
permute. In both cases we can use MOVPRFX to handle the case in which
the first input and output can't be tied.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
rsandifo [Thu, 15 Aug 2019 08:34:40 +0000 (08:34 +0000)]
[AArch64] Remove unneeded FSUB alternatives and add a new one
The floating-point subtraction patterns don't need to handle
subtraction of constants, since those go through the addition
patterns instead. There was a missing MOVPRFX alternative for
FSUBR though.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR.
rsandifo [Thu, 15 Aug 2019 08:29:11 +0000 (08:29 +0000)]
[AArch64] Use SVE reversed shifts in preference to MOVPRFX
This patch makes us use reversed SVE shifts when the first operand
can't be tied to the output but the second can. This is tested
more thoroughly by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3):
Add an alternative that uses reversed shifts.
ktkachov [Thu, 15 Aug 2019 08:26:50 +0000 (08:26 +0000)]
[aarch64] Use neoversen1 tuning struct for -mcpu=cortex-a76
The neoversen1 tuning struct gives better performance on the Cortex-A76, so use that.
The only difference from the current tuning is the function and label alignment settings.
This gives about 1.3% improvement on SPEC2006 int and 0.3% on SPEC2006 fp.
* config/aarch64/aarch64-cores.def (cortex-a76): Use neoversen1 tuning
struct.
rsandifo [Thu, 15 Aug 2019 08:22:07 +0000 (08:22 +0000)]
[AArch64] Use SVE MLA, MLS, MAD and MSB for conditional arithmetic
This patch uses predicated MLA, MLS, MAD and MSB to implement
conditional "FMA"s on integers. This also requires providing
the unpredicated optabs (fma and fnma) since otherwise
tree-ssa-math-opts.c won't try to use the conditional forms.
We still want to use shifts and adds in preference to multiplications,
so the patch makes the optab expanders check for that.
The tests cover floating-point types too, which are already handled,
and which were already tested to some extent by gcc.dg/vect.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
rsandifo [Thu, 15 Aug 2019 08:18:03 +0000 (08:18 +0000)]
[AArch64] Use SVE binary immediate instructions for conditional arithmetic
This patch lets us use the immediate forms of FADD, FSUB, FSUBR,
FMUL, FMAXNM and FMINNM for conditional arithmetic. (We already
use them for normal unconditional arithmetic.)
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64.c (aarch64_print_vector_float_operand):
Print 2.0 naturally.
(aarch64_sve_float_mul_immediate_p): Return true for 2.0.
* config/aarch64/predicates.md
(aarch64_sve_float_negated_arith_immediate): New predicate,
renamed from aarch64_sve_float_arith_with_sub_immediate.
(aarch64_sve_float_arith_with_sub_immediate): Test for both
positive and negative constants.
(aarch64_sve_float_arith_with_sub_operand): Redefine as a register
or an aarch64_sve_float_arith_with_sub_immediate.
* config/aarch64/constraints.md (vsN): Use
aarch64_sve_float_negated_arith_immediate.
* config/aarch64/iterators.md (SVE_COND_FP_BINARY_I1): New int
iterator.
(sve_pred_fp_rhs2_immediate): New int attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>): Use
sve_pred_fp_rhs1_operand and sve_pred_fp_rhs2_operand.
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_2_const)
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_any_const)
(*cond_add<SVE_F:mode>_2_const, *cond_add<SVE_F:mode>_any_const)
(*cond_sub<mode>_3_const, *cond_sub<mode>_any_const): New patterns.
rsandifo [Thu, 15 Aug 2019 08:12:41 +0000 (08:12 +0000)]
[AArch64] Use SVE FABD in conditional arithmetic
This patch extends the FABD support so that it handles conditional
arithmetic. We're relying on combine for this, since there's no
associated IFN_COND_* (yet?).
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_abd<SVE_F:mode>_2)
(*aarch64_cond_abd<SVE_F:mode>_3)
(*aarch64_cond_abd<SVE_F:mode>_any): New patterns.
rsandifo [Thu, 15 Aug 2019 08:08:49 +0000 (08:08 +0000)]
[AArch64] Use SVE [SU]ABD in conditional arithmetic
This patch extends the [SU]ABD support so that it handles
conditional arithmetic. We're relying on combine for this,
since there's no associated IFN_COND_* (yet?).
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_<su>abd<mode>_2)
(*aarch64_cond_<su>abd<mode>_any): New patterns.
rsandifo [Thu, 15 Aug 2019 08:05:50 +0000 (08:05 +0000)]
Add support for conditional shifts
This patch adds support for IFN_COND shifts left and shifts right.
This is mostly mechanical, but since we try to handle conditional
operations in the same way as unconditional operations in match.pd,
we need to support IFN_COND shifts by scalars as well as vectors.
E.g.:
IFN_COND_SHL (cond, a, { 1, 1, ... }, fallback)
and:
IFN_COND_SHL (cond, a, 1, fallback)
are the same operation, with:
(for shiftrotate (lrotate rrotate lshift rshift)
...
/* Prefer vector1 << scalar to vector1 << vector2
if vector2 is uniform. */
(for vec (VECTOR_CST CONSTRUCTOR)
(simplify
(shiftrotate @0 vec@1)
(with { tree tem = uniform_vector_p (@1); }
(if (tem)
(shiftrotate @0 { tem; }))))))
preferring the latter. The patch copes with this by extending
create_convert_operand_from to handle scalar-to-vector conversions.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
marxin [Thu, 15 Aug 2019 06:58:09 +0000 (06:58 +0000)]
Properly register dead cgraph_nodes in passes.c.
2019-08-15 Martin Liska <mliska@suse.cz>
PR ipa/91404
* passes.c (order): Remove.
(uid_hash_t): Likewise).
(remove_cgraph_node_from_order): Remove from set
of pointers (cgraph_node *).
(insert_cgraph_node_to_order): New.
(duplicate_cgraph_node_to_order): New.
(do_per_function_toporder): Register all 3 cgraph hooks.
Skip removed_nodes now as we know about all of them.
redi [Wed, 14 Aug 2019 19:52:58 +0000 (19:52 +0000)]
PR c++/91436 fix C++ dialect for std::make_unique fix-it hint
The std::make_unique function wasn't added until C++14, and neither was
the std::complex_literals namespace.
gcc/cp:
PR c++/91436
* name-lookup.c (get_std_name_hint): Fix min_dialect field for
complex_literals and make_unique entries.
gcc/testsuite:
PR c++/91436
* g++.dg/lookup/missing-std-include-5.C: Limit test to C++14 and up.
* g++.dg/lookup/missing-std-include-6.C: Don't check make_unique in
test that runs for C++11.
* g++.dg/lookup/missing-std-include-8.C: Check make_unique here.
uros [Wed, 14 Aug 2019 18:43:16 +0000 (18:43 +0000)]
* config/i386/i386-expand.c (ix86_expand_vector_init_one_nonzero)
<case E_V8QImode>: Use vector_set path for
TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
(ix86_expand_vector_init_one_nonzero) <case E_V8QImode>:
Do not widen for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
mpolacek [Wed, 14 Aug 2019 14:44:55 +0000 (14:44 +0000)]
PR c++/91391 - bogus -Wcomma-subscript warning.
* parser.c (cp_parser_postfix_open_square_expression): Don't warn about
a deprecated comma here. Pass warn_comma_subscript down to
cp_parser_expression.
(cp_parser_expression): New bool parameter. Warn about uses of a comma
operator within a subscripting expression.
(cp_parser_skip_to_closing_square_bracket): Revert to pre-r274121 state.
(cp_parser_skip_to_closing_square_bracket_1): Remove.
clyon [Wed, 14 Aug 2019 13:14:59 +0000 (13:14 +0000)]
Add generic support for noinit attribute.
Similar to what already exists for TI msp430 or in TI compilers for
arm, this patch adds support for the "noinit" attribute.
It is convenient for embedded targets where the user wants to keep the
value of some data when the program is restarted: such variables are
not zero-initialized. It is mostly a helper/shortcut to placing
variables in a dedicated section.
It's probably desirable to add the following chunk to the GNU linker:
diff --git a/ld/emulparams/armelf.sh b/ld/emulparams/armelf.sh
index 272a8bc..9555cec 100644
--- a/ld/emulparams/armelf.sh
+++ b/ld/emulparams/armelf.sh
@@ -10,7 +10,19 @@ OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7)
*(.vfp11_veneer) *(.v4_bx)'
OTHER_BSS_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__bss_start__ =
.${CREATE_SHLIB+)};"
OTHER_BSS_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}_bss_end__ =
.${CREATE_SHLIB+)}; ${CREATE_SHLIB+PROVIDE (}__bss_end__ =
.${CREATE_SHLIB+)};"
OTHER_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__end__ = .${CREATE_SHLIB+)};"
-OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
+OTHER_SECTIONS='
+.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /* This section contains data that is not initialised during load
+ *or* application reset. */
+ .noinit (NOLOAD) :
+ {
+ . = ALIGN(2);
+ PROVIDE (__noinit_start = .);
+ *(.noinit)
+ . = ALIGN(2);
+ PROVIDE (__noinit_end = .);
+ }
+'
so that the noinit section has the "NOLOAD" flag.
I added a testcase if gcc.c-torture/execute, gated by the new noinit
effective-target.
Finally, I tested on arm-eabi, but not on msp430 for which I do not
have the environment.
rguenth [Wed, 14 Aug 2019 12:04:05 +0000 (12:04 +0000)]
2019-08-14 Richard Biener <rguenther@suse.de>
Uroš Bizjak <ubizjak@gmail.com>
PR target/91154
* config/i386/i386-features.h (scalar_chain::scalar_chain): Add
mode arguments.
(scalar_chain::smode): New member.
(scalar_chain::vmode): Likewise.
(dimode_scalar_chain): Rename to...
(general_scalar_chain): ... this.
(general_scalar_chain::general_scalar_chain): Take mode arguments.
(timode_scalar_chain::timode_scalar_chain): Initialize scalar_chain
base with TImode and V1TImode.
* config/i386/i386-features.c (scalar_chain::scalar_chain): Adjust.
(general_scalar_chain::vector_const_cost): Adjust for SImode
chains.
(general_scalar_chain::compute_convert_gain): Likewise. Add
{S,U}{MIN,MAX} support.
(general_scalar_chain::replace_with_subreg): Use vmode/smode.
(general_scalar_chain::make_vector_copies): Likewise. Handle
non-DImode chains appropriately.
(general_scalar_chain::convert_reg): Likewise.
(general_scalar_chain::convert_op): Likewise.
(general_scalar_chain::convert_insn): Likewise. Add
fatal_insn_not_found if the result is not recognized.
(convertible_comparison_p): Pass in the scalar mode and use that.
(general_scalar_to_vector_candidate_p): Likewise. Rename from
dimode_scalar_to_vector_candidate_p. Add {S,U}{MIN,MAX} support.
(scalar_to_vector_candidate_p): Remove by inlining into single
caller.
(general_remove_non_convertible_regs): Rename from
dimode_remove_non_convertible_regs.
(remove_non_convertible_regs): Remove by inlining into single caller.
(convert_scalars_to_vector): Handle SImode and DImode chains
in addition to TImode chains.
* config/i386/i386.md (<maxmin><MAXMIN_IMODE>3): New expander.
(*<maxmin><MAXMIN_IMODE>3_1): New insn-and-split.
(*<maxmin>di3_doubleword): Likewise.
rsandifo [Wed, 14 Aug 2019 11:00:45 +0000 (11:00 +0000)]
[AArch64] Use SVE UXT[BHW] as a form of predicated AND
UXTB, UXTH and UXTW are equivalent to predicated ANDs with the constants
0xff, 0xffff and 0xffffffff respectively. This patch uses them in the
patterns for IFN_COND_AND.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_print_operand): Allow %e to
take the equivalent mask, as well as a bit count.
* config/aarch64/predicates.md (aarch64_sve_uxtb_immediate)
(aarch64_sve_uxth_immediate, aarch64_sve_uxt_immediate)
(aarch64_sve_pred_and_operand): New predicates.
* config/aarch64/iterators.md (sve_pred_int_rhs2_operand): New
code attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_INT_BINARY:optab><SVE_I:mode>): Use it.
(*cond_uxt<mode>_2, *cond_uxt<mode>_any): New patterns.
rsandifo [Wed, 14 Aug 2019 10:56:57 +0000 (10:56 +0000)]
[AArch64] Add SVE conditional conversion patterns
This patch adds patterns to match conditional conversions between
integers and like-sized floats. The patterns are actually more
general than that, but the other combinations can only be tested
via the ACLE.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FCVTI:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
(*cond_<SVE_COND_ICVTF:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>):
New patterns.
rsandifo [Wed, 14 Aug 2019 10:53:10 +0000 (10:53 +0000)]
[AArch64] Add SVE conditional floating-point unary patterns
This patch adds patterns to match conditional unary operations
on floating-point modes. At the moment we rely on combine to merge
separate arithmetic and vcond_mask operations, and since the latter
doesn't accept zero operands, we miss out on the opportunity to use
the movprfx /z alternative. (This alternative is tested by the ACLE
patches though.)
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_2): New pattern.
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_any): Likewise.
rsandifo [Wed, 14 Aug 2019 10:48:50 +0000 (10:48 +0000)]
[AArch64] Add SVE conditional integer unary patterns
This patch adds patterns to match conditional unary operations
on integers. At the moment we rely on combine to merge separate
arithmetic and vcond_mask operations, and since the latter doesn't
accept zero operands, we miss out on the opportunity to use the
movprfx /z alternative. (This alternative is tested by the ACLE
patches though.)
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_2): New pattern.
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_any): Likewise.
pmderodat [Wed, 14 Aug 2019 09:52:58 +0000 (09:52 +0000)]
[Ada] Improve performance of Containers.Functional_Base
This patch modifies the implementation of Functional_Base to damp the
cost of its subprograms at runtime in specific cases. Instead of copying
the entire underlying array to create a new container, containers can
share the same Array_Base attribute. Performance on common use cases of
formal and functional containers is improved with this patch.
2019-08-14 Joffrey Huguet <huguet@adacore.com>
gcc/ada/
* libgnat/a-cofuba.ads: Add a Length attribute to type
Container. Add a type Array_Base which replaces the previous
Elements attribute of Container.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
* libgnat/a-cofuba.adb (Resize): New subprogram. It is used to
resize the underlying array of a container if necessary.
(=, <=, Find, Get, Intersection, Length, Num_Overlaps, Set,
Union): Update to match changes in type declarations.
(Add): Modify body to damp the time and space cost in a specific
case.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
(Remove): Modify body to damp the time and space cost in a
specific case.
pmderodat [Wed, 14 Aug 2019 09:52:54 +0000 (09:52 +0000)]
[Ada] Alignment may be specified as zero
An Alignment clause or an aspect_specification for Alignment may be
specified as 0, which is treated the same as 1.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_ch13.adb (Get_Alignment_Value): Return 1 for Alignment 0,
and do not give an error.
* doc/gnat_rm/representation_clauses_and_pragmas.rst: Update the
corresponding documentation.
* gnat_rm.texi: Regenerate.
pmderodat [Wed, 14 Aug 2019 09:52:39 +0000 (09:52 +0000)]
[Ada] Do not crash with -gnatR3 on Ghost aspects
2019-08-14 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* sem_aux.adb (Next_Rep_Item): If a node in the rep chain
involves a Ghost aspect it may have been replaced by a null
statement; use the original node to find next Rep_Item.
* repinfo.adb (List_Entities): Do not list an Ignored
Ghost_Entity, for which information may have been deleted.
pmderodat [Wed, 14 Aug 2019 09:52:34 +0000 (09:52 +0000)]
[Ada] Warn about unknown condition in Compile_Time_Warning
The compiler now warns if the condition in a pragma Compile_Time_Warning
or Compile_Time_Error does not have a compile-time-known value. The
warning is not given for pragmas in a generic template, but is given for
pragmas in an instance.
The -gnatw_c and -gnatw_C switches turn the warning on and off. The
default is on.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_prag.ads, sem_prag.adb
(Process_Compile_Time_Warning_Or_Error): In parameterless
version, improve detection of whether we are in a generic unit
to cover the case of an instance within a generic unit.
(Process_Compile_Time_Warning_Or_Error): Rename the
two-parameter version to be
Validate_Compile_Time_Warning_Or_Error, and do not export it.
Issue a warning if the condition is not known at compile time.
The key point is that the warning must be given only for pragmas
deferred to the back end, because the back end discovers
additional values that are known at compile time. Previous
changes in this ticket have enabled this by deferring to the
back end without checking for special cases such as 'Size.
(Validate_Compile_Time_Warning_Or_Error): Rename to be
Defer_Compile_Time_Warning_Error_To_BE.
* warnsw.ads, warnsw.adb (Warn_On_Unknown_Compile_Time_Warning):
Add new switches -gnatw_c and -gnatw_C to control the above
warning.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Document new switches.
* gnat_ugn.texi: Regenerate.
pmderodat [Wed, 14 Aug 2019 09:52:24 +0000 (09:52 +0000)]
[Ada] Incorrect error on inline protected function
This patch fixes a bug where if a protected function has a pragma
Inline, and has no local variables, and the body consists of a single
extended_return_statement, and the result type is an indefinite
composite subtype, and inlining is enabled, the compiler gives an error,
even though the program is legal.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* inline.adb (Check_And_Split_Unconstrained_Function): Ignore
protected functions to get rid of spurious error. The
transformation done by this procedure triggers legality errors
in the generated code in this case.
gcc/testsuite/
* gnat.dg/inline19.adb, gnat.dg/inline19.ads: New testcase.
pmderodat [Wed, 14 Aug 2019 09:52:20 +0000 (09:52 +0000)]
[Ada] Defer processing of unknown CTW/E conditions to the back end
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_prag.adb (Process_Compile_Time_Warning_Or_Error): Defer
processing to the back end in all cases where the pragma's
condition is not known at compile time during the front end
(except in generics), as opposed to detecting 'Size attributes
and the like. This ensures that we take advantage of whatever
can be compile-time known after running the back end, as opposed
to having the front end guess what the back end can do. Remove
a little duplicated code at the call site.
* gnat1drv.adb (Post_Compilation_Validation_Checks): Unlock the
Elists while in Validate_Compile_Time_Warning_Errors, because it
does analysis and name resolution, which sometimes involves
adding Elists.
pmderodat [Wed, 14 Aug 2019 09:52:15 +0000 (09:52 +0000)]
[Ada] Compiler speedup with inlining across units
This change is aimed at speeding up the inlining across units done by
the Ada compiler when -gnatn is specified and in the presence of units
instantiating a lot of generic packages.
The current implementation is as follows: when a generic package is
being instantiated, the compiler scans its spec for the presence of
subprograms with an aspect/pragma Inline and, upon finding one,
schedules the instantiation of its body. That's not very efficient
because the compiler doesn't know yet if one of those inlined
subprograms will eventually be called from the main unit.
The new implementation arranges for the compiler to instantiate the body
on demand, i.e. when it encounters a call to one of the inlined
subprograms. That's still not optimal because, at this point, the
compiler has not yet computed whether the call itself is reachable from
the main unit (it will do this computation at the very end of the
processing, just before sending the inlined units to the code generator)
but that's nevertheless a net progress.
The patch also enhances the -gnatd.j option to make it output the list
of instances "inlined" this way. The following package is a simple
example:
with Q;
procedure P is
begin
Q.Proc;
end;
package Q is
procedure Proc;
pragma Inline (Proc);
end Q;
with G;
package body Q is
package My_G is new G (1);
procedure Proc is
Val : constant Integer := My_G.Func;
begin
if Val /= 1 then
raise Program_Error;
end if;
end;
end Q;
generic
Value : Integer;
package G is
function Func return Integer;
pragma Inline (Func);
end G;
package body G is
function Func return Integer is
begin
return Value;
end;
end G;
2019-08-14 Eric Botcazou <ebotcazou@adacore.com>
gcc/ada/
* einfo.ads (Is_Called): Document new usage on E_Package
entities.
* einfo.adb (Is_Called): Accept E_Package entities.
(Set_Is_Called): Likewise.
* exp_ch6.adb (Expand_Call_Helper): Move code dealing with
instances for back-end inlining to Add_Inlined_Body.
* inline.ads: Remove with clauses for Alloc and Table.
(Pending_Instantiations): Move to...
* inline.adb: Add with clauses for Alloc, Uintp, Table and
GNAT.HTable.
(Backend_Instances): New variable.
(Pending_Instantiations): ...here.
(Called_Pending_Instantiations): New table.
(Node_Table_Size): New constant.
(Node_Header_Num): New subtype.
(Node_Hash): New function.
(To_Pending_Instantiations): New hash table.
(Add_Inlined_Body): Bail out early for subprograms in the main
unit or subunit. Likewise if the Is_Called flag is set. If the
subprogram is an instance, invoke Add_Inlined_Instance. Call
Set_Is_Called earlier. If the subrogram is within an instance,
invoke Add_Inlined_Instance. Also deal with the case where the
call itself is within an instance.
(Add_Inlined_Instance): New procedure.
(Add_Inlined_Subprogram): Remove conditions always fulfilled.
(Add_Pending_Instantiation): Move the defence against ludicruous
number of instantiations to here. When back-end inlining is
enabled, associate an instantiation with its index in table and
mark a few selected kinds of instantiations as always needed.
(Initialize): Set Backend_Instances to No_Elist.
(Instantiate_Body): New procedure doing the work extracted
from...
(Instantiate_Bodies): ...here. When back-end inlining is
enabled, loop over Called_Pending_Instantiations instead of
Pending_Instantiations.
(Is_Nested): Minor tweak.
(List_Inlining_Info): Also list the contents of
Backend_Instances.
* sem_ch12.adb (Might_Inline_Subp): Return early if Is_Inlined
is set and otherwise set it before returning true.
(Analyze_Package_Instantiation): Remove the defence against
ludicruous number of instantiations. Invoke
Remove_Dead_Instance instead of doing the removal manually if
there is a guaranteed ABE.
pmderodat [Wed, 14 Aug 2019 09:52:10 +0000 (09:52 +0000)]
[Ada] Equality for nonabstract type derived from interface treated as abstract
The compiler was creating an abstract function for the equality
operation of a (nonlimited) interface type, and that could result in
errors on generic instantiations that are passed nonabstract types
derived from the interface type along with the derived type's inherited
equality operation (complaining about an abstract subprogram being
passed to a nonabstract formal). The "=" operation of an interface is
supposed to be nonabstract (a direct consequence of the rule in RM
4.5.2(6-7)), so we now create an expression function rather than an
abstract function. The function returns False, but the result is
unimportant since a function of an abstract type can never actually be
invoked (its arguments must generally be class-wide, since there can be
no objects of the type, and calling it will dispatch).
2019-08-14 Gary Dismukes <dismukes@adacore.com>
gcc/ada/
* exp_ch3.adb (Predef_Spec_Or_Body): For an equality operation
of an interface type, create an expression function (that
returns False) rather than declaring an abstract function.
* freeze.adb (Check_Inherited_Conditions): Set Needs_Wrapper to
False unconditionally at the start of the loop creating wrappers
for inherited operations.
gcc/testsuite/
* gnat.dg/equal11.adb, gnat.dg/equal11_interface.ads,
gnat.dg/equal11_record.adb, gnat.dg/equal11_record.ads: New
testcase.
pmderodat [Wed, 14 Aug 2019 09:52:06 +0000 (09:52 +0000)]
[Ada] Strengthen Locked flag
This patch strengthens the Locked flag, by Asserting that it is False on
operations that might cause reallocation.
No change in behavior (except in the presence of compiler bugs), so no
test.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* table.adb: Assert that the table is not locked when increasing
Last, even if it doesn't cause reallocation. In other words,
assert that on operations that MIGHT cause reallocation.
* table.ads: Fix comment accordingly.
projects / thirdparty / gcc.git / log
