rs6000-c.c (altivec_overloaded_builtins): Add array entries to represent __ieee128 versions of the scalar_test_data_class...
gcc/ChangeLog:
2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
array entries to represent __ieee128 versions of the
scalar_test_data_class, scalar_test_neg, scalar_extract_exp,
scalar_extract_sig, and scalar_insert_exp built-in functions.
(altivec_resolve_overloaded_builtin): Add special case handling
for the __builtin_scalar_insert_exp function, as represented by
the P9V_BUILTIN_VEC_VSIEDP constant.
* config/rs6000/rs6000-builtin.def (VSEEQP): Add scalar extract
exponent support for __ieee128 argument.
(VSESQP): Add scalar extract signature support for __ieee128
argument.
(VSTDCNQP): Add scalar test negative support for __ieee128
argument.
(VSIEQP): Add scalar insert exponent support for __int128 argument
with __ieee128 result.
(VSIEQPF): Add scalar insert exponent support for __ieee128
argument with __ieee128 result.
(VSTDCQP): Add scalar test data class support for __ieee128
argument.
(VSTDCNQP): Add overload support for scalar test negative with
__ieee128 argument.
(VSTDCQP): Add overload support for scalar test data class
__ieee128 argument.
* config/rs6000/vsx.md (UNSPEC_VSX_SXSIG) Replace
UNSPEC_VSX_SXSIGDP.
(UNSPEC_VSX_SIEXPQP): New constant.
(xsxexpqp): New insn for VSX scalar extract exponent quad
precision.
(xsxsigqp): New insn for VSX scalar extract significand quad
precision.
(xsiexpqpf): New insn for VSX scalar insert exponent quad
precision with floating point argument.
(xststdcqp): New expand for VSX scalar test data class quad
precision.
(xststdcnegqp): New expand for VSX scalar test negative quad
precision.
(xststdcqp): New insn to match expansions for VSX scalar test data
class quad precision and VSX scalar test negative quad precision.
* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add
special case operand checking to enforce that second operand of
VSX scalar test data class with quad precision argument is a 7-bit
unsigned literal.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Add
prototypes and descriptions of __ieee128 versions of
scalar_extract_exp, scalar_extract_sig, scalar_insert_exp,
scalar_test_data_class, and scalar_test_neg built-in functions.
gcc/testsuite/ChangeLog:
2017-07-14 Kelvin Nilsen <kelvin@gcc.gnu.org>
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-14.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-15.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-10.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-11.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-12.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-13.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-14.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-15.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-4.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-6.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-7.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-8.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-9.c: New test.
Jason Merrill [Fri, 14 Jul 2017 19:13:49 +0000 (15:13 -0400)]
Constrain std::variant constructor for class template argument deduction
2017-07-14 Jason Merrill <jason@redhat.com>
Jonathan Wakely <jwakely@redhat.com>
* include/std/variant (variant::variant(_Tp&&)): Constrain to remove
the constructor for empty variants from the candidate functions
during class template argument deduction.
* testsuite/20_util/variant/deduction.cc: New.
Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>
From-SVN: r250213
[ARM] Fix definition of __ARM_FEATURE_NUMERIC_MAXMIN
Definition of __ARM_FEATURE_NUMERIC_MAXMIN checks for
TARGET_ARM_ARCH >= 8 and TARGET_NEON being true in addition to
TARGET_VFP5. However, instructions covered by this macro are part of
FPv5 which is available in ARMv7E-M architecture. This commit fixes the
macro to only check for TARGET_VFP5.
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-c.c (arm_cpu_builtins): Define
__ARM_FEATURE_NUMERIC_MAXMIN solely based on TARGET_VFP5.
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-cpus.in (cortex-r52): Add new entry.
(armv8-r): Set ARM Cortex-R52 as default CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
Cortex-R52.
* doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
extension for -mcpu=cortex-r52.
fp-armv8 is currently defined as a double precision FPv5 with 32 D
registers *and* a special FP_ARMv8 bit. However FP for ARMv8 should only
bring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is
spurious. As a consequence, many instruction patterns which are guarded
by TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.
This commit gets rid of TARGET_FPU_ARMV8 and rewire all uses to
expressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.
It also redefine ISA_FP_ARMv8 to include the D32 capability to
distinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to
enable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D
registers).
2017-07-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
(ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
* config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
(fp-armv8): Define it as FP_ARMv8 only.
config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
(TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
TARGET_FPU_ARMV8.
config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
* config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
than TARGET_FPU_ARMV8.
* config/arm/arm-c.c (arm_cpu_builtins): Likewise for
__ARM_FEATURE_NUMERIC_MAXMIN macro definition.
* config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
TARGET_FPU_ARMV8.
* config/arm/neon.md (neon_vrint): Likewise.
(neon_vcvt): Likewise.
(neon_<fmaxmin_op><mode>): Likewise.
(<fmaxmin><mode>3): Likewise.
* config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
* config/arm/predicates.md (arm_cond_move_operator): Check against
TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.
David Malcolm [Fri, 14 Jul 2017 15:09:00 +0000 (15:09 +0000)]
c/c++: Add fix-it hints for suggested missing #includes
gcc/c-family/ChangeLog:
* c-common.c (try_to_locate_new_include_insertion_point): New
function.
(per_file_includes_t): New typedef.
(added_includes_t): New typedef.
(added_includes): New variable.
(maybe_add_include_fixit): New function.
* c-common.h (maybe_add_include_fixit): New decl.
gcc/c/ChangeLog:
* c-decl.c (implicitly_declare): When suggesting a missing
#include, provide a fix-it hint.
gcc/cp/ChangeLog:
* name-lookup.c (get_std_name_hint): Add '<' and '>' around
the header names.
(maybe_suggest_missing_header): Update for addition of '<' and '>'
to above. Provide a fix-it hint.
* pt.c: Include "gcc-rich-location.h"
(listify): Attempt to add fix-it hint for missing
#include <initializer_list>.
* rtti.c: Include "gcc-rich-location.h".
(typeid_ok_p): Attempt to add fix-it hint for missing
#include <typeinfo>.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/missing-initializer_list-include.C: New test case.
* g++.dg/lookup/missing-std-include-2.C: New test case.
* g++.dg/lookup/missing-std-include-3.C: New test case.
* g++.dg/rtti/missing-typeinfo-include.C: New test case.
* gcc.dg/missing-header-fixit-1.c: New test case.
* gcc.dg/missing-header-fixit-2.c: New test case.
* gcc.dg/missing-header-fixit-2.h: New header.
Jakub Jelinek [Fri, 14 Jul 2017 09:10:45 +0000 (11:10 +0200)]
re PR sanitizer/81066 (sanitizer_stoptheworld_linux_libcdep.cc:276:22: error: aggregate ‘sigaltstack handler_stack’ has incomplete type and cannot be defined)
Martin Liska [Fri, 14 Jul 2017 07:44:33 +0000 (09:44 +0200)]
Remove Java references in source code.
2017-07-14 Martin Liska <mliska@suse.cz>
* cfgexpand.c (expand_gimple_basic_block): Remove dead comment.
* dwarf2out.c (is_java): Remove the function.
(output_pubname): Remove usage of the function.
(lower_bound_default): Remove usage of DW_LANG_Java.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove compiler defaults for .java and .zip files.
* gimple-expr.c (remove_suffix): Change as there's no longer
extension than 4-letter one.
* gimplify.c (mostly_copy_tree_r): Remove Java-special part.
(gimplify_save_expr): Likewise.
* ipa-utils.h (polymorphic_type_binfo_p): Remove the comment
as it's possible even for other languages than Java.
* langhooks.h (struct lang_hooks): Remove Java from a comment.
* lto-opts.c (lto_write_options): Remove reference to Java.
* opts.c (strip_off_ending): Update file extension handling.
* tree-cfg.c (verify_gimple_call): Remove comment with Java.
* tree-eh.c (lower_resx): Likewise.
* tree.c (free_lang_data_in_type): Remove dead code.
(find_decls_types_r): Likewise.
(build_common_builtin_nodes): Remove Java from a comment.
(verify_type): Remove dead code.
* varasm.c (assemble_external): Remove Java from a comment.
Martin Liska [Fri, 14 Jul 2017 07:05:27 +0000 (09:05 +0200)]
Remove Pascal language in source code.
2017-07-14 Martin Liska <mliska@suse.cz>
* dbxout.c (get_lang_number): Do not handle GNU Pascal.
* dbxout.h (extern void dbxout_stab_value_internal_label_diff):
Remove N_SO_PASCAL.
* dwarf2out.c (lower_bound_default): Do not handle
DW_LANG_Pascal83.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove default extension binding for GNU Pascal.
* stmt.c: Remove Pascal language from a comment.
* xcoffout.c: Likewise.
David Malcolm [Thu, 13 Jul 2017 19:30:42 +0000 (19:30 +0000)]
diagnostics: fix crash when consolidating out-of-order fix-it hints (PR c/81405)
PR c/81405 identifies a crash when printing fix-it hints from
-Wmissing-braces when there are excess elements.
The fix-it hints are bogus (which I've filed separately as PR c/81432),
but they lead to a crash within the fix-it consolidation logic I added
in r247548, in line_corrections::add_hint.
The root cause is that some of the fix-it hints are out-of-order
with respect to the column numbers they affect, which can lead to negative
values when computing the gap between the fix-it hints, leading to bogus
memcpy calls that generate out-of-bounds buffer accesses.
The fix is to sort the fix-it hints after filtering them, ensuring that
the gap >= 0. The patch also adds numerous assertions to the code, both
directly, and by moving the memcpy calls and their args behind
interfaces (themselves containing gcc_assert).
This fixes the crash; it doesn't fix the bug in -Wmissing-braces that
leads to the bogus hints.
gcc/ChangeLog:
PR c/81405
* diagnostic-show-locus.c (fixit_cmp): New function.
(layout::layout): Sort m_fixit_hints.
(column_range::column_range): Assert that the values are valid.
(struct char_span): New struct.
(correction::overwrite): New method.
(struct source_line): New struct.
(line_corrections::add_hint): Add assertions. Reimplement memcpy
calls in terms of classes source_line and char_span, and
correction::overwrite.
(selftest::test_overlapped_fixit_printing_2): New function.
(selftest::diagnostic_show_locus_c_tests): Call it.
Richard Earnshaw [Thu, 13 Jul 2017 10:01:55 +0000 (10:01 +0000)]
[ARM, VXworks] Fix build
My patch last week to address selection of be8 linking mode broke the
build for vxworks. It turns out that this port is one of the few
remaining that is still not based on the EABI/AAPCS.
This patch fixes the build, but I've not really tested it beyond
building the core compiler binaries. Building a workable compiler
entails downloading a load of vxworks stuff that I'm not sure where to
find.
Michael Meissner [Wed, 12 Jul 2017 23:07:50 +0000 (23:07 +0000)]
re PR target/81193 (PowerPC GCC __builtin_cpu_is and __builtin_cpu_supports should warn about old libraries)
[gcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
provides the hardware capability bits, define the macro
__BUILTIN_CPU_SUPPORTS__.
* config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
if GLIBC does not provide the hardware capability bits. Add a
gcc_unreachable call if the built-in cpu function is neither
__builtin_cpu_is nor __builtin_cpu_supports.
(rs6000_get_function_versions_dispatcher): Change the warning
that an old GLIBC is used which does not export the capability
bits to be an error.
* doc/extend.texi (target_clones attribute): Document the
restriction that GLIBC 2.23 or newer is needed on the PowerPC.
(PowerPC built-in functions): Document that GLIBC 2.23 or newer is
needed by __builtin_cpu_is and __builtin_cpu_supports. Document
the macros defined by GCC if the newer GLIBC is available.
[gcc/testsuite]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
[libgcc]
2017-07-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81193
* configure.ac (PowerPC float128 hardware support): Test whether
we can use __builtin_cpu_supports before enabling the ifunc
handler.
* configure: Regenerate.
re PR target/79883 (avr i18n: untranslated "interrupt" or "signal")
PR target/79883
* config/avr/avr.c (avr_set_current_function): In diagnostic
messages: Quote keywords and (parts of) identifiers.
[WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or
"INTERUPT".
Carl Love [Wed, 12 Jul 2017 15:10:21 +0000 (15:10 +0000)]
rs6000-c.c: Add support for built-in functions vector bool char vec_revb (vector bool char)...
gcc/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_revb (vector bool char);
vector bool short vec_revb (vector short char);
vector bool int vec_revb (vector bool int);
vector bool long long vec_revb (vector bool long long);
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-12 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/p9-xxbr-1.c (rev_bool_char, rev_bool_short,
rev_bool_int): Add test cases for builtins.
* gcc.target/powerpc/p9-xxbr-2.c (rev_long_long, rev_ulong_ulong): Add
test cases for builtins.
Andreas Krebbel [Wed, 12 Jul 2017 15:00:58 +0000 (15:00 +0000)]
S/390: Remove loc splitter
The backend splitter splitting a 3 operand load on condition into 2 is
wrong. The S/390 load on condition instruction might trap on the
memory operand even if the condition is false. So if the first load
on condition overwrites a register used as part of the memory address
of the second the second might trigger a segfault even if it does not
actually perform the load.
Trying to fix this I noticed that the generated code looks anyway
better without the splitter. So removing the splitter entirely is the
way to go here.
gcc/ChangeLog:
2017-07-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
Carl Love [Tue, 11 Jul 2017 14:53:06 +0000 (14:53 +0000)]
rs6000-c.c: Add support for builtins vector unsigned int vec_parity_lsbb (vector signed int)...
gcc/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c.c: Add support for builtins
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
vector unsigned long long vec_parity_lsbb (vector signed long long);
vector unsigned long long vec_parity_lsbb (vector unsigned long long);
* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
gcc/testsuite/ChangeLog:
2017-07-11 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
test cases for the builtins.
David Malcolm [Tue, 11 Jul 2017 13:43:31 +0000 (13:43 +0000)]
diagnostics: support compact printing of secondary locations
gcc/ChangeLog:
* diagnostic-show-locus.c: Include "gcc-rich-location.h".
(layout::m_primary_loc): New field.
(layout::layout): Initialize new field. Move location filtering
logic from here to...
(layout::maybe_add_location_range): ...this new method. Add
support for filtering to just the lines already specified by other
locations.
(layout::will_show_line_p): New method.
(selftest::test_add_location_if_nearby): New test function.
(selftest::diagnostic_show_locus_c_tests): Call it.
* gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
New method.
Tom de Vries [Tue, 11 Jul 2017 12:25:01 +0000 (12:25 +0000)]
Add extra initialization of broadcasted condition variables
2017-07-11 Tom de Vries <tom@codesourcery.com>
* config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG): New macro.
(bb_first_real_insn): New function.
(nvptx_single): Add extra initialization of broadcasted condition
variables.
Daniel Cederman [Tue, 11 Jul 2017 07:18:50 +0000 (07:18 +0000)]
sparc.opt (mfix-ut700): New option.
* config/sparc/sparc.opt (mfix-ut700): New option.
(mfix-gr712rc): Likewise.
(sparc_fix_b2bst): New variable.
* doc/invoke.texi (SPARC options): Document them.
(ARM options): Fix warnings.
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(pass_work_around_errata::gate): Also test sparc_fix_b2bst.
(sparc_option_override): Set sparc_fix_b2bst appropriately.
* config/sparc/sparc.md (fix_b2bst): New attribute.
(in_branch_delay): Prevent stores in delay slot if fix_b2bst.
H.J. Lu [Sun, 9 Jul 2017 18:25:49 +0000 (18:25 +0000)]
x86: Use DRAP only if there are outgoing arguments on stack
Since DRAP is needed only if there are outgoing arguments on stack, we
should track outgoing arguments on stack and avoid setting need_drap to
true when there are no outgoing arguments on stack.
gcc/
PR target/81313
* config/i386/i386.c (ix86_function_arg_advance): Set
outgoing_args_on_stack to true if there are outgoing arguments
on stack.
(ix86_function_arg): Likewise.
(ix86_get_drap_rtx): Use DRAP only if there are outgoing
arguments on stack and ACCUMULATE_OUTGOING_ARGS is false.
* config/i386/i386.h (machine_function): Add
outgoing_args_on_stack.
David Malcolm [Fri, 7 Jul 2017 18:49:09 +0000 (18:49 +0000)]
libcpp: preserve ranges within macro expansions (PR c++/79300)
gcc/testsuite/ChangeLog:
PR c++/79300
* g++.dg/diagnostic/pr79300.C: New test case.
libcpp/ChangeLog:
PR c++/79300
* line-map.c (linemap_macro_loc_to_def_point): Preserve range
information for macro expansions by delaying resolving ad-hoc
locations until within the loop.
rs6000.c (rs6000_get_function_versions_dispatcher): Add warning if GCC was not configured to link against a GLIBC that exports the...
[gcc]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_get_function_versions_dispatcher):
Add warning if GCC was not configured to link against a GLIBC that
exports the hardware capability bits.
(make_resolver_func): Make resolver function private and not a
COMDAT function. Create the name with clone_function_name instead
of make_unique_name.
[gcc/testsuite]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/clone1.c: Add check to make sure the
__builtin_cpu_supports function is fully supported.
* gcc.target/powerpc/clone2.c: New runtime test for
target_clones.
This patch serie adds support for the SPARC M8 processor to GCC.
The SPARC M8 processor implements the Oracle SPARC Architecture 2017.
- bmask* instructions are put in their own instruction type. It makes
little sense to have them in the same category than array
instructions.
- Similarly, VIS compare instructions are put in their own instruction
type. This is to better accommodate subtypes, which are not quite
the same than the subtypes of `visl' instructions.
- The introduction of a new `subtype' insn attribute in sparc.md
avoids the need for adjusting the instruction scheduler DFAs for
previous cpu models every time a new cpu is introduced.
- The full set of SPARC instructions used in sparc.md, and their
position in the type/subtype hierarchy, is documented in a comment.
This eases the modification of the DFA schedulers, and the addition
of new cpus.
- The M7 DFA scheduler is reworked:
+ To use the new type/subtype hierarchy.
+ The v3pipe insn attribute is no longer needed.
+ More accurate latencies for instructions.
+ The C4 core pipeline is documented in a comment in niagara7.md.
- Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN
denomination for M8 and later processors.)
- Support for a new VIS level, VIS4B, covering the new VIS
instructions introduced in OSA2017 and implemented in the M8. Also
built-ins.
- A M8 DFA scheduler:
+ Also based on the new type/subtype hierarchy.
+ The functional units in the C5 core are explicitly documented in a
comment in m8.md.
gcc/ChangeLog:
* config/sparc/m8.md: New file.
* config/sparc/sparc.md: Include m8.md.
* config/sparc/sparc.opt: New option -mvis4b.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
(sparc_option_override): Handle VIS4B.
(enum sparc_builtins): Define
SPARC_BUILTIN_DICTUNPACK{8,16,32},
SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
(check_constant_argument): New function.
(sparc_vis_init_builtins): Define builtins
__builtin_vis_dictunpack{8,16,32},
__builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
__builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
__builtin_vis_fpcmpde{8,16,32}shl and
__builtin_vis_fpcmpur{8,16,32}shl.
(sparc_expand_builtin): Check that the constant operands to
__builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
constant and in range.
* config/sparc/sparc-c.c (sparc_target_macros): Handle
TARGET_VIS4B.
* config/sparc/sparc.h (SPARC_IMM2_P): Define.
(SPARC_IMM5_P): Likewise.
* config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
(enabled): Handle vis4b.
(UNSPEC_DICTUNPACK): New unspec.
(UNSPEC_FPCMPSHL): Likewise.
(UNSPEC_FPUCMPSHL): Likewise.
(UNSPEC_FPCMPDESHL): Likewise.
(UNSPEC_FPCMPURSHL): Likewise.
(cpu_feature): New CPU feature `vis4b'.
(dictunpack{8,16,32}): New insns.
(FPCSMODE): New mode iterator.
(fpcscond): New code iterator.
(fpcsucond): Likewise.
(fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
(fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
(fpcmpde{8,16,32}{si,di}shl): Likewise.
(fpcmpur{8,16,32}{si,di}shl): Likewise.
* config/sparc/constraints.md: Define constraints `q' for unsigned
2-bit integer constants and `t' for unsigned 5-bit integer
constants.
* config/sparc/predicates.md (imm5_operand_dictunpack8): New
predicate.
(imm5_operand_dictunpack16): Likewise.
(imm5_operand_dictunpack32): Likewise.
(imm2_operand): Likewise.
* doc/invoke.texi (SPARC Options): Document -mvis4b.
* doc/extend.texi (SPARC VIS Built-in Functions): Document the
ditunpack* and fpcmp*shl builtins.
* config.gcc: Handle m8 in --with-{cpu,tune} options.
* config.in: Add HAVE_AS_SPARC6 define.
* config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
M8.
* config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
TARGET_CPU_m8.
(ASM_CPU32_DEFAUILT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle m8.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc-opts.h (enum processor_type): Add
PROCESSOR_M8.
* config/sparc/sparc.c (m8_costs): New struct.
(sparc_option_override): Handle TARGET_CPU_m8.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
(sparc_issue_rate): Likewise.
(sparc_register_move_cost): Likewise.
* config/sparc/sparc.h (TARGET_CPU_m8): Define.
(CPP_CPU64_DEFAULT_SPEC): Define for M8.
(ASM_CPU64_DEFAULT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle M8.
(ASM_CPU_SPEC): Likewise.
(AS_M8_FLAG): Define.
* config/sparc/sparc.md: Add m8 to the cpu attribute.
* config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
* configure.ac (HAVE_AS_SPARC6): Check for assembler support for
M8 instructions.
* configure: Regenerate.
* doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
-mtune=m8.
Jan Hubicka [Fri, 7 Jul 2017 13:28:35 +0000 (15:28 +0200)]
ipa-comdats.c: Remove optimize check from gate.
* ipa-comdats.c: Remove optimize check from gate.
* ipa-fnsummary.c (ipa_fn_summary_generate): do not generate summary
for functions not optimized.
(ipa_fn_summary_read): Skip optimize check.
(ipa_fn_summary_write): Likewise.
* ipa-inline-analysis.c (do_estimate_growth_1): Check that caller
is optimized.
* ipa-inline.c (can_inline_edge_p): Not optimized functions are
uninlinable.
(can_inline_edge_p): Check flag_pcc_struct_return for match.
(check_callers): Give up on caller which is not optimized.
(inline_small_functions): Likewise.
(ipa_inline): Do not give up when not optimizing.
* ipa-visbility.c (function_and_variable_visibility): Do not optimize
away unoptimizes cdtors.
(whole_program_function_and_variable_visibility): Do
ipa_discover_readonly_nonaddressable_vars in LTO mode.
* ipa.c (process_references): Do not check optimize.
(symbol_table::remove_unreachable_nodes): Update optimize check.
(set_writeonly_bit): Update optimize check.
(pass_ipa_cdtor_merge::gate): Do not check optimize.
(pass_ipa_single_use::gate): Remove.
Jan Hubicka [Thu, 6 Jul 2017 16:47:20 +0000 (18:47 +0200)]
lto-wrapper.c (merge_and_complain): Do not merge fexceptions...
* lto-wrapper.c (merge_and_complain): Do not merge
fexceptions, fnon_call_exceptions, ftrapv, ffp_contract_, fmath_errno,
fsigned_zeros, ftrapping_math, fwrapv.
(append_compiler_options): Do not track these options.
(append_linker_options): Likewie
Jan Hubicka [Thu, 6 Jul 2017 16:46:47 +0000 (18:46 +0200)]
cgraphunit.c (cgraph_node::finalize_function): When !flag_toplevel_reorde set no_reorder flag.
* cgraphunit.c (cgraph_node::finalize_function): When
!flag_toplevel_reorde set no_reorder flag.
(varpool_node::finalize_decl): Likewise.
(symbol_table::compile): Drop no toplevel reorder path.
* lto-partition.c (lto_balanced_map): Do not check
flag_toplevel_reorder.
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