Add default STM32MP13xx debug UART initialization. This is similar
to STM32MP15xx debug UART initialization, except the RCC registers
are at different offsets and the UART pinmux pins are different.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:30 +0000 (02:10 +0200)]
ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type
The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
to the STM32MP15xx PMIC initialization, except the VTT rail is not
enabled. Fill in the STM32MP13xx support.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:29 +0000 (02:10 +0200)]
ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:27 +0000 (02:10 +0200)]
ARM: stm32: Add STM32MP13xx SPL Kconfig options
Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Andrew Goodbody [Thu, 24 Jul 2025 11:37:38 +0000 (12:37 +0100)]
clk: stm32: Wrong macros used in register read
Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Alice Guo [Mon, 7 Jul 2025 20:20:34 +0000 (04:20 +0800)]
clk: scmi: Fix clock identifier passed to struct scmi_clk_parent_set_in
Commit aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.
Fixes: aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CCF")
Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Mon, 30 Jun 2025 00:09:07 +0000 (02:09 +0200)]
reset: stm32: Fix header misuse
The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.
Cheick Traore [Fri, 20 Jun 2025 15:50:00 +0000 (17:50 +0200)]
configs: stm32mp25: Enable MFD timer and PWM for stm32mp25_defconfig
Enable the following configs:
- CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
timer
- CONFIG_DM_PWM: enables support for pulse-width modulation devices
- CONFIG_CMD_PWM: enables 'pwm' command to control PWM channels
- CONFIG_PWM_STM32: enables support for the STM32 PWM devices
Cheick Traore [Fri, 20 Jun 2025 15:49:59 +0000 (17:49 +0200)]
pwm: stm32: add support for stm32mp25
Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.
Cheick Traore [Fri, 20 Jun 2025 15:49:58 +0000 (17:49 +0200)]
arm: stm32mp2: add multifunction timer support for stm32mp25
Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.
In a private fork, it's not unreasonable to commit various binary
files associated to one's project, and thus put a suitable
.gitattributes file next to it to force git to treat that file as
binary. In my case, I have a .xslx spreadsheet used for computing
suitable RAM timing tables, which I wanted to put in
board/<vendor>/<project>. Git duly warned me that it would do LF/CRLF
mangling, so I also added a .gitattributes file next to it with
*.xlsx binary
but upon adding that file, git told me that I'd have to use -f because
it's a dot-file that is by default ignored.
Add .gitattributes to the list of dot-files that should not be
ignored.
While in here, sort the list and update the comment, as there are also
files which git itself does not make use of in the list, cf. linux
commit f46e65da48b2 (".gitignore: exclude .get_maintainer.ignore and
.gitattributes").
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew Goodbody [Mon, 21 Jul 2025 14:43:36 +0000 (15:43 +0100)]
cmd: elf: Prevent possible buffer overflow
In do_bootvx the environment variable 'bootdev' is fetched and copied
into a buffer without confirming that it will not overflow that buffer.
Use strlcpy to ensure that the buffer will not be overflowed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Tom Rini [Mon, 28 Jul 2025 14:08:16 +0000 (08:08 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These patches add support for the new Allwinner A523/A527/T527 SoC (all
same die), alongside with defconfigs for three boards using one of those
SoCs.
The patches are the usual combination of refactoring (of the SPL clock
code this time), tweaks to existing drivers to support peripherals in
their A523 versions, and new drivers for pincontrol and clocks. A big
chunk is of course the DRAM controller init routines, many thanks to
Jernej and Mikhail for providing this code, after a big reverse
engineering effort.
Since the DTs for the three supported boards have been merged into the
kernel repo recently, this is concluded by cherry-picks of those
patches, and the defconfig files to finally enable booting those boards.
The patches have been sitting around for a while, and folks are already
using them, so it's now time to get them into the tree.
Gitlab CI passed, and I booted that briefly on those three boards, plus
on some other SoCs to spot potential regressions.
Andre Przywara [Tue, 21 Jan 2025 21:55:07 +0000 (21:55 +0000)]
sunxi: A523: add defconfigs for three boards
So far developers seem to use three popular boards:
- Avaota A1: dev board with USB 3.0, dual Ethernet, small display
- X96QPro+: TV box with Gigabit Ethernet, USB 3.0, eMMC
- Radxa A5E: small dev board with USB3/M.2 2230 (muxed), dual Ethernet
Add the defconfig files for those boards, containing the DRAM parameters
and the usual Kconfig options.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 7 Mar 2025 00:57:08 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add Avaota-A1 router support
The Avaota A1 router board is an Open Source hardware board, designed
by YuzukiHD. Pine64 produces some boards and sells them. It uses the
Allwinner A527 or T527 SoC, and comes with the following features:
- Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMIC
- Raspberry-Pi-2 compatible GPIO header
- 1 USB 2.0 type A host port, 1 USB 3.0 type A host post
- 1 USB 2.0 type C port (OTG + serial debug)
- MicroSD slot
- eMMC between 16 and 128 GiB
- on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via RTL8211F PHYs)
- HDMI port
- DP port
- camera and LCD connectors
- 3.5mm headphone jack
- (yet) unsupported WiFi/BT chip
- 1.3" LC display, connected via SPI
- 12 V barrel plug for power supply
Add the devicetree file describing the currently supported features.
Andre Przywara [Fri, 7 Mar 2025 00:57:10 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add Radxa A5E support
The Radxa A5E is a development board using the Allwinner A527 SoC, which
is using the same die as the A523 SoC, just exposing the pins of more
peripherals (like HDMI or the 2nd MAC). The board features:
- Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMICs
- Raspberry-Pi-2 compatible 40pin GPIO header
- 1 USB 2.0 type C port (OTG), also power supply
- 1 USB 3.0 type A host port (multiplexed with M.2 slot)
- 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed
with USB 3.0 port)
- MicroSD slot
- optional eMMC, 8, 16 or 32GB available
- optional on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs)
- PoE header for optional supply circuit on one Ethernet port
- WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800)
- HDMI port
- camera and LCD connectors
- power supply via USB-C connector (but no PD) or GPIO header pins
This .dts describes the devices as far as we support them at the moment.
The PMIC rails have been assigned as per the schematics.
Andre Przywara [Fri, 7 Mar 2025 00:57:09 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add X96Q-Pro+ support
The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to
be a package variant of the A523 family, at least it uses the same SoC
ID and is compatible as far as we can assess.
It comes with the following specs:
- Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU
- 2 or 4GiB DDR3L DRAM
- 32, 64, or 128 GiB eMMC flash
- AXP717 + AXP323 PMICs
- Gigabit Ethernet (using MAXIO PHY)
- HDMI port
- 2 * USB 2.0 ports
- 1 * USB 3.0 port
- microSD card slot
- TOSLINK digital audio output
- 3.5mm A/V port
- infrared sensor
- 7-segment display
- 5V barrel plug power supply
- power button
The PCB provides holes for soldering a UART header or cable, this is
connected to the debug UART0. There is another set of UART pins
available. The board also features a FEL button (accessible through the
3.5mm socket) and a reset button (only accessible when case is open).
This .dts just describes the basic peripherals as far as we support them
at the moment. The PMIC rail assignments are reverse engineered as far
as possible, by dumping them from a running Android system, and correlating
them to other boards using the same SoC.
The Allwinner A523, and its siblings A527 and T527, which share the same
die, are a new family of SoCs introduced in 2023. They features eight
Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and
USB 3.0 controller.
Add the basic SoC devicetree .dtsi for the chip, describing the
fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl.
Also some other peripherals are fully compatible with previous IP, so
add the USB and MMC nodes as well.
The other peripherals will be added in the future, once we understand
their compatibility and DT requirements.
Add reverse engineered code to add support for DDR3 DRAM chips on the
Allwinner A523 DRAM controller.
The timings are copying what boot0 set up on the X96QPro+ TV box, though
they seem quite suboptimal, with longer latencies that would be required
for DDR3-1600. The chips are also actually capable of DDR3-1833, so
there is room for future improvement.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
[Andre: rework to copy from H616 DDR3 driver, calculate timings] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Sun, 29 Dec 2024 20:13:13 +0000 (21:13 +0100)]
sunxi: A523: add DRAM initialisation routine
DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.
This version supports LPDDR4 for now only, as seen on the early boards.
This needs improvements, but it can be done later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Sat, 24 Aug 2024 16:58:28 +0000 (17:58 +0100)]
sunxi: sun50i_h6: add A523 SPL clock setup code
This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 2 Jan 2025 00:52:27 +0000 (00:52 +0000)]
sunxi: update cpu_sunxi_ncat2.h
The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.
Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 12 Sep 2024 01:19:45 +0000 (02:19 +0100)]
sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 13 Sep 2024 08:01:00 +0000 (09:01 +0100)]
clk: sunxi: Add support for the A523 -R CCU
Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 9 Sep 2024 00:47:31 +0000 (01:47 +0100)]
clk: sunxi: Add support for the A523 CCU
Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 29 Dec 2024 20:13:13 +0000 (21:13 +0100)]
sunxi: spl: add support for Allwinner A523 watchdog
The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.
Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:41:37 +0000 (13:41 +0000)]
sunxi: clock: H6: add A523 CPU PLL support
The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.
Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.
The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:40:05 +0000 (13:40 +0000)]
sunxi: clock: H6: factor out H6/H616 CPU clock setup
When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.
The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:29:34 +0000 (13:29 +0000)]
sunxi: clock: H6: factor out clock_set_pll()
The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.
So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.
Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* update FIT signature testing instructions
* describe defconfigs for AM69-SK
UEFI:
* provide unit test for system table pointer
* efi_realloc() must check efi_alloc() return value
* correct EFI_DEBUG_TABLE_ENTRY_SIZE
* avoid NULL dereference in ESRT creation tests
* add missing check in FMP.GetImageInfo()
* rename lib/efi to lib/efi_client
* rename CONFIG_EFI to CONFIG_EFI_CLIENT
* create a new CONFIG_EFI
* update maintainers for EFI_CLIENT
efi_loader: add missing check in FMP.GetImageInfo()
The UEFI 2.11 specification, chapter 23.1.3 requires
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() to return
EFI_INVALID_PARAMETER if *ImageInfoSize is not too small
and ImageInfo is NULL.
Fixes: f27c20148511 ("efi_loader: add firmware management protocol for FIT image") Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
With the current code we allocate to little memory when adding entries to
the EFI_DEBUG_INFO_TABLE and we fail to correctly move entries when an
entry is removed.
EFI_DEBUG_TABLE_ENTRY_SIZE must be the size of an entry in the
EFI_DEBUG_INFO_TABLE, not the size of a pointer.
Simon Glass [Wed, 28 May 2025 16:03:16 +0000 (10:03 -0600)]
efi: Create a new CONFIG_EFI
Create a Kconfig which indicates that EFI functionality is in use,
either as a client (EFI app / stub) or provider (EFI loader). This will
make it easier to share code between these two parts of U-Boot
Tom Rini [Fri, 25 Jul 2025 19:03:01 +0000 (13:03 -0600)]
Docker, CI: Update to latest Ubuntu and Dockerfile
- Update to Ubuntu "Jammy" 20250714 tag
- Update to current Dockerfile which brings us QEMU 10.0.2 and newer
coreboot and pulls in lz4 via the non-legacy package name.
Tom Rini [Fri, 25 Jul 2025 16:55:45 +0000 (10:55 -0600)]
Merge patch series "CI: Disable sifive_unleashed_sdcard QEMU testing"
This series from myself brings CI up to using QEMU 10.0.2 for platforms.
We need to disable one test for now while a report to upstream QEMU is
resolved and also need to now update coreboot in order to be able to
build a version of it non-interactively (source locations have changed).
Tom Rini [Wed, 16 Jul 2025 00:15:37 +0000 (18:15 -0600)]
CI: Disable sifive_unleashed_sdcard QEMU testing
Changes in upstream QEMU have lead to this specific configuration of the
sifive_unleashed platform not working in QEMU. Until this can be
root caused and resolved, disable this test for now.
Sam Protsenko [Wed, 9 Jul 2025 22:29:26 +0000 (17:29 -0500)]
doc: samsung: Describe flashing process for E850-96
Now that USB is enabled on the E850-96 board, DFU and fastboot tools are
functional and can be used to flash images to eMMC. Update the E850-96
documentation accordingly and describe flashing to User Data Area and
Boot HW Partition of eMMC using fastboot and DFU tools.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Make it possible to update E850-96 firmware binaries using EFI Capsule
Update mechanism. For example, to update the U-Boot binary, the capsule
file can be generated like this:
The resulting 'capsule4.bin' should be copied to ESP partition (in
/boot/efi/EFI/UpdateCapsule/ directory). Then after reboot U-Boot will
update the 'bootloader' area in eMMC Boot Partition A (boot0) and remove
the capsule file, by EFI boot manager executed as a part of Standard
Boot:
Applying capsule capsule4.bin succeeded.
Reboot after firmware update.
The kernel will also expose the ESRT table information via SysFS in
/sys/firmware/efi/esrt/entries.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 9 Jul 2025 22:29:24 +0000 (17:29 -0500)]
configs: e850-96: Enable USB gadget and fastboot
Now that USB phy and dwc3 glue layer was added for Exynos850, USB gadget
is functional on E850-96 board. Enable next features to make it useful:
- Exynos850 USB PHY driver (needed for all USB functions)
- dwc3 generic driver
- USB gadget
- CONFIG_DM_USB_GADGET: needed for DWC3 glue layer to instantiate the
peripheral driver, i.e. dwc3_generic_peripheral_probe()
- USB VID and PID
- DFU
- Fastboot (including flashing to eMMC boot partitions)
As all Exynos firmware binaries (including U-Boot) are contained in eMMC
boot partition A (mmc0boot0), because that's where Boot ROM code jumps,
it might be useful to be able to flash that area with fastboot. Other
more fine grained choices for updating the firmware would be DFU and EFI
Capsule Update mechanism.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 9 Jul 2025 22:29:23 +0000 (17:29 -0500)]
configs: e850-96: Increase malloc() pool size
"fastboot flash" tries to malloc 8 MiB buffer after receiving data over
USB and trying to write it to eMMC. Right now only 8.12 MiB malloc is
available for E850-96 overall, which leads to this issue:
Malloc failed for: CHUNK_TYPE_RAW
Fix it by increasing malloc pool size from 8.12 MiB up to 32 MiB, like
it's done in many other boards using fastboot.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 9 Jul 2025 22:29:22 +0000 (17:29 -0500)]
board: samsung: e850-96: Add Android partitions
Matches downstream Android-Q partition table created by flashing the
modified gpt.img [1], with added ESP partition (EFI System Partition).
It's an A/B slotted Android partition table, so it's possible to boot
Android from this table using Android GBL EFI app. Tested using
AOSP/main images for E850-96 with booting via GBL app.
Sam Protsenko [Wed, 9 Jul 2025 22:29:21 +0000 (17:29 -0500)]
board: samsung: e850-96: Add dfu_alt_info
Add 'dfu_alt_info' environment variable which contains:
- Linux eMMC partitions ('esp' and 'rootfs')
- eMMC Boot Partition A layout, where all the firmware reside
It makes it possible to update the bootloader (U-Boot). All sizes in
'dfu_alt_info' are given in 512B blocks (LBA). eMMC size is 58.2 GiB.
The eMMC Boot Partition A (mmc0boot0) layout looks like this:
where U-Boot should be flashed into 'bootloader' partition. So U-Boot
binary size should be 2 MiB or less. The whole boot0 partition is 4 MiB,
but only 2.8 MiB is currently used.
With this change, the U-Boot binary can be updated on eMMC like this:
Looking at E850-96 booting diagram at [1,2], it's easy to see how these
binaries are being executed in the same order they are placed in
mmc0boot0 area. E.g. fwbl1 is definitely BL1 (software part of Boot
ROM). So it's obvious the ROM code just reads the binary from eMMC at
0x0 offset into RAM (SRAM?) and executes it.
All mentioned images can be found at [3], as stated in E850-96 U-Boot
documentation. 'dram_train', 'ect_test' and 'acpm_test' areas should be
ignored -- they are not flashed with real images.
Sam Protsenko [Wed, 9 Jul 2025 22:29:20 +0000 (17:29 -0500)]
board: samsung: e850-96: Setup serial# env var
Setup "serial#" environment variable from the chip ID. The chip ID is
read from Exynos850 SoC OTP (One Time Programmable) memory, which acts
like an EEPROM and contains unique SoC ID. This "serial#" variable is
further used for "fastboot devices" serial number, etc.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 9 Jul 2025 22:29:19 +0000 (17:29 -0500)]
usb: dwc3-generic: Add Exynos850 support
The only thing needed from DWC3 glue layer for Exynos850 is to enable
USB clocks. The generic glue layer driver already does that. Add
Exynos850 dwc3 compatible string to enable support for this chip.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 9 Jul 2025 22:29:18 +0000 (17:29 -0500)]
phy: samsung: Add Exynos USB DRD PHY driver
Add DM driver for Exynos USB PHY controllers. For now it only supports
Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as
Exynos850 doesn't support USB 3.0. Only two clocks are used for this
controller:
- phy: bus clock, used for PHY registers access
- ref: PHY reference clock (OSCCLK)
Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
Tom Rini [Thu, 24 Jul 2025 17:50:25 +0000 (11:50 -0600)]
Merge patch series "Add support for K3 BIST"
Neha Malcom Francis <n-francis@ti.com> says:
This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.
At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.
The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence
BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.
Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603
arm: dts: k3: use SPL_TEXT_BASE for R5 SPL load address
The load address for the R5's SPL is defined in Kconfig by
SPL_TEXT_BASE. Rather than hard coding the load address which could
lead to hard to debug issues if this value is changed, just use the
SPL_TEXT_BASE value.
Reviewed-by: Andrew Davis <afd@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Andrew Goodbody [Thu, 17 Jul 2025 15:29:21 +0000 (16:29 +0100)]
fs: exfat: Remove unused label code
Smatch reported a possible buffer overflow in exfat_set_label but it
turns out that this code is unused so just guard the function with
'#ifndef __UBOOT__' as well as exfat_get_label that is also unused and
the helper static find_label.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Sam Protsenko [Thu, 17 Jul 2025 02:44:26 +0000 (21:44 -0500)]
treewide: Remove empty board_init() function from all boards
Commit 86acdce2ba88 ("common: add config for board_init() call")
introduced CONFIG_BOARD_INIT option. This option can be disabled for the
boards where board_init() function is not needed. Remove empty
board_init() calls for all boards where it's possible, and disable
CONFIG_BOARD_INIT in all related defconfigs.
This cleanup was made semi-automatically using these scripts: [1].
No functional change, but the binary size for the modified boards is
reduced a bit.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon Tested-by: Bryan Brattlof <bb@ti.com> Acked-by: Peng Fan <peng.fan@nxp.com> #NXP boards
Add a driver for the BIST module that support triggering of both PBIST
(Memory BIST) and LBIST (Logic BIST) tests. Also expose the relevant
operations and functions that would be required for an end user to
trigger the tests.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
The 'overhead' variable is uninitialized and actually shall not be used.
Delete it to fix coverity CID 37041718 - Uninitialized scalar variable.
Fixes: 73c40fcb7367 ("spl: Refactor spl_load_info->read to use units of bytes") Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 22 Jul 2025 13:40:24 +0000 (14:40 +0100)]
imx93: adc: local variable ret should not be unsigned
Local variable ret is declared as unsigned but is used to receive the
return value of functions that return int. ret is then tested for being
negative which must always fail. Change ret to be an int.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
board: phytec: migrate imx8mm boards to standard boot
remove boot logic from shared env file for phyboard-polis and
phygate-tauri.
Adjust configs for both boards as well.
Space at the beginning of addressable RAM is reserved for space used via
standard boot env variables. CONFIG_SYS_LOAD_ADDR is set to the lowest
address behind the standard boot variables reserved space.
imx: power-domain: Fix crash due to uninitialized 'id' field
In case of the i.MX8M power-domains (i.MX8MQ, MM, MN) there is only
one power-domain for each device. Therefore the 'id' field in struct
power_domain should always be zero.
Currently if a power-domain is accessed after the initial bind, the
'id' field is left uninitialized. This didn't cause any problems
until the following commits were introduced:
9086b64ca071 ("power-domain: Add support for refcounting (again)") a785ef24487b ("imx: power-domain: Enable refcounting on imx8mp")
Now the 'id' field gets accessed in the power_domain_off() sequence
and the invalid value causes "Synchronous Abort" failures.
This was observed on a i.MX8MM board when running "usb start" and
then "usb stop".
Fix this issue by setting power_domain->id to '0' in
imx8m_power_domain_of_xlate().
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Fixes: d08a194871fd ("imx: add support for i.MX8MQ power domain controller") Fixes: 9086b64ca071 ("power-domain: Add support for refcounting (again)") Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
board: phytec: phycore-imx93: Drop unused PMIC define
Drop unused define for PCA9450 PMIC register which is already part of
the header file <power/pca9450.h> since commit 1d0d25704345 ("imx93_evk:
spl: update pmic settings").
CONFIG_IS_ENABLED macro is covering CONFIG_POWER_DOMAIN or
CONFIG_SPL_POWER_DOMAIN Kconfig symbols based on build target which
simplify logic around binding power domain driver.
The buffer that is being used to write into the flash needs
to be handled properly with padding of 0xFF. The place that
this is done can be at a more generic place like spi-nor core.
net: xilinx: Fix kernel-doc for axi_mrmac function parameters
The kernel-doc comment for the axi_mrmac_recv function was missing
the colon (':') after the '@packetp' parameter tag.
The kernel-doc comment for the axi_mrmac_free_pkt function was missing
the colon (':') after the 'length' parameter tag.
This caused a Sparse warnings regarding the 'packetp' and 'length'
parameters not being described. Fix the formatting to align
with kernel-doc standards and resolve the warning.
drivers/net/xilinx_axi_mrmac.c:357:
warning: Function parameter or member 'packetp' not described
in 'axi_mrmac_recv'
drivers/net/xilinx_axi_mrmac.c:411:
warning: Function parameter or member 'length' not described
in 'axi_mrmac_free_pkt'
drivers: fpga: fix function declaration without a prototype
As reported by clang 20.1, fix multiple of the following:
drivers/fpga/ivm_core.c:593:23: error: a function declaration without
a prototype is deprecated in all versions of C
[-Werror,-Wstrict-prototypes]
593 | long int ispVMDataSize()
| ^
| void
Also fix the following warning from checkpatch.pl:
WARNING: Prefer 'long' over 'long int' as the int is unnecessary
drivers: fpga: correct compiler errors and warnings
Errors reported by GCC 14.2 when enabling FPGA commands and
drivers. Also many style fixes as reported by checkpatch.pl on the
diffs. Most changes in stratixII.c which has been reorganized as well
to avoid the top function prototypes.
projects / thirdparty / u-boot.git / log
