Matthew Wahab [Thu, 10 Dec 2015 13:58:21 +0000 (13:58 +0000)]
[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.
This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
include/opcode
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
AARCH64_FEATURE_V8_1.
(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
AARCH64_FEATURE_V8_1.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch adds the new FP16 instructions,
making them available when the architecture extension +fp+fp16 is
specified.
The instructions added are:
- Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL.
- Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB,
FNMADD and FNMSUB.
- Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI.
- Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point)
UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU
(fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU,
FCVTPS, FCVTPU, FCVTMS and FCVTMU.
- Scalar FMOV: immediate, general and register
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 16:25:52 +0000 (16:25 +0000)]
[AArch64][PATCH 2/3] Adjust a utility function for floating point values.
ARMv8.2 adds 16-bit floating point operations as an optional
extension. This patch adjusts the utility function expand_fp_imm to
support 16-bit values.
The function is intended to convert an 8-bit immediate representing a
floating point value to a representation that can be passed to
fprintf. Because of the limited use of the results, the only change made
to the function is to treat a request for a 16-bit float as a request
for a 32-bit float.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (half_conv_t): New.
(expand_fp_imm): Replace is_dp flag with the parameter size to
specify the number of bytes for the required expansion. Treat
a 16-bit expansion like a 32-bit expansion. Add check for an
unsupported size request. Update comment.
(aarch64_print_operand): Update to support 16-bit floating point
values. Update for changes to expand_fp_imm.
Matthew Wahab [Fri, 27 Nov 2015 15:47:53 +0000 (15:47 +0000)]
[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch set adds support for the 16-bit FP
instructions to binutils, enabling the instructions when both +fp and
+fp16 architecture extensions are enabled.
The patches in this series:
- Add a feature macro for use by the encoding/decoding mechanism.
- Adjust a utility function, used when disassembling, to support 16-bit
floating point values.
- Add the new scalar floating-point instructions.
This patch adds the feature macro FP_F16 to the AArch64 encoding/decoding
mechanism, enabling it when both +fp and +fp16 are selected.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 15:25:08 +0000 (15:25 +0000)]
[AArch64] Add ARMv8.2 instructions BFC and REV64.
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.
This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 15:02:26 +0000 (15:02 +0000)]
[AArch64] Let aliased instructions be their preferred form.
Although the AArch64 backend supports aliased instructions, the aliasing
forms are always preferred over the real instruction. This makes it
awkward to handle instructions which have aliases but which are their
own preferred form.
This patch includes the instruction being aliased in the list of
alternatives which is searched when considering which form to use.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c: Weaken assert.
* aarch64-gen.c: Include the instruction in the list of its
possible aliases.
Matthew Wahab [Fri, 27 Nov 2015 13:44:10 +0000 (13:44 +0000)]
[Aarch64] Support an ARMv8.2 system register.
ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds
support for the register to binutils, making it available when
-march=armv8.2-a is selected.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 13:19:50 +0000 (13:19 +0000)]
[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.
ARMv8.2 adds optional support for 16-bit operations to the FP and
Adv.SIMD instructions. This patch adds a feature macro for this support
with a new command line option "+fp16" to enable/disable it.
Although the command line option is added as an architecture extension,
it only affects instructions available with when +fp or +simd is
enabled. If +fp16 is specified then it will also enable +fp.
There are currently no FP16 instructions implemented in binutils, this
patch is to enable subsequent work on supporting the extension.
gas/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 20 Nov 2015 16:09:34 +0000 (16:09 +0000)]
[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.
The ARMv8.1 architecture includes the Virtualization Host Extensions
which add a number of system registers. This patch adds support for
these system registers, making them available when -march=armv8.1-a is
selected.
include/opcode/
2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 19 Nov 2015 09:24:14 +0000 (09:24 +0000)]
[ARM] Add ARMv8.2 architecture feature and command line option.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.
gas/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 19 Nov 2015 09:12:49 +0000 (09:12 +0000)]
[AArch64] Add ARMv8.2 command line option and feature flag.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.
gas/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.
In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.
This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.
* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
TAG_ARCH_profile for armv8-a.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
Maxim Kuvyrkov [Wed, 4 Nov 2015 13:52:34 +0000 (14:52 +0100)]
Fix detection of GNU LD version in GCC's scripts
GCC's configure scripts are confused by YYYY.MM format of Linaro releases
and mistake YYYY for major version (currently 2) and MM for minor version
(currently 25). This, in turn, makes GCC think that GNU LD doesn't support
plugins, which disables -fuse-linker-plugin functionality used by LTO.
This problem was already fixed before, and there is a comment about avoiding
"." in the BFD_VERSION_STRING, but, for reasons I can't explain, the problem
occurred again. So fixing it ... again.
Alan Modra [Sat, 25 Jul 2015 07:08:42 +0000 (16:38 +0930)]
Fix broken -Bsymbolic-functions
For selected targets. The testcase reveals a number of targets that
still need fixing.
bfd/
* elf32-arm.c (elf32_arm_final_link_relocate): Use SYMBOLIC_BIND to
check if a symbol should be bound symbolically.
* elf32-hppa.c (elf32_hppa_check_relocs,
elf32_hppa_adjust_dynamic_symbol, elf32_hppa_relocate_section,
elf32_hppa_finish_dynamic_symbol): Likewise.
* elf32-m68k.c (elf_m68k_check_relocs,
elf_m68k_relocate_section): Likewise.
* elf32-nios2.c (nios2_elf32_relocate_section,
nios2_elf32_check_relocs, allocate_dynrelocs): Likewise.
* elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol,
elf32_tic6x_relocate_section): Likewise.
ld/testsuite/
* ld-elf/symbolic-func.s,
* ld-elf/symbolic-func.r: New test.
* ld-elf/elf.exp: Run it.
Terry Guo [Tue, 24 Mar 2015 06:08:08 +0000 (14:08 +0800)]
Extend arm_feature_set struct to provide more bits
gas/ChangeLog:
2015-03-24 Terry Guo <terry.guo@arm.com>
* config/tc-arm.c (no_cpu_selected): Use new macro to compare
features.
(parse_psr): Likewise.
(do_t_mrs): Likewise.
(do_t_msr): Likewise.
(static const arm_feature_set arm_ext_*): Defined with new
macros.
(static const arm_feature_set arm_cext_*): Likewise.
(static const arm_feature_set fpu_fpa_ext_*): Likewise.
(static const arm_feature_set fpu_vfp_ext_*): Likewise.
(deprecated_coproc_regs): Likewise.
(UL_BARRIER): Likewise.
(barrier_opt_names): Likewise.
(arm_cpus): Likewise.
(arm_extensions): Likewise.
include/opcode/ChangeLog:
2015-03-24 Terry Guo <terry.guo@arm.com>
* arm.h (arm_feature_set): Extended to provide more available
* bits.
(ARM_ANY): Updated to follow above new definition.
(ARM_CPU_HAS_FEATURE): Likewise.
(ARM_CPU_IS_ANY): Likewise.
(ARM_MERGE_FEATURE_SETS): Likewise.
(ARM_CLEAR_FEATURE): Likewise.
(ARM_FEATURE): Likewise.
(ARM_FEATURE_COPY): New macro.
(ARM_FEATURE_EQUAL): Likewise.
(ARM_FEATURE_ZERO): Likewise.
(ARM_FEATURE_CORE_EQUAL): Likewise.
(ARM_FEATURE_LOW): Likewise.
(ARM_FEATURE_CORE_LOW): Likewise.
(ARM_FEATURE_CORE_COPROC): Likewise.
opcodes/ChangeLog:
2015-03-24 Terry Guo <terry.guo@arm.com>
* arm-dis.c (opcode32): Updated to use new arm feature struct.
(opcode16): Likewise.
(coprocessor_opcodes): Replace bit with feature struct.
(neon_opcodes): Likewise.
(arm_opcodes): Likewise.
(thumb_opcodes): Likewise.
(thumb32_opcodes): Likewise.
(print_insn_coprocessor): Likewise.
(print_insn_arm): Likewise.
(select_arm_features): Follow new feature struct.
Jan Beulich [Wed, 7 Jan 2015 08:39:27 +0000 (09:39 +0100)]
arm: fix extension feature disabling
Using e.g.
.arch_extension simd
.arch_extension nocrypto
so far results in SIMD support getting disabled, which I can't see being
the purpose of the "no"-prefixed variants of architecture extension
specifications.
Of course it is questionable whether the current, counter intuitive
behavior needs to be retained, and the new behavior perhaps be made work
through e.g. a newly recognized "no-" prefix.
gas/
2015-01-07 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (struct arm_option_extension_value_table):
Split field "value" into fields "merge_value" and "clear_value".
(arm_extensions): Adjust initializer accordingly.
Matthew Wahab [Mon, 1 Jun 2015 15:00:28 +0000 (16:00 +0100)]
[AArch64][libopcode] Add support for PAN architecture extension
The ARMv8.1 architecture introduced the Privileged Access Never extension. This
adds a processor state field PSTATE.PAN which can be accessed using the MRS/MSR
instructions.
This patch adds support for the PAN architecture feature and processor state
field to libopcode.
include/opcode
2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
The first and second exception_code invocations create the
.text.exception and the .init.exception sections respectively. This is
useful e.g. to discriminate between anciliary sections that are tied to
.init code and can be discarded at run time when initialization is over
vs anciliary sections tied to .text sections that need to stay resident.
Marcus Shawcroft [Tue, 24 Feb 2015 12:04:41 +0000 (12:04 +0000)]
Workaround for Cortex A53 erratum 843419
Some early revisions of the Cortex-A53 have an erratum (843419). The
details of the erratum are quite complex and involve dynamic
conditions. For the purposes of the workaround we have simplified the
static conditions to an ADRP in the last two instructions of a 4KByte
page, followed within four instructions by a load/store dependent on
the ADRP.
This patch adds support to conservatively scan for and workaround
Cortex A53 erratum 843419. There are two different workaround
strategies used. The first is to rewrite ADRP instructions which form
part of an erratum sequence with an ADR instruction. In situations
where the ADR provides insufficient offset the dependent load or store
instruction from the sequence is moved to a stub section and branches
are inserted from the original sequence to the relocated instruction
and back again.
Stub section sizes are rounded up to a multiple of 4096 in order to
ensure that the act of inserting work around stubs does not create
more errata sequences.
Workaround stubs are always inserted into the stub section associated
with the input section containing the erratum sequence. This ensures
that the fully relocated form of the veneered load store instruction
is available at the point in time when the stub section is written.
Marcus Shawcroft [Sun, 22 Mar 2015 08:31:18 +0000 (08:31 +0000)]
Implement branch over stub section.
Ensure that injection of a stub section does not break a link where
there is an xpectation that flow of control can pass from one input
section to another simply by linking the input sections in series.
The solution here is to allow stub sections to be inserted after any
input section (existing behaviour), but inject an additional branch at
the start of each stub section such that control flow falling into the
stub section will branch over the stub section.
Marcus Shawcroft [Sat, 28 Feb 2015 00:17:22 +0000 (00:17 +0000)]
Refactor section_group[] representation.
Change the behaviour of section_group[] such that .stub_sec points to
the stub section attached to the indexed section rather than the stub
section attached to the link_section pointed to be the index section.
This provides a mechanism to get to the stub section following any
input section. While still allowing the section grouping mechanism to
find the section group stub section associated with an input section
by first following the link_sec pointer.
Marcus Shawcroft [Fri, 20 Mar 2015 19:08:00 +0000 (19:08 +0000)]
Refactor generation of 835769 workaround stubs.
This patch recognizes that we only need to perform one scan for the
835769 errata and that this scan can take place before we insert
branch stubs. The erratum scan code is relocated and adjusted to
create stub entries directly rather than populating an intermediate
representation. Since stub entries are created immediately we can
drop the adhoc stub size adjustment code and allow the generic stub
sizing code to deal with 835769 stub entries.
This patch restructures the code but does not change the workaround
used to deal with erratum 83679, the exact placement of workaround
stubs in the final image may change slightly after this patch due to
stubs being created in a different order.
H.J. Lu [Mon, 5 Jan 2015 12:42:37 +0000 (04:42 -0800)]
Assign file position for .strtab only if needed
bfd/
PR ld/17773
* elflink.c (bfd_elf_final_link): Assign the file position for
the symbol string table only there are symbols to be emitted.
ld/testsuite/
PR ld/17773
* ld-elf/binutils.exp (binutils_test): Add an optional
readelf_options. Replace -l with $readelf_options. Add a
gap test.
* ld/testsuite/ld-elf/gap.s: New file.
Matthew Fortune [Tue, 16 Dec 2014 12:39:22 +0000 (12:39 +0000)]
Rework the alignment check for BFD_RELOC_MIPS_18_PCREL_S3.
gas/
* config/tc-mips.c (md_apply_fix): Apply alignment check
to the symbol and offset rather than *valP for
BFD_RELOC_MIPS_18_PCREL_S3. Also update the error message
for BFD_RELOC_MIPS_19_PCREL_S2.
gas/testsuite/
* gas/mips/r6-64.s: Remove .align directives from LDPC
instructions and add further tests for LDPC.
* gas/mips/r6-64-n32.d: remove the NOPs from LDPC expected
output and update for new tests.
* gas/mips/r6-64-n64.d: Likewise.
* gas/mips/ldpc-unalign.l: New file.
* gas/mips/ldpc-unalign.s: Likewise.
* gas/mips/mips.exp: Run ldpc-unalign test.
Matthew Fortune [Thu, 18 Dec 2014 20:08:38 +0000 (20:08 +0000)]
Fix undefined weak symbol reloc tests
ld/testsuite/
* ld-mips-elf/mips-elf.exp: Update undefweak-overflow tests.
* ld-mips-elf/undefweak-overflow-n32.d: Remove.
* ld-mips-elf/undefweak-overflow-n64.d: Likewise.
* ld-mips-elf/undefweak-overflow.s: Set mips64r6, noreorder and
add a label to mark the micromips region.
* ld-mips-elf/undefweak-overflow.d: Update expected output.
Andrew Bennett [Thu, 20 Nov 2014 15:40:16 +0000 (15:40 +0000)]
[MIPS] When calculating a relocation using an undefined weak symbol don't check for overflow.
In MIPS the relocation calculation only ignores the overflow checks for undefined
weak symbols on relocations associated with j/jal. This patch extends this to
the relocations used by the: b* instructions; pc/gp relative symbol offsets; and the
lwpc/ldpc MIPS r6 instructions.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation): Only check for overflow
on non-weak undefined symbols.
ld/testsuite/
* ld-mips-elf/mips-elf.exp: Add in undefined weak overflow tests for
o32, n32 and n64.
* ld-mips-elf/undefweak-overflow.s: New test.
* ld-mips-elf/undefweak-overflow.d: New test.
* ld-mips-elf/undefweak-overflow-n32.d: New test.
* ld-mips-elf/undefweak-overflow-n64.d: New test.
H.J. Lu [Sun, 14 Dec 2014 07:37:22 +0000 (23:37 -0800)]
Handle weak alias for PIE with copy reloc
When there is a weak symbol with a real definition, the processor
independent code will have arranged for us to see the real definition
first. We need to copy the needs_copy bit from the real definition and
check it when allowing copy reloc in PIE.
bfd/
PR ld/17689
* elf64-x86-64.c (elf_x86_64_link_hash_entry): Add needs_copy.
Change has_bnd_reloc to bit field.
(elf_x86_64_link_hash_newfunc): Initialize needs_copy and
has_bnd_reloc to 0.
(elf_x86_64_check_relocs): Set has_bnd_reloc to 1 instead
of TRUE.
(elf_x86_64_adjust_dynamic_symbol): Copy needs_copy from the
real definition to a weak symbol.
(elf_x86_64_allocate_dynrelocs): Also check needs_copy of a
weak symbol for PIE when discarding space for relocs against
symbols which turn out to need copy relocs.
(elf_x86_64_relocate_section): Also check needs_copy of a
weak symbol for PIE with copy reloc.
projects / thirdparty / binutils-gdb.git / log
