Palmer Dabbelt [Tue, 21 Mar 2017 15:36:44 +0000 (08:36 -0700)]
Sanitize RISC-V GAS help text, documentation
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
* config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64,
-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
print an invalid default ISA string.
* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
Alan Modra [Sun, 26 Mar 2017 21:49:48 +0000 (08:19 +1030)]
PR21303, objdump doesn't show e200z4 insns
PR 21303
opcodes/
* ppc-dis.c (struct ppc_mopt): Comment.
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
gas/
* testsuite/gas/ppc/pr21303.d,
* testsuite/gas/ppc/pr21303.s: New test
* testsuite/gas/ppc/ppc.exp: Run it.
Peter Bergner [Thu, 9 Mar 2017 02:49:03 +0000 (20:49 -0600)]
Update -maltivec and -mvsx options to only enable their oldest instructions.
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec
and vsx instructions respecitively that have ever been added. This is in
constract to GCC's -maltivec and -mvsx options, which only enable the oldest
(ie, first) set of altivec and vsx instructions. This patch changes GAS to
mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a
problem with trying to assemble the lxvx instruction which is different
between POWER8 and POWER9.
opcodes/
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
<vsx>: Do not use PPC_OPCODE_VSX3;
gas/
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
(objdump): Use the -Mpower8 option.
Alan Modra [Tue, 7 Mar 2017 00:34:19 +0000 (11:04 +1030)]
PowerPC64 abort due to dynamic relocs on hidden undefweak
ppc64_elf_relocate_section lacked a check which meant that it emitted
dynamic relocs against a hidden undefweak symbol for which no dynamic
relocs had been allocated.
Alan Modra [Mon, 6 Mar 2017 09:09:34 +0000 (19:39 +1030)]
Don't decode powerpc insns with invalid fields
Certain insns have restrictions on fields. For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields. This holds even when the RA0
field is 0 (meaning a zero rather than r0).
PR 21124
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
(extract_raq, extract_ras, extract_rbx): New functions.
(powerpc_operands): Use opposite corresponding insert function.
(Q_MASK): Define.
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
register restriction.
Alan Modra [Tue, 28 Feb 2017 00:08:51 +0000 (10:38 +1030)]
Nios2 dynobj handling fixes
A number of places in elf32-nios.c created dynamic sections but didn't
set the hash table dynobj. That meant we could have duplicate dynamic
sections connected to a number of bfds, so size_dynamic_sections
didn't properly discard or allocate contents.
Also, the entire set of dynamic sections was created in check_relocs
on seeing GOT relocs, when only .got related sections are needed,
probably done to hide segfaults later in finish_dynamic_sections.
The patch fixes these issues and makes the assembler emit errors when
nios2 lacks the necessary pc-relative relocs for subtraction
expressions, rather than silently generating bad code.
eg. ld-elf/merge. I've also tidied uses of elf32_nios2_hash_table and
elf_hash_table.
bfd/
PR 20995
* elf32-nios2.c (nios2_elf32_relocate_section): Use htab
rather than elf32_nios2_hash_table or elf_hash_table.
(create_got_section): Likewise.
(nios2_elf32_finish_dynamic_symbol): Likewise.
(nios2_elf32_adjust_dynamic_symbol): Likewise.
(nios2_elf32_size_dynamic_sections): Likewise.
(nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot
vars. Use htab equivalents directly instead. Don't create
all dynamic sections on needing just the GOT. Use a goto
rather than a fall-through with reloc test. Ensure
htab->dynobj is set when making dynamic sreloc section.
(nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab
equivalent directly instead. Don't segfault on looking for
.dynamic when dynamic sections have not been created. Don't
segfault on .got.plt being discarded.
(nios2_elf32_size_dynamic_sections): Delete plt and got vars.
Don't set "relocs" on .rela.plt. Do handle .sbss. Delete
fixme and another not so relevant comment.
(nios2_elf_add_symbol_hook): Delete dynobj var. If not
already set, set hash table dynobj on creating .sbss.
gas/
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
ld/
* testsuite/ld-elf/merge.d: xfail for nios.
Alan Modra [Mon, 27 Feb 2017 21:36:02 +0000 (08:06 +1030)]
Don't make dynamic .data.rel.ro SEC_READONLY
I'd made this dynamic section read-only so a flag test distinguished
it from .dynbss, but like any other .data.rel.ro section it really
should be marked read-write. (It is read-only after relocation, not
before.) When using the standard linker scripts this usually doesn't
matter since the output section is among other read-write sections and
not page aligned. However, it might matter in the extraordinary case
of the dynamic section being the only .data.rel.ro section with the
output section just happening to be page aligned and a multiple of a
page in size. In that case the output section would be read-only, and
live it its own read-only PT_LOAD segment, which is incorrect.
Alan Modra [Mon, 27 Feb 2017 22:02:36 +0000 (08:32 +1030)]
PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA. They ought to both be -4. The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
/* Make it pc-relative. If the back-end code has not
selected a pc-relative reloc, cancel the adjustment
we do later on all pc-relative relocs. */
*not* cancelling the pc-relative adjustment. So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust. Having the new internal reloc also makes it easy to
support
addpcis rx,sym@ha
as an equivalent to
addpcis rx,(sym-0f)@ha
0:
The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.
Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.
include/
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
(ppc64_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
ld/
* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
limits of addpcis range.
Andrew Waterman [Wed, 22 Feb 2017 05:56:57 +0000 (21:56 -0800)]
bfd: RISC-V: relax to gp in more cases.
bfd/ChangeLog:
2017-02-24 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (GP_NAME): New macro.
(riscv_global_pointer_value): Use it.
(_bfd_riscv_relax_lui): If symbol and global pointer are in same
output section, consider only that section's alignment.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
The documentation entry for the SVE feature incorrectly said that
it was enabled by default for ARMv8-A or later. This patch fixes
that and also mentions that +sve implies +simd. (It also implies
+fp, but that follows by transitivity.)
[AArch64] Add separate feature flag for weaker release consistent load insns
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
Andreas Krebbel [Mon, 2 Jan 2017 15:40:29 +0000 (16:40 +0100)]
S/390: Add support for new cpu architecture - arch12.
This adds support of new instructions to the S/390 specific parts.
The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.
Note: arch12 is NOT the official name of the new CPU. It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual. The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.
No testsuite regressions.
Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
facility.
* s390-opc.c: Add new operand description macros, new instruction
types, instruction masks, and new .insn instruction types.
* s390-opc.txt: Add new arch12 instructions.
include/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): New value
S390_OPCODE_ARCH12.
(S390_INSTR_FLAG_VX2): New macro definition.
gas/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
* doc/as.texinfo: Document arch12 as cpu type.
* doc/c-s390.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
* testsuite/gas/s390/zarch-arch12.d: New test.
* testsuite/gas/s390/zarch-arch12.s: New test.
* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
output patterns.
Alan Modra [Thu, 23 Feb 2017 01:50:42 +0000 (12:20 +1030)]
Correct VLE 16D and SDAREL relocations
PR 20744
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Correct dst_mask on all VLE
16D relocations.
(ppc_elf_vle_split16): Correct field mask and shift for 16D relocs.
(ppc_elf_relocate_section): Correct calculation for VLE SDAREL
relocs.
ld/
* testsuite/ld-powerpc/vle-reloc-2.s: Use r6 for last insn of
each group.
* testsuite/ld-powerpc/vle-reloc-2.d: Update for above change
and sdarel reloc fix.
Alan Modra [Thu, 16 Feb 2017 11:49:10 +0000 (22:19 +1030)]
ld testsuite function pointer comparisons vs. hppa
ld/testsuite/ld-elf/check-ptr-eq.c fails for hppa, since function
pointers may point at plabels. It isn't valid to cast two function
pointers to void* and then compare the void pointers.
* testsuite/ld-elf/check-ptr-eq.c (check_ptr_eq): Change params
from void pointers to function pointers.
* testsuite/ld-elf/pr18718.c: Update to suit.
* testsuite/ld-elf/pr18720a.c: Update to suit.
Alan Modra [Tue, 14 Feb 2017 00:15:51 +0000 (10:45 +1030)]
hppa -z relro again
I misunderstood the hppa alias problem. File offsets of segments need
to be such that no page is mapped twice with different permissions.
(Which still seems to me like something the kernel could fix, but
anyhow, this is not so difficult to achieve in ld.)
PR 21000
bfd/
* elf-bfd.h (struct elf_backend_data): Add no_page_alias.
* elfxx-target.h (elf_backend_no_page_alias): Define.
(elfNN_bed): Init new field.
* elf.c (assign_file_positions_for_load_sections): If no_page_alias
ensure PT_LOAD segment starts on a new page.
* elf32-hppa.c (elf_backend_no_page_alias): Define.
ld/
* testsuite/ld-elf/loadaddr1.d: Adjust for hppa file offsets.
* testsuite/ld-elf/loadaddr2.d: Likewise.
* testsuite/ld-elf/loadaddr3a.d: Likewise.
* testsuite/ld-scripts/rgn-at5.d: Likewise.
Alan Modra [Thu, 16 Feb 2017 01:53:12 +0000 (12:23 +1030)]
PR21132, hppa-linux pie support doesn't work
This fixes a long-standing hppa bug seen when generating PIEs, and I
think possible to trigger with forced local symbols in shared
libraries. Not allocating enough space for PLT relocs results in ld
writing outside of the buffer.
PR 21132
* elf32-hppa.c (allocate_plt_static): Allocate space for relocs
if pic.
H.J. Lu [Wed, 15 Feb 2017 19:39:30 +0000 (11:39 -0800)]
i386: Allow "lea foo@GOT, %reg" in PIC
"lea foo@GOT, %reg" is OK in PIC since it only loads the GOT offset
into register, which can be used later with a GOT base register to
get the value in the GOT entry.
Palmer Dabbelt [Wed, 8 Feb 2017 19:26:07 +0000 (11:26 -0800)]
Don't use "_gp" on RISC-V, use "_global_pointer$" instead
"_gp" could conflict with ABI-complient code. While it's probably OK
because MIPS uses this name, we figured it'd be good to clean this up
before a release with RISC-V in it.
ld/ChangeLog:
2017-02-13 Palmer Dabbelt <palmer@dabbelt.com>
* emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Change
_gp to __global_pointer$.
bfd/ChangeLog:
2017-02-13 Palmer Dabbelt <palmer@dabbelt.com>
* elfnn-riscv.c (riscv_global_pointer_value): Change _gp to
__global_pointer$.
MIPS/BFD: Respect the ELF gABI dynamic symbol table sort requirement
Ensure all local symbols precede external symbols in the dynamic symbol
table.
No local symbols are expected to make it to the dynamic symbol table
except for section symbols already taken care of, so this is really a
safeguard only against a potential BFD bug otherwise not so harmful,
which may become a grave one due to a symbol table sorting requirement
violation (see PR ld/20828 for an example). This means however that no
test suite coverage is possible for this change as code introduced here
is not normally expected to trigger.
Logically split then the part of the dynamic symbol table which is not
global offset table mapped, into a local area at the beginning and an
external area following. By the time `mips_elf_sort_hash_table' is
called we have the number of local dynamic symbol table entries (section
and non-section) already counted in `local_dynsymcount', so use it to
offset the external area from the beginning.
bfd/
* elfxx-mips.c (mips_elf_hash_sort_data): Add
`max_local_dynindx'.
(mips_elf_sort_hash_table): Handle it.
(mips_elf_sort_hash_table_f) <GGA_NONE>: For forced local
symbols bump up `max_local_dynindx' rather than
`max_non_got_dynindx'.
MIPS/BFD: Use `bfd_size_type' for dynamic symbol table indices
Use the `bfd_size_type' data type for dynamic symbol table indices in
the MIPS backend, in line with generic code and removing the need to use
a cast.
bfd/
* elfxx-mips.c (mips_elf_hash_sort_data): Convert the
`min_got_dynindx', `max_unref_got_dynindx' and
`max_non_got_dynindx' members to the `bfd_size_type' data type.
(mips_elf_sort_hash_table): Adjust accordingly.
MIPS/BFD: Fix assertion in `mips_elf_sort_hash_table'
Move the assertion on non-NULL `htab' in `mips_elf_sort_hash_table' to
the beginning, before the pointer is dereferenced (`mips_elf_hash_table
(info)' and `elf_hash_table (info)' both point to the same memory
location, differently typed).
bfd/
* elfxx-mips.c (mips_elf_sort_hash_table): Move assertion on
non-NULL `htab' to the beginning.
projects / thirdparty / binutils-gdb.git / log
