Jinyang He [Fri, 11 Aug 2023 08:10:40 +0000 (16:10 +0800)]
LoongArch: Enable gas sort relocs
The md_pre_output_hook creating fixup is asynchronous, causing relocs
may be out of order in .eh_frame. Define GAS_SORT_RELOCS so that reorder
relocs when write_relocs.
Nick Alcock [Mon, 29 Jul 2024 11:45:09 +0000 (12:45 +0100)]
libctf: fix ref leak of names of newly-inserted non-root-visible types
A bug in ctf_dtd_delete led to refs in the string table to the
names of non-root-visible types not being removed when the DTD
was. This seems harmless, but actually it would lead to a write
down a pointer into freed memory if such a type was ctf_rollback()ed
over and then the dict was serialized (updating all the refs as the
strtab was serialized in turn).
Bug introduced in commit fe4c2d55634c700ba527ac4183e05c66e9f93c62
("libctf: create: non-root-visible types should not appear in name tables")
which is included in binutils 2.35.
libctf/
* ctf-create.c (ctf_dtd_delete): Remove refs for all types
with names, not just root-visible ones.
Alan Modra [Fri, 4 Aug 2023 05:39:53 +0000 (15:09 +0930)]
PR30697, ppc32 mix of local-dynamic and global-dynamic TLS
This fixes miscounting of dynamic relocations on GOT entries when
a) there are both local-dynamic and global-dynamic tls accesss for a
given symbol, and
b) the symbol is global with non-default visibility, and
c) the __tls_get_addr calls aren't optimised away.
PR 30697
bfd/
* elf32-ppc.c (allocate_dynrelocs): Correct local-dynamic
reloc count.
ld/
* testsuite/ld-powerpc/tls32ldgd.d,
* testsuite/ld-powerpc/tls32ldgd.s: New test.
* testsuite/ld-powerpc/powerpc.exp: Run it.
Alan Modra [Thu, 22 Jun 2023 23:18:38 +0000 (08:48 +0930)]
[GOLD] powerpc DT_RELACOUNT
DT_RELACOUNT was calculated incorrectly, and relative relocs not
sorted as they should be to the start of .rela.dyn, due to adding one
particular class of dynamic reloc using the wrong "add" method.
* powerpc.cc (Target_powerpc::Scan::global): Add relative
dyn relocs for ADDR64 and similar using add_global_relative.
In commit 0961e631575b, the fix for PR30217, make_lplt_section and
make_brlt_section were changed to use rela_dyn_ rather than their own
separate dynamic reloc sections. This fails miserably whenever brlt_
is needed for long branches, due to needing to iterate sizing and thus
reset brlt_ sizes.
PR 30536
PR 30217
* powerpc.cc (Target_powerpc::make_brlt_section): Don't use
rela_dyn_.
H.J. Lu [Wed, 29 Mar 2023 20:06:26 +0000 (13:06 -0700)]
lto: Don't add indirect symbols for versioned aliases in IR
Linker adds indirect symbols for versioned symbol aliases, which are
created by ".symver foo, foo@FOO", by checking symbol type, value and
section so that references to foo will be replaced by references to
foo@FOO if foo and foo@FOO have the same symbol type, value and section.
But in IR, since all symbols of the same type have the same value and
section, we can't tell if a symbol is an alias of another symbol by
their types, values and sections. We shouldn't add indirect symbols
for versioned symbol aliases in IR.
bfd/
PR ld/30281
* elflink.c (elf_link_add_object_symbols): Don't add indirect
symbols for ".symver foo, foo@FOO" aliases in IR.
gas: arm: Change warning message to not reference specific A-class architecture revision
We noticed that a warning message about the use of scalar fp16
instructions being UNPREDICTABLE when conditionalized in an IT
block referenced the specific A-class architecture revision
ARMv8.2-A.
Many of these instructions are now also part of ARMv8.1-M, so
the warning message had become misleading. Here we just change
the message to not specify an architecture revision at all and
update all testing accordingly. This was done with a simple
find-n-replace within the binutils sources. No tests have
regressed for the arm target.
gas: arm: Fix a further IT-predicated vcvt issue in the presense of MVE vcvtn
Previously we had experienced issues with assembling a "VCVTNE" instruction
in the presence of the MVE architecture extension, because it could be
interpreted both as:
* The base instruction VCVT + NE for IT predication when inside an IT block.
* The MVE instruction VCVTN + E in the Else of a VPT block.
Given a C reproducer of:
```
int test_function(float value)
{
int ret_val = 10;
if (value != 0.0)
{
ret_val = (int) value;
}
return ret_val;
}
```
GCC generates a VCVTNE instruction based on the `truncsisf2_vfp`
pattern, which will look like:
`vcvtne.s32.f32 s-reg, s-reg`
This still triggers an error due to being misidentified as "vcvtn+e"
Similar errors were found with other type combinations and instruction
patterns (these have all been added to the testing of this patch).
This class of errors was previously worked around by:
https://sourceware.org/pipermail/binutils/2020-August/112728.html
which addressed this by looking at the operand types, however,
that isn't adequate to cover all the extra cases that have been
found. Instead, we add some special-casing logic earlier when
the instructions are parsed that is conditional on whether we are
in a VPT block or not, when the instruction is parsed.
gas/ChangeLog:
* config/tc-arm.c (opcode_lookup): Add special vcvtn handling.
* testsuite/gas/arm/mve-vcvtne-it-bad.l: Add further testing.
* testsuite/gas/arm/mve-vcvtne-it-bad.s: Likewise.
* testsuite/gas/arm/mve-vcvtne-it.d: Likewise.
* testsuite/gas/arm/mve-vcvtne-it.s: Likewise.
projects / thirdparty / binutils-gdb.git / log
