Martin Liska [Wed, 27 Dec 2017 09:30:14 +0000 (10:30 +0100)]
Assign result of get_string_lenth to a SSA_NAME (PR tree-optimization/83552).
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
* tree-ssa-strlen.c (fold_strstr_to_strncmp): Assign result
of get_string_lenth to a SSA_NAME if not a GIMPLE value.
2017-12-27 Martin Liska <mliska@suse.cz>
PR tree-optimization/83552
* gcc.dg/pr83552.c: New test.
Jakub Jelinek [Sat, 23 Dec 2017 08:40:19 +0000 (09:40 +0100)]
re PR c++/83553 (compiler removes body of the for-loop, although there is a case label inside)
PR c++/83553
* fold-const.c (struct contains_label_data): New type.
(contains_label_1): Return non-NULL even for CASE_LABEL_EXPR, unless
inside of a SWITCH_BODY seen during the walk.
(contains_label_p): Use walk_tree instead of
walk_tree_without_duplicates, prepare data for contains_label_1 and
provide own pset.
Jakub Jelinek [Fri, 22 Dec 2017 18:04:18 +0000 (19:04 +0100)]
re PR debug/83550 (Bad location of DW_TAG_structure_type with forward declaration since r224161)
PR debug/83550
* c-decl.c (finish_struct): Set DECL_SOURCE_LOCATION on
TYPE_STUB_DECL and call rest_of_type_compilation before processing
incomplete vars rather than after it.
Jakub Jelinek [Fri, 22 Dec 2017 18:01:58 +0000 (19:01 +0100)]
re PR debug/83547 ((statement-frontiers) error: void value not ignored as it ought to be)
PR debug/83547
* tree-iterator.c (alloc_stmt_list): Start with cleared
TREE_SIDE_EFFECTS regardless whether a new STATEMENT_LIST is allocated
or old one reused.
c/
* c-typeck.c (c_finish_stmt_expr): Ignore !TREE_SIDE_EFFECTS as
indicator of ({ }), instead skip all trailing DEBUG_BEGIN_STMTs first,
and consider empty ones if there are no other stmts. For
-Wunused-value walk all statements before the one only followed by
DEBUG_BEGIN_STMTs.
testsuite/
* gcc.c-torture/compile/pr83547.c: New test.
Ian Lance Taylor [Fri, 22 Dec 2017 16:43:28 +0000 (16:43 +0000)]
compiler: do not propagate address-taken of a slice element to the slice
Array_index_expression may be used for indexing/slicing array or
slice. If a slice element is address taken, the slice itself is
not necessarily address taken. Only propagate address-taken for
arrays.
Ian Lance Taylor [Fri, 22 Dec 2017 15:55:10 +0000 (15:55 +0000)]
compiler: bring escape analysis mostly in line with gc compiler
This CL ports the latest (~Go 1.10) escape analysis code from
the gc compiler. Changes include:
- In the gc compiler, the variable expression is represented
with the variable node itself (ONAME). It is the same node
used in the AST for multiple var expressions for the same
variable. In our case, the var expressions nodes are distinct
nodes. We need to propagate the escape state from/to the
underlying variable in getter and setter. We already do it in
the setter. Do it in the getter as well.
- At the point of escape analysis, some AST constructs have not
been lowered to runtime calls, for example, map literal
construction and some builtin calls. Change the analysis to
work on the non-lowered AST constructs instead of call
expressions for them. For this to work, the analysis needs to
look into Builtin_call_expression. Move its class definition
from expressions.cc to expressions.h, and add necessary
accessors. Also fix bugs in other runtime call handlings
(selectsend, ifaceX2Y2, etc.).
- Handle closures properly. The analysis tracks the function
reference expression, and the escape state is propagated to
the underlying heap expression for get_backend to do stack
allocation for non-escaping closures.
- Fix add_dereference. Before, this was doing expr->deref(),
which undoes an indirection instead of add one. In the gc
compiler, it adds a level of indirection, which is modeled as
an OIND node regardless of the type of the expression. We
can't do this for non-pointer typed expression, otherwise it
will result in a type error. Instead, we model it with a
special flavor of Node, "indirect". The flood phase handles
this by incrementing its level.
- Slicing of an array was not handled correctly. The gc compiler
has an implicit (compiler inserted) OADDR node for the array,
so the analysis is actually performed on the address of the
array. We don't have this implicit address-of expression in
the AST. Instead, we model this by adding an implicit child to
the Node of the Array_index_expression representing slicing of
an array.
- Array_index_expression may represent indexing or slicing. The
code distinguishes them by looking at whether the type of the
expression is a slice. This does not work if the slice element
is a slice. Instead, check whether its end() is NULL.
- Temporary references was handled only in a limited case, as
part of address-of expression. This CL handles it in general.
The analysis uses the Temporary_statement as the point of
tracking, and forwards Temporary_reference_expression to the
underlying statement when needed.
- Handle call return value flows, escpecially multiple return
values. This includes porting part of CL 8202, CL 20102, and
other fixes.
- Support go:noescape pragma.
- Add special handling for self assignment like
b.buf = b.buf[m:n]. (CL 3162)
- Remove ESCAPE_SCOPE, which was treated essentially the same as
ESCAPE_HEAP, and was removed from the gc compiler. (CL 32130)
- Run flood phase until fix point. (CL 30693)
- Unnamed parameters do not escape. (CL 38600)
- Various small bug fixes and improvements.
"make check-go" passes except the one test in math/big, when the
escape analysis is on. The escape analysis is still not run by
default.
Igor Tsimbalist [Fri, 22 Dec 2017 11:41:02 +0000 (12:41 +0100)]
This is a follow up patch for pr83488 to fix an error in setting...
This is a follow up patch for pr83488 to fix an error in setting
OPTION_MASK_ISA_AVX512VNNI_SET and OPTION_MASK_ISA_AVX512F_SET bits.
There were both set in ix86_isa_flags2 while being defined in
different ISA sets. Additionally move OPTION_MASK_ISA_AVX512VNNI_SET
to ix86_isa_flags as it can be used with OPTION_MASK_ISA_AVX512VL_SET.
gcc/
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VNNI_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VNNI_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_AVX512VNNI_*SET being in ix86_isa_flags.
* config/i386/i386-builtin.def: Move VNNI builtins from ARGS2
section to ARGS.
* config/i386/i386-c.c: Check for OPTION_MASK_ISA_AVX512VNNI in
isa_flag instead of isa_flag2.
* config/i386/i386.c (ix86_target_string): Move -mavx512vnni from
isa_opts2 to isa_opts.
* config/i386/i386.opt (mavx512vnni): Move from ix86_isa_flags2
to ix86_isa_flags.
Ian Lance Taylor [Fri, 22 Dec 2017 03:27:00 +0000 (03:27 +0000)]
compiler: improve escape analysis diagnostics
This CL brings escape analysis diagnostics closer to the gc
compiler's. This makes porting and debugging escape analysis
code easier. A few changes:
- In the gc compiler, the variable expression is represented
with the variable node itself (ONAME), the location of which
is the location of definition. We add a definition_location
method to Node, and make use of it when the gc compiler emits
diagnostics at the definition locations.
- In the gc compiler, methods are named T.M or (*T).M. Add the
type to the method name when possible.
- Print "moved to heap" messages only for variables.
- Reduce some duplicated diagnostics.
- Print "does not escape" messages in more situations which the
gc compiler does.
- Remove the special handling for closure numbers. In gofrontend,
closures are named "$nested#" where # is a global counter
starting from 0, whereas in the gc compiler they are named
"outer.func#" where # is a per-function counter starting from
1. We tried to adjust the closure name to better matching the
ones in the gc compiler, however, it cannot match exactly
because of the difference of the counter. Instead, just print
"outer.$nested#".
Alexandre Oliva [Fri, 22 Dec 2017 02:07:31 +0000 (02:07 +0000)]
[SFN] sync up debug-only stmt list's side effects with empty stmts too
for gcc/c-family/ChangeLog
PR debug/83527
PR debug/83419
* c-semantics.c (only_debug_stmts_after_p): New.
(pop_stmt_list): Clear side effects in debug-only stmt list.
Check for single nondebug stmt followed by debug stmts only.
Jakub Jelinek [Thu, 21 Dec 2017 23:10:45 +0000 (00:10 +0100)]
re PR middle-end/83487 (ICE in expand_call, at calls.c:4098)
PR middle-end/83487
* config/i386/i386.c (ix86_function_arg_boundary): Return
PARM_BOUNDARY for TYPE_EMPTY_P types.
* gcc.c-torture/compile/pr83487.c: New test.
* gcc.dg/compat/pr83487-1.h: New file.
* gcc.dg/compat/pr83487-1_main.c: New test.
* gcc.dg/compat/pr83487-1_x.c: New file.
* gcc.dg/compat/pr83487-1_y.c: New file.
* gcc.dg/compat/pr83487-2_main.c: New test.
* gcc.dg/compat/pr83487-2_x.c: New file.
* gcc.dg/compat/pr83487-2_y.c: New file.
* g++.dg/abi/pr83487.C: New test.
* g++.dg/compat/abi/pr83487-1_main.C: New test.
* g++.dg/compat/abi/pr83487-1_x.C: New file.
* g++.dg/compat/abi/pr83487-1_y.C: New file.
* g++.dg/compat/abi/pr83487-2_main.C: New test.
* g++.dg/compat/abi/pr83487-2_x.C: New file.
* g++.dg/compat/abi/pr83487-2_y.C: New file.
Jakub Jelinek [Thu, 21 Dec 2017 19:28:10 +0000 (20:28 +0100)]
re PR rtl-optimization/80747 (gcc.dg/tree-ssa/tailrecursion-4.c fails with ICE when compiled with options "-fprofile-use -freorder-blocks-and-partition")
PR rtl-optimization/80747
PR rtl-optimization/83512
* cfgrtl.c (force_nonfallthru_and_redirect): When splitting
succ edge from ENTRY, copy partition from e->dest to the newly
created bb.
* bb-reorder.c (reorder_basic_blocks_simple): If last_tail is
ENTRY, use BB_PARTITION of its successor block as current_partition.
Don't copy partition when splitting succ edge from ENTRY.
* gcc.dg/pr80747.c: New test.
* gcc.dg/pr83512.c: New test.
Jakub Jelinek [Thu, 21 Dec 2017 19:26:34 +0000 (20:26 +0100)]
re PR tree-optimization/83521 (ICE: verify_gimple failed (error: invalid operand in unary operation))
PR tree-optimization/83521
* tree-ssa-phiopt.c (factor_out_conditional_conversion): Use
gimple_build_assign without code on result of
fold_build1 (VIEW_CONVERT_EXPR, ...), as it might not create
a VIEW_CONVERT_EXPR.
Alexandre Oliva [Thu, 21 Dec 2017 18:14:21 +0000 (18:14 +0000)]
[-fcompare-debug] retain insn locations when turning dbr seq into return
A number of -fcompare-debug errors on sparc arise as we split a dbr
SEQUENCE back into separate insns to turn the branch into a return.
If we just take the location from the PREV_INSN, it might be a debug
insn without INSN_LOCATION, or an insn with an unrelated location.
But that's silly: each of the SEQUENCEd insns is still an insn with
its own INSN_LOCATION, so use that instead, even though some may have
been adjusted while constructing the SEQUENCE.
for gcc/ChangeLog
* reorg.c (make_return_insns): Reemit each insn with its own
location.
Alexandre Oliva [Thu, 21 Dec 2017 18:14:06 +0000 (18:14 +0000)]
[SFN] propagate single-nondebug-stmt's side effects to enclosing list
Statements without side effects, preceded by debug begin stmt markers,
would become a statement list with side effects, although the stmt on
its own would be extracted from the list and remain not having side
effects. This causes debug info and possibly codegen differences.
This patch fixes it, identifying the situation in which the stmt would
have been extracted from the stmt list, and propagating the side
effects flag from the stmt to the list.
for gcc/ChangeLog
PR debug/83419
* c-family/c-semantics.c (pop_stmt_list): Propagate side
effects from single nondebug stmt to container list.
James Greenhalgh [Thu, 21 Dec 2017 16:39:43 +0000 (16:39 +0000)]
[patch AArch64] Do not perform a vector splat for vector initialisation if it is not useful
Our current vector initialisation code will first duplicate
the first element to both lanes, then overwrite the top lane with a new
value.
This duplication can be clunky and wasteful.
Better would be to simply use the fact that we will always be overwriting
the remaining bits, and simply move the first element to the corrcet place
(implicitly zeroing all other bits).
We also need a new pattern in simplify-rtx.c:simplify_ternary_operation ,
to ensure we can still simplify:
(vec_concat:OUTER x:INNER y:INNER) or (vec_concat y x)
---
gcc/
* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code
generation for cases where splatting a value is not useful.
* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
across a vec_duplicate and a paradoxical subreg forming a vector
mode to a vec_concat.
Kyrylo Tkachov [Thu, 21 Dec 2017 15:02:49 +0000 (15:02 +0000)]
[arm] Specify +dotprod support for Cortex-A55 and Cortex-A75 in native system detection
Since support for -mcpu=cortex-a55 and -mcpu=cortex-a75
was added we added support for the +dotprod extension
which these CPUs support.
We already specify as such in the arm-cpus.in entries for
these processors. However the table in driver-arm.c was
not adding +dotproct to the -march string that it generates.
This patch fixes that oversight.
In the future I'd like to get the arm_cpu_table in driver-arm.c
be auto-generated somehow from the arm-cpus.in data so
that we don't have to keep track of discrepancies explicitly...
Bootstrapped and tested on arm-none-linux-gnueabihf.
* config/arm/driver-arm.c (arm_cpu_table): Specify dotprod
support for Cortex-A55 and Cortex-A75.
Jakub Jelinek [Thu, 21 Dec 2017 08:45:30 +0000 (09:45 +0100)]
re PR target/83488 (ICE on a CET test-case)
PR target/83488
* config/i386/i386.c (ix86_target_string): Move -mavx512vbmi2 and
-mshstk entries from isa_opts2 to isa_opts and -mhle, -mmovbe,
-mclzero and -mmwaitx entries from isa_opts to isa_opts2.
(ix86_option_override_internal): Adjust for
OPTION_MASK_ISA_{HLE,MOVBE,CLZERO,MWAITX} moving to ix86_isa_flags2
and OPTION_MASK_ISA_SHSTK moving to ix86_isa_flags.
(BDESC_VERIFYS): Remove SPECIAL_ARGS2 related checks.
(ix86_init_mmx_sse_builtins): Remove bdesc_special_args2 handling.
Use def_builtin2 instead of def_builtin for OPTION_MASK_ISA_MWAITX
and OPTION_MASK_ISA_CLZERO builtins. Use def_builtin instead of
def_builtin2 for CET builtins.
(ix86_expand_builtin): Remove bdesc_special_args2 handling. Fix
up formatting in IX86_BUILTIN_RDPID code.
* config/i386/i386-builtin.def: Move VBMI2 builtins from SPECIAL_ARGS2
section to SPECIAL_ARGS and from ARGS2 section to ARGS.
* config/i386/i386.opt (mavx512vbmi2, mshstk): Move from
ix86_isa_flags2 to ix86_isa_flags.
(mhle, mmovbe, mclzero, mmwaitx): Move from ix86_isa_flags to
ix86_isa_flags2.
* config/i386/i386-c.c (ix86_target_macros_internal): Check for
OPTION_MASK_ISA_{CLZERO,MWAITX} in isa_flag2 instead of isa_flag.
Check for OPTION_MASK_ISA_{SHSTK,AVX512VBMI2} in isa_flag instead
of isa_flag2.
* common/config/i386/i386-common.c (OPTION_MASK_ISA_AVX512VBMI2_SET):
Or in OPTION_MASK_ISA_AVX512F_SET.
(OPTION_MASK_ISA_AVX512F_UNSET): Or in
OPTION_MASK_ISA_AVX512VBMI2_UNSET.
(ix86_handle_option): Adjust for
OPTION_MASK_ISA_{SHSTK,AVX512VBMI2}_*SET being in ix86_isa_flags
and OPTION_MASK_ISA_{MOVBE,MWAITX,CLZERO}_*SET in ix86_isa_flags2.
This patch makes prune_runtime_alias_test_list take the iteration
factor as a poly_int and tracks polynomial offsets internally
as well.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-data-ref.h (prune_runtime_alias_test_list): Take the
factor as a poly_uint64 rather than an unsigned HOST_WIDE_INT.
* tree-data-ref.c (prune_runtime_alias_test_list): Likewise.
Track polynomial offsets.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255936
This patch makes vect_compute_data_ref_alignment treat DR_INIT as a
poly_int and handles cases in which the calculated misalignment might
not be constant.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vect-data-refs.c (vect_compute_data_ref_alignment):
Treat drb->init as a poly_int. Fail if its misalignment wrt
vector_alignment isn't known.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255935
This patch splits the loop versioning threshold out from the
cost model threshold so that the former can become a poly_uint64.
We still use a single test to enforce both limits where possible.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vectorizer.h (_loop_vec_info): Add a versioning_threshold
field.
(LOOP_VINFO_VERSIONING_THRESHOLD): New macro
(vect_loop_versioning): Take the loop versioning threshold as a
separate parameter.
* tree-vect-loop-manip.c (vect_loop_versioning): Likewise.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Initialize
versioning_threshold.
(vect_analyze_loop_2): Compute the loop versioning threshold
whenever loop versioning is needed, and store it in the new
field rather than combining it with the cost model threshold.
(vect_transform_loop): Update call to vect_loop_versioning.
Try to combine the loop versioning and cost thresholds here.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255934
This patch makes ivopts handle polynomial address offsets
when recording potential IV uses.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssa-loop-ivopts.h (strip_offset): Return the offset as
poly_uint64_pod rather than an unsigned HOST_WIDE_INT.
* tree-loop-distribution.c (classify_builtin_st): Update accordingly.
* tree-ssa-loop-ivopts.c (iv_use::addr_offset): Change from
an unsigned HOST_WIDE_INT to a poly_uint64_pod.
(group_compare_offset): Update accordingly.
(split_small_address_groups_p): Likewise.
(record_use): Take addr_offset as a poly_uint64 rather than
an unsigned HOST_WIDE_INT.
(strip_offset): Return the offset as a poly_uint64 rather than
an unsigned HOST_WIDE_INT.
(record_group_use, split_address_groups): Track polynomial offsets.
(add_iv_candidate_for_use): Likewise.
(addr_offset_valid_p): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(strip_offset_1): Return the offset as a poly_int64 rather than
a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255933
This patch changes the offset parameter to get_binfo_at_offset
from HOST_WIDE_INT to poly_int64. This function probably doesn't
need to handle polynomial offsets in practice, but it's easy
to do and avoids forcing the caller to check first.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (get_binfo_at_offset): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* tree.c (get_binfo_at_offset): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255932
This patch allows MEM_REF offsets to be polynomial, with mem_ref_offset
now returning a poly_offset_int instead of an offset_int. The
non-mechanical changes to callers of mem_ref_offset were handled by
previous patches.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
This patch handles polynomial offsets in find_bswap_or_nop_load,
which could be useful for constant-sized data at a variable offset.
It is needed for a later patch to compile.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* gimple-ssa-stor-merging.c (find_bswap_or_nop_load): Track polynomial
offsets for MEM_REFs.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255929
This patch makes adjust_ptr_info_misalignment take the adjustment
as a poly_uint64 rather than an unsigned int.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssanames.h (adjust_ptr_info_misalignment): Take the increment
as a poly_uint64 rather than an unsigned int.
* tree-ssanames.c (adjust_ptr_info_misalignment): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255928
verify_expr ensured that the size and offset in gimple BIT_FIELD_REFs
satisfied tree_fits_uhwi_p. This patch extends that so that they can
be poly_uint64s, and adds helper routines for accessing them when the
verify_expr requirements apply.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (bit_field_size, bit_field_offset): New functions.
* hsa-gen.c (gen_hsa_addr): Use them.
* tree-ssa-forwprop.c (simplify_bitfield_ref): Likewise.
(simplify_vector_constructor): Likewise.
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Likewise.
* tree-cfg.c (verify_expr): Require the sizes and offsets of a
BIT_FIELD_REF to be poly_uint64s rather than uhwis.
* fold-const.c (fold_ternary_loc): Protect tree_to_uhwi with
tree_fits_uhwi_p.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255926
This patch changes the sizes passed to emit_group_load and
emit_group_store from int to poly_int64.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.h (emit_group_load, emit_group_load_into_temps)
(emit_group_store): Take the size as a poly_int64 rather than an int.
* expr.c (emit_group_load_1, emit_group_load): Likewise.
(emit_group_load_into_temp, emit_group_store): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255925
all of which are part of the IRA/reload interface.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* ira-int.h (ira_spilled_reg_stack_slot::width): Change from
an unsigned int to a poly_uint64.
* ira.h (ira_reuse_stack_slot, ira_mark_new_stack_slot): Take the
sizes as poly_uint64s rather than unsigned ints.
* ira-color.c (ira_reuse_stack_slot, ira_mark_new_stack_slot):
Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255924
This patch changes the type of stack_var::size from HOST_WIDE_INT
to poly_uint64. The difference in signedness is because the
field was set by:
v->size = tree_to_uhwi (size);
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* cfgexpand.c (stack_var::size): Change from a HOST_WIDE_INT
to a poly_uint64.
(add_stack_var, stack_var_cmp, partition_stack_vars)
(dump_stack_var_partition): Update accordingly.
(alloc_stack_frame_space): Take the size as a poly_int64 rather
than a HOST_WIDE_INT.
(expand_stack_vars, expand_one_stack_var_1): Handle polynomial sizes.
(defer_stack_allocation, estimated_stack_frame_size): Likewise.
(account_stack_vars, expand_one_var): Likewise. Return a poly_uint64
rather than a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255922
It also changes TARGET_RETURN_POPS_ARGS so that the size of the
arguments passed in and the size returned by the hook are both
poly_int64s.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* target.def (return_pops_args): Treat both the input and output
sizes as poly_int64s rather than HOST_WIDE_INTS.
* targhooks.h (default_return_pops_args): Update accordingly.
* targhooks.c (default_return_pops_args): Likewise.
* doc/tm.texi: Regenerate.
* emit-rtl.h (incoming_args): Change pops_args, size and
outgoing_args_size from int to poly_int64_pod.
* function.h (expr_status): Change x_pending_stack_adjust and
x_stack_pointer_delta from int to poly_int64.
(args_size::constant): Change from HOST_WIDE_INT to poly_int64.
(ARGS_SIZE_RTX): Update accordingly.
* calls.c (highest_outgoing_arg_in_use): Change from int to
unsigned int.
(stack_usage_watermark, stored_args_watermark): New variables.
(stack_region_maybe_used_p, mark_stack_region_used): New functions.
(emit_call_1): Change the stack_size and rounded_stack_size
parameters from HOST_WIDE_INT to poly_int64. Track n_popped
as a poly_int64.
(save_fixed_argument_area): Check stack_usage_watermark.
(initialize_argument_information): Change old_pending_adj from
a HOST_WIDE_INT * to a poly_int64_pod *.
(compute_argument_block_size): Return the size as a poly_int64
rather than an int.
(finalize_must_preallocate): Track polynomial argument sizes.
(compute_argument_addresses): Likewise.
(internal_arg_pointer_based_exp): Track polynomial offsets.
(mem_overlaps_already_clobbered_arg_p): Rename to...
(mem_might_overlap_already_clobbered_arg_p): ...this and take the
size as a poly_uint64 rather than an unsigned HOST_WIDE_INT.
Check stored_args_used_watermark.
(load_register_parameters): Update accordingly.
(check_sibcall_argument_overlap_1): Likewise.
(combine_pending_stack_adjustment_and_call): Take the unadjusted
args size as a poly_int64 rather than an int. Return a bool
indicating whether the optimization was possible and return
the new adjustment by reference.
(check_sibcall_argument_overlap): Track polynomail argument sizes.
Update stored_args_watermark.
(can_implement_as_sibling_call_p): Handle polynomial argument sizes.
(expand_call): Likewise. Maintain stack_usage_watermark and
stored_args_watermark. Update calls to
combine_pending_stack_adjustment_and_call.
(emit_library_call_value_1): Handle polynomial argument sizes.
Call stack_region_maybe_used_p and mark_stack_region_used.
Maintain stack_usage_watermark.
(store_one_arg): Likewise. Update call to
mem_overlaps_already_clobbered_arg_p.
* config/arm/arm.c (arm_output_function_prologue): Add a cast to
HOST_WIDE_INT.
* config/avr/avr.c (avr_outgoing_args_size): Likewise.
* config/microblaze/microblaze.c (microblaze_function_prologue):
Likewise.
* config/cr16/cr16.c (cr16_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
(cr16_compute_frame, cr16_initial_elimination_offset): Add casts
to HOST_WIDE_INT.
* config/ft32/ft32.c (ft32_compute_frame): Likewise.
* config/i386/i386.c (ix86_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
(ix86_expand_split_stack_prologue): Add a cast to HOST_WIDE_INT.
* config/moxie/moxie.c (moxie_compute_frame): Likewise.
* config/m68k/m68k.c (m68k_return_pops_args): Update for new
TARGET_RETURN_POPS_ARGS interface.
* config/vax/vax.c (vax_return_pops_args): Likewise.
* config/pa/pa.h (STACK_POINTER_OFFSET): Add a cast to poly_int64.
(EXIT_IGNORE_STACK): Update reference to crtl->outgoing_args_size.
* config/arm/arm.h (CALLER_INTERWORKING_SLOT_SIZE): Likewise.
* config/powerpcspe/aix.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/powerpcspe/darwin.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/powerpcspe/powerpcspe.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/aix.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/darwin.h (STACK_DYNAMIC_OFFSET): Likewise.
* config/rs6000/rs6000.h (STACK_DYNAMIC_OFFSET): Likewise.
* dojump.h (saved_pending_stack_adjust): Change x_pending_stack_adjust
and x_stack_pointer_delta from int to poly_int64.
* dojump.c (do_pending_stack_adjust): Update accordingly.
* explow.c (allocate_dynamic_stack_space): Handle polynomial
stack_pointer_deltas.
* function.c (STACK_DYNAMIC_OFFSET): Add a cast to poly_int64.
(pad_to_arg_alignment): Track polynomial offsets.
(assign_parm_find_stack_rtl): Likewise.
(assign_parms, locate_and_pad_parm): Handle polynomial argument sizes.
* toplev.c (output_stack_usage): Update reference to
current_function_pushed_stack_size.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255921
This patch makes the instantiate virtual regs pass track offsets
as poly_ints.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* function.c (in_arg_offset, var_offset, dynamic_offset)
(out_arg_offset, cfa_offset): Change from int to poly_int64.
(instantiate_new_reg): Return the new offset as a poly_int64_pod
rather than a HOST_WIDE_INT.
(instantiate_virtual_regs_in_rtx): Track polynomial offsets.
(instantiate_virtual_regs_in_insn): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255920
This patch adds new utility functions for manipulating REG_ARGS_SIZE
notes and allows the notes to carry polynomial as well as constant sizes.
The code was inconsistent about whether INT_MIN or HOST_WIDE_INT_MIN
should be used to represent an unknown size. The patch uses
HOST_WIDE_INT_MIN throughout.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* rtl.h (get_args_size, add_args_size_note): New functions.
(find_args_size_adjust): Return a poly_int64 rather than a
HOST_WIDE_INT.
(fixup_args_size_notes): Likewise. Make the same change to the
end_args_size parameter.
* rtlanal.c (get_args_size, add_args_size_note): New functions.
* builtins.c (expand_builtin_trap): Use add_args_size_note.
* calls.c (emit_call_1): Likewise.
* explow.c (adjust_stack_1): Likewise.
* cfgcleanup.c (old_insns_match_p): Update use of
find_args_size_adjust.
* combine.c (distribute_notes): Track polynomial arg sizes.
* dwarf2cfi.c (dw_trace_info): Change beg_true_args_size,
end_true_args_size, beg_delay_args_size and end_delay_args_size
from HOST_WIDE_INT to poly_int64.
(add_cfi_args_size): Take the args_size as a poly_int64 rather
than a HOST_WIDE_INT.
(notice_args_size, notice_eh_throw, maybe_record_trace_start)
(maybe_record_trace_start_abnormal, scan_trace, connect_traces): Track
polynomial arg sizes.
* emit-rtl.c (try_split): Use get_args_size.
* recog.c (peep2_attempt): Likewise.
* reload1.c (reload_as_needed): Likewise.
* expr.c (find_args_size_adjust): Return the adjustment as a
poly_int64 rather than a HOST_WIDE_INT.
(fixup_args_size_notes): Change end_args_size from a HOST_WIDE_INT
to a poly_int64 and change the return type in the same way.
(emit_single_push_insn): Track polynomial arg sizes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255919
This patch converts the frame allocation code (mostly in function.c)
to use poly_int64 rather than HOST_WIDE_INT for frame offsets and
sizes.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* function.h (frame_space): Change start and length from HOST_WIDE_INT
to poly_int64.
(get_frame_size): Return the size as a poly_int64 rather than a
HOST_WIDE_INT.
(frame_offset_overflow): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
(assign_stack_temp): Likewise for the size.
* function.c (get_frame_size): Return a poly_int64 rather than
a HOST_WIDE_INT.
(frame_offset_overflow): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(try_fit_stack_local): Take the start, length and size as poly_int64s
rather than HOST_WIDE_INTs. Return the offset as a poly_int64_pod
rather than a HOST_WIDE_INT.
(add_frame_space): Take the start and end as poly_int64s rather than
HOST_WIDE_INTs.
(assign_stack_local_1, assign_stack_local, assign_stack_temp_for_type)
(assign_stack_temp): Likewise for the size.
(temp_slot): Change size, base_offset and full_size from HOST_WIDE_INT
to poly_int64.
(find_temp_slot_from_address): Handle polynomial offsets.
(combine_temp_slots): Likewise.
* emit-rtl.h (rtl_data::x_frame_offset): Change from HOST_WIDE_INT
to poly_int64.
* cfgexpand.c (alloc_stack_frame_space): Return the offset as a
poly_int64 rather than a HOST_WIDE_INT.
(expand_one_stack_var_at): Take the offset as a poly_int64 rather
than a HOST_WIDE_INT.
(expand_stack_vars, expand_one_stack_var_1, expand_used_vars): Handle
polynomial frame offsets.
* config/m32r/m32r-protos.h (m32r_compute_frame_size): Take the size
as a poly_int64 rather than an int.
* config/m32r/m32r.c (m32r_compute_frame_size): Likewise.
* config/v850/v850-protos.h (compute_frame_size): Likewise.
* config/v850/v850.c (compute_frame_size): Likewise.
* config/xtensa/xtensa-protos.h (compute_frame_size): Likewise.
* config/xtensa/xtensa.c (compute_frame_size): Likewise.
* config/pa/pa-protos.h (pa_compute_frame_size): Likewise.
* config/pa/pa.c (pa_compute_frame_size): Likewise.
* explow.h (get_dynamic_stack_base): Take the offset as a poly_int64
rather than a HOST_WIDE_INT.
* explow.c (get_dynamic_stack_base): Likewise.
* final.c (final_start_function): Use the constant lower bound
of the frame size for -Wframe-larger-than.
* ira.c (do_reload): Adjust for new get_frame_size return type.
* lra.c (lra): Likewise.
* reload1.c (reload): Likewise.
* config/avr/avr.c (avr_asm_function_end_prologue): Likewise.
* config/pa/pa.h (EXIT_IGNORE_STACK): Likewise.
* rtlanal.c (get_initial_register_offset): Return the offset as
a poly_int64 rather than a HOST_WIDE_INT.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255917
This patch makes a few small poly_int64 changes to reload1.c,
mostly related to eliminations. Again, there's no real expectation
that reload will be used for targets that have polynomial-sized modes,
but it seemed easier to convert it anyway.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* reload1.c (elim_table): Change initial_offset, offset and
previous_offset from HOST_WIDE_INT to poly_int64_pod.
(offsets_at): Change the target array's element type from
HOST_WIDE_INT to poly_int64_pod.
(set_label_offsets, eliminate_regs_1, eliminate_regs_in_insn)
(elimination_costs_in_insn, update_eliminable_offsets)
(verify_initial_elim_offsets, set_offsets_for_label)
(init_eliminable_invariants): Update after above changes.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255916
This patch makes a few small poly_int64 changes to reload.c,
such as in the "decomposition" structure. In practice, any
port with polynomial-sized modes should be using LRA rather
than reload, but it's easier to convert reload anyway than
to sprinkle to_constants everywhere.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* reload.h (reload::inc): Change from an int to a poly_int64_pod.
* reload.c (combine_reloads, debug_reload_to_stream): Likewise.
(decomposition): Change start and end from HOST_WIDE_INT
to poly_int64_pod.
(decompose, immune_p): Update accordingly.
(find_inc_amount): Return a poly_int64 rather than an int.
* reload1.c (inc_for_reload): Take the inc_amount as a poly_int64
rather than an int.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255915
This patch makes get_inner_reference and ptr_difference_const return the
bit size and bit position as poly_int64s rather than HOST_WIDE_INTS.
The non-mechanical changes were handled by previous patches.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (get_inner_reference): Return the bitsize and bitpos
as poly_int64_pods rather than HOST_WIDE_INT.
* fold-const.h (ptr_difference_const): Return the pointer difference
as a poly_int64_pod rather than a HOST_WIDE_INT.
* expr.c (get_inner_reference): Return the bitsize and bitpos
as poly_int64_pods rather than HOST_WIDE_INT.
(expand_expr_addr_expr_1, expand_expr_real_1): Track polynomial
offsets and sizes.
* fold-const.c (make_bit_field_ref): Take the bitpos as a poly_int64
rather than a HOST_WIDE_INT. Update call to get_inner_reference.
(optimize_bit_field_compare): Update call to get_inner_reference.
(decode_field_reference): Likewise.
(fold_unary_loc): Track polynomial offsets and sizes.
(split_address_to_core_and_offset): Return the bitpos as a
poly_int64_pod rather than a HOST_WIDE_INT.
(ptr_difference_const): Likewise for the pointer difference.
* asan.c (instrument_derefs): Track polynomial offsets and sizes.
* config/mips/mips.c (r10k_safe_mem_expr_p): Likewise.
* dbxout.c (dbxout_expand_expr): Likewise.
* dwarf2out.c (loc_list_for_address_of_addr_expr_of_indirect_ref)
(loc_list_from_tree_1, fortran_common): Likewise.
* gimple-laddress.c (pass_laddress::execute): Likewise.
* gimple-ssa-store-merging.c (find_bswap_or_nop_load): Likewise.
* gimplify.c (gimplify_scan_omp_clauses): Likewise.
* simplify-rtx.c (delegitimize_mem_from_attrs): Likewise.
* tree-affine.c (tree_to_aff_combination): Likewise.
(get_inner_reference_aff): Likewise.
* tree-data-ref.c (split_constant_offset_1): Likewise.
(dr_analyze_innermost): Likewise.
* tree-scalar-evolution.c (interpret_rhs_expr): Likewise.
* tree-sra.c (ipa_sra_check_caller): Likewise.
* tree-vect-data-refs.c (vect_check_gather_scatter): Likewise.
* ubsan.c (maybe_instrument_pointer_overflow): Likewise.
(instrument_bool_enum_load, instrument_object_size): Likewise.
* gimple-ssa-strength-reduction.c (slsr_process_ref): Update call
to get_inner_reference.
* hsa-gen.c (gen_hsa_addr): Likewise.
* sanopt.c (maybe_optimize_ubsan_ptr_ifn): Likewise.
* tsan.c (instrument_expr): Likewise.
* match.pd: Update call to ptr_difference_const.
This patch makes get_bit_range return the range and position as poly_ints.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expr.h (get_bit_range): Return the bitstart and bitend as
poly_uint64s rather than unsigned HOST_WIDE_INTs. Return the bitpos
as a poly_int64 rather than a HOST_WIDE_INT.
* expr.c (get_bit_range): Likewise.
(expand_assignment): Update call accordingly.
* fold-const.c (optimize_bit_field_compare): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255912
Previously aarch64_classify_address used an rtx code to distinguish
LDP/STP addresses from normal addresses; the code was PARALLEL
to select LDP/STP and anything else to select normal addresses.
This patch replaces that parameter with a dedicated enum.
The SVE port will add another enum value that didn't map naturally
to an rtx code.
2017-12-21 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_addr_query_type): New enum.
(aarch64_legitimate_address_p): Use it instead of an rtx code,
as an optional final parameter.
* config/aarch64/aarch64.c (aarch64_classify_address): Likewise.
(aarch64_legitimate_address_p): Likewise.
(aarch64_print_address_internal): Take an aarch64_addr_query_type
instead of an rtx code.
(aarch64_address_valid_for_prefetch_p): Update calls accordingly.
(aarch64_legitimate_address_hook_p): Likewise.
(aarch64_print_ldpstp_address): Likewise.
(aarch64_print_operand_address): Likewise.
(aarch64_address_cost): Likewise.
* config/aarch64/constraints.md (Uml, Umq, Ump, Utq): Likewise.
* config/aarch64/predicates.md (aarch64_mem_pair_operand): Likewise.
(aarch64_mem_pair_lanes_operand): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255911
Jakub Jelinek [Wed, 20 Dec 2017 19:41:38 +0000 (20:41 +0100)]
re PR ipa/83506 (ICE: Segmentation fault in force_nonfallthru_and_redirect)
PR ipa/83506
* ipa-fnsummary.c (pass_data_ipa_free_fn_summary): Use 0 for
todo_flags_finish.
(pass_ipa_free_fn_summary): Add small_p private data member,
initialize to false in the ctor.
(pass_ipa_free_fn_summary::clone,
pass_ipa_free_fn_summary::set_pass_param,
pass_ipa_free_fn_summary::gate): New methods.
(pass_ipa_free_fn_summary::execute): Return TODO_remove_functions
| TODO_dump_symtab if small_p.
* passes.def: Add true parm for the existing pass_ipa_free_fn_summary
entry and add another instance of the pass with false parm after
ipa-pure-const.
* ipa-pure-const.c (pass_ipa_pure_const): Don't call
ipa_free_fn_summary here.
* gcc.dg/pr83506.c: New test.
* gcc.dg/ipa/ctor-empty-1.c: Use -fdump-ipa-free-fnsummary1 instead
of -fdump-ipa-free-fnsummary and scan in free-fnsummary1 instead of
free-fnsummary dump.
Alexandre Oliva [Wed, 20 Dec 2017 14:48:34 +0000 (14:48 +0000)]
[SFN] debug markers before labels no more
Make sure that gimple and RTL IRs don't have debug markers before
labels. When we build the CFG, we move labels before any markers
appearing before them. Then, make sure we don't mistakenly
reintroduce them.
This reverts some of the complexity that had been brought about by the
initial SFN patches.
This patch makes pass_store_merging track polynomial sizes
and offsets. store_immediate_info remains restricted to stores
with a constant offset and size.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* poly-int-types.h (round_down_to_byte_boundary): New macro.
(round_up_to_byte_boundary): Likewise.
* expr.h (get_bit_range): Add temporary shim.
* gimple-ssa-store-merging.c (store_operand_info): Change the
bitsize, bitpos, bitregion_start and bitregion_end fields from
unsigned HOST_WIDE_INT to poly_uint64.
(merged_store_group): Likewise load_align_base.
(compatible_load_p, compatible_load_p): Update accordingly.
(imm_store_chain_info::coalesce_immediate_stores): Likewise.
(split_group, imm_store_chain_info::output_merged_store): Likewise.
(mem_valid_for_store_merging): Return the bitsize, bitpos,
bitregion_start and bitregion_end as poly_uint64s rather than
unsigned HOST_WIDE_INTs. Track polynomial offsets internally.
(handled_load): Take the bitsize, bitpos,
bitregion_start and bitregion_end as poly_uint64s rather than
unsigned HOST_WIDE_INTs.
(pass_store_merging::process_store): Update call to
mem_valid_for_store_merging.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255894
This patch makes get_object_alignment_2 track polynomial offsets
and sizes. The real work is done by get_inner_reference, but we
then need to handle the alignment correctly.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* builtins.c (get_object_alignment_2): Track polynomial offsets
and sizes. Update the alignment handling.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255893
This patch makes expand_debug_expr track polynomial memory offsets.
It simplifies the handling of the case in which the reference is not
to the first byte of the base, which seemed non-trivial enough to
make it worth splitting out as a separate patch.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree.h (get_inner_reference): Add a version that returns the
offset and size as poly_int64_pods rather than HOST_WIDE_INTs.
* cfgexpand.c (expand_debug_expr): Track polynomial offsets. Simply
the case in which bitpos is not associated with the first byte.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255892
This patch changes the bitpos argument to pointer_may_wrap_p from
HOST_WIDE_INT to poly_int64. A later patch makes the callers track
polynomial offsets.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* fold-const.c (pointer_may_wrap_p): Take the offset as a
HOST_WIDE_INT rather than a poly_int64.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255890
This patch changes symbol_number::bytepos from a HOST_WIDE_INT
to a poly_int64. perform_symbolic_merge can cope with symbolic
offsets as long as the difference between the two offsets is
constant. (This could happen for a constant-sized field that
occurs at a variable offset, for example.)
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* gimple-ssa-store-merging.c (symbolic_number::bytepos): Change from
HOST_WIDE_INT to poly_int64_pod.
(perform_symbolic_merge): Update accordingly.
(bswap_replace): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255889
This patch changes the type of aff_tree::offset from widest_int to
poly_widest_int and adjusts the function interfaces in the same way.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-affine.h (aff_tree::offset): Change from widest_int
to poly_widest_int.
(wide_int_ext_for_comb): Delete.
(aff_combination_const, aff_comb_cannot_overlap_p): Take the
constants as poly_widest_int rather than widest_int.
(aff_combination_constant_multiple_p): Return the multiplier
as a poly_widest_int.
(aff_combination_zero_p, aff_combination_singleton_var_p): Handle
polynomial offsets.
* tree-affine.c (wide_int_ext_for_comb): Make original widest_int
version static and add an overload for poly_widest_int.
(aff_combination_const, aff_combination_add_cst)
(wide_int_constant_multiple_p, aff_comb_cannot_overlap_p): Take
the constants as poly_widest_int rather than widest_int.
(tree_to_aff_combination): Generalize INTEGER_CST case to
poly_int_tree_p.
(aff_combination_to_tree): Track offsets as poly_widest_ints.
(aff_combination_add_product, aff_combination_mult): Handle
polynomial offsets.
(aff_combination_constant_multiple_p): Return the multiplier
as a poly_widest_int.
* tree-predcom.c (determine_offset): Return the offset as a
poly_widest_int.
(split_data_refs_to_components, suitable_component_p): Update
accordingly.
(valid_initializer_p): Update call to
aff_combination_constant_multiple_p.
* tree-ssa-address.c (addr_to_parts): Handle polynomial offsets.
* tree-ssa-loop-ivopts.c (get_address_cost_ainc): Take the step
as a poly_int64 rather than a HOST_WIDE_INT.
(get_address_cost): Handle polynomial offsets.
(iv_elimination_compare_lt): Likewise.
(rewrite_use_nonlinear_expr): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255888
projects / thirdparty / gcc.git / log
