Wayne Lin [Fri, 10 Jan 2025 13:08:20 +0000 (21:08 +0800)]
drm/amd/display: Add DCN36 DMCUB
DMCU-B (Display Micro-Controller Unit B) is a display microcontroller
used for shared display functionality with BIOS and for advanced
power saving display features.
Add case to support DCN3.6 as well.
V2: adjust copyright license text
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:41:03 +0000 (20:41 +0800)]
drm/amd/display: Add DCN36 DML2 support
Enable DML2 for DCN36.
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:37:14 +0000 (20:37 +0800)]
drm/amd/display: Add DCN36 GPIO
Add DCN36 support in GPIO.
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:32:48 +0000 (20:32 +0800)]
drm/amd/display: Add DCN36 Resource
Add resource handling for DCN36.
V2: adjust copyright license text
V3: remove unnecessary headers
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:27:27 +0000 (20:27 +0800)]
drm/amd/display: Add DCN36 IRQ
Add IRQ services for DCN36.
This allows us to create/init and manage irqs for DCN3
V2: adjust copyright license text
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:55:42 +0000 (20:55 +0800)]
drm/amd/display: Add DCN36 BIOS command table support
Add case for DCN36 in command_table_helper2.c.
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Fri, 10 Jan 2025 12:24:08 +0000 (20:24 +0800)]
drm/amd/display: Add DCN36 version identifiers
Add DCN3.6 asic identifiers.
Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 31 Jan 2025 02:25:12 +0000 (21:25 -0500)]
drm/amdgpu/gfx9: use amdgpu_gfx_off_ctrl_immediate() for PG
Use amdgpu_gfx_off_ctrl_immediate() when powergating.
There's no need for the delay in gfx off allow. The
powergating is dynamically disabled/enabled as for
RV/PCO on compute queues and allowing gfx off again as
soon the job is submitted improves power savings.
Lijo Lazar [Tue, 4 Feb 2025 06:32:41 +0000 (12:02 +0530)]
drm/amd/pm: Remove unnecessary device state checks
For amdgpu_get_pp_force_state, amdgpu_get_pp_cur_state already takes
care of device state check. In other cases, values are returned from
driver cached variables and are not dependent on device state.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <feifei.xu@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 4 Feb 2025 06:23:26 +0000 (11:53 +0530)]
drm/amd/pm: Fix get_if_active usage
If a device supports runtime pm, then pm_runtime_get_if_active returns 0
if a device is not active and 1 if already active. However, if a device
doesn't support runtime pm, the API returns -EINVAL. A device not
supporting runtime pm implies it's not affected by runtime pm and it's
active. Hence no need to get() to increment usage count. Remove < 0
return value check. Also, ignore runpm state to determine active status.
If the device is already in suspend state, disallow access.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <feifei.xu@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 4 Feb 2025 05:44:21 +0000 (11:14 +0530)]
drm/amd/pm: Add APIs for device access checks
Wrap the checks before device access in helper functions and use them
for device access. The generic order of APIs now is to do input argument
validation first and check if device access is allowed.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Feifei Xu <feifei.xu@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Mon, 3 Feb 2025 18:02:03 +0000 (11:02 -0700)]
drm/amd/display: Replace pr_info in dc_validate_boot_timing()
Use DC_LOG_DEBUG instead of pr_info to match other uses in dc.c.
Fixes: 091e301c2b41 ("drm/amd/display: Add debug messages for dc_validate_boot_timing()") Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
link_enc_cfg_get_link_enc_used_by_stream() is no longer used after
2021's:
commit 6366b00346c0 ("drm/amd/display: Maintain consistent mode of
operation during encoder assignment")
which introduces and uses the _current version instead.
Remove it.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
get_max_support_fbc_buffersize() is unused since 2021's
commit 94f0d0c80cf3 ("drm/amd/display/dc/dce110/dce110_compressor: Remove
unused function 'dce110_get_required_compressed_surfacesize")
removed it's only caller.
Remove it.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
get_clock_requirements_for_state() was added in 2018 by
commit 8ab2180f96f5 ("drm/amd/display: Add function to fetch clock
requirements")
but never used.
Remove it.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
mod_freesync_get_vmin_vmax() and mod_freesync_get_v_position() were
added in 2017 by
commit 72ada5f76939 ("drm/amd/display: FreeSync Auto Sweep Support")
mod_freesync_is_valid_range() was added in 2018 by
commit e80e94460841 ("drm/amd/display: add method to check for supported
range")
mod_freesync_get_settings() was added in 2018 by
commit a3e1737ed61c ("drm/amd/display: Implement stats logging")
and
mod_freesync_calc_field_rate_from_timing() was added in 2020 by
commit 49c70ece54b0 ("drm/amd/display: Change input parameter for
set_drr")
None of these have been used.
Remove them.
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Fri, 31 Jan 2025 12:46:12 +0000 (18:16 +0530)]
drm/amd/pm: Limit to 8 jpeg rings per instance
JPEG 5.0.1 supports upto 10 rings, however PMFW support for SMU v13.0.6
variants is now limited to 8 per instance. Limit to 8 temporarily to
avoid out of bounds access.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Thu, 30 Jan 2025 07:05:42 +0000 (12:35 +0530)]
drm/amdgpu: Enable devcoredump for JPEG5_0_0
Add register list and enable devcoredump for JPEG5_0_0
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 06:43:17 +0000 (12:13 +0530)]
drm/amdgpu: Enable devcoredump for JPEG2_5_0
Add register list and enable devcoredump for JPEG2_5_0
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 06:38:48 +0000 (12:08 +0530)]
drm/amdgpu: Enable devcoredump for JPEG2_0_0
Add register list and enable devcoredump for JPEG2_0_0
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 06:31:18 +0000 (12:01 +0530)]
drm/amdgpu: Enable devcoredump for JPEG3_0_0
Add register list and enable devcoredump for JPEG3_0_0
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 05:22:35 +0000 (10:52 +0530)]
drm/amdgpu: Enable devcoredump for JPEG4_0_5
Add register list and enable devcoredump for JPEG4_0_5
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 05:16:15 +0000 (10:46 +0530)]
drm/amdgpu: Enable devcoredump for JPEG4_0_0
Add register list and enable devcoredump for JPEG4_0_0
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Wed, 29 Jan 2025 05:01:32 +0000 (10:31 +0530)]
drm/amdgpu: Enable devcoredump for JPEG5_0_1
Add register list and enable devcoredump for JPEG5_0_1
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Tue, 28 Jan 2025 19:23:52 +0000 (00:53 +0530)]
drm/amdgpu: Enable devcoredump for JPEG4_0_3
Add register list and enable devcoredump for JPEG4_0_3
V2: (Lijo)
- remove version specific callbacks and use simplified helper functions
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini() and avoid the call here
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Tue, 28 Jan 2025 18:27:03 +0000 (23:57 +0530)]
drm/amdgpu: Add helper funcs for jpeg devcoredump
Add devcoredump helper functions that can be reused for all jpeg versions.
V2: (Lijo)
- add amdgpu_jpeg_reg_dump_init() and amdgpu_jpeg_reg_dump_fini()
- use reg_list and reg_count from init() to dump and print registers
- memory allocation and freeing is moved to the init() and fini()
V3: (Lijo)
- move amdgpu_jpeg_reg_dump_fini() to sw_fini()
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Mon, 27 Jan 2025 06:31:18 +0000 (01:31 -0500)]
drm/amd/display: 3.2.319
- Move SPL to a new path
- Request HW cursor on DCN3.2 with SubVP
- Allow reuse of of DCN4x code
- Enable odm 4:1 when debug key is set
- Fix seamless boot sequence
- Support multiple options during psr entry.
- Revert "Exit idle optimizations before attempt to access PHY"
- Fix out-of-bound accesses
- Fixes for mcache programming in DML21
Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Thu, 23 Jan 2025 19:36:57 +0000 (14:36 -0500)]
drm/amd/display: Move SPL to a new path
[WHY & HOW]
- Move SPL from dc/spl to dc/sspl
- Update build files and header paths
- Remove dc/spl files
Reviewed-by: George Zhang <george.zhang@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Thu, 23 Jan 2025 21:39:52 +0000 (16:39 -0500)]
drm/amd/display: Request HW cursor on DCN3.2 with SubVP
[WHY]
When SubVP is active the HW cursor size is limited to 64x64, and
anything larger will force composition which is bad for gaming on
DCN3.2 if the game uses a larger cursor.
[HOW]
If HW cursor is requested, typically by a fullscreen game, do not
enable SubVP so that up to 256x256 cursor sizes are available for
DCN3.2.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Aric Cyr <Aric.Cyr@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro [Fri, 25 Oct 2024 14:31:18 +0000 (10:31 -0400)]
drm/amd/display: Allow reuse of of DCN4x code
Remove the static qualifier to make it available for code sharing
with other components.
Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Muhammad Ahmed [Tue, 21 Jan 2025 21:24:04 +0000 (16:24 -0500)]
drm/amd/display: Enable odm 4:1 when debug key is set
[WHAT]
odm 4to1 is enabled when debug key is set.
Reviewed-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Muhammad Ahmed <muhammad.ahmed@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sathishkumar S [Thu, 16 Jan 2025 19:25:04 +0000 (00:55 +0530)]
drm/amdgpu: Add a func for core specific reg offset
Add an inline function to calculate core specific register offsets for
JPEG v4.0.3 and reuse it, makes code more readable and easier to align.
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Tsai [Mon, 20 Jan 2025 03:21:46 +0000 (11:21 +0800)]
drm/amd/display: Support multiple options during psr entry.
[WHY]
Some panels may not handle idle pattern properly during PSR entry.
[HOW]
Add a condition to allow multiple options on power down
sequence during PSR1 entry.
Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Martin Tsai <Martin.Tsai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reason to revert: screen flashes or gray screen appeared half of the
screen after resume from S4/S5.
Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Fri, 17 Jan 2025 22:49:41 +0000 (17:49 -0500)]
drm/amd/display: Fixes for mcache programming in DML21
[WHY & HOW]
- Fix indexing phantom planes for mcache programming in the wrapper
- Fix phantom mcache allocations to align with HW guidance
- Fix mcache assignment for chroma plane for multi-planar formats
Reviewed-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 28 Jan 2025 06:09:13 +0000 (11:39 +0530)]
drm/amdgpu: Use version to figure out harvest info
IP tables with version <=2 may use harvest bit. For version 3 and above,
harvest bit is not applicable, instead uses harvest table. Fix the
logic accordingly.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx10: Enable cleaner shader for GFX10.1.1/10.1.2 GPUs
Enable the cleaner shader for GFX10.1.1/10.1.2 GPUs to provide data
isolation between GPU workloads. The cleaner shader is responsible for
clearing the Local Data Store (LDS), Vector General Purpose Registers
(VGPRs), and Scalar General Purpose Registers (SGPRs), which helps
prevent data leakage and ensures accurate computation results.
This update extends cleaner shader support to GFX10.1.1/10.1.2 GPUs,
previously available for GFX10.1.10. It enhances security by clearing
GPU memory between processes and maintains a consistent GPU state across
KGD and KFD workloads.
Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 20 Jan 2025 19:30:59 +0000 (14:30 -0500)]
drm/amdgpu: update and cleanup PM4 headers
Consolidate PM4 definitions. Most of these were previously
only defined in UMDs. Add them here as well and sync with
latest packets. Also no need to include soc15d.h on gfx10+.
Aric Cyr [Mon, 20 Jan 2025 02:45:59 +0000 (21:45 -0500)]
drm/amd/display: 3.2.318
This version brings along the following fixes:
- Fixes on psr_version, dcn35 register address, DCPG OP control sequences
- Imporvements to CR AUX RD interval interpretation, dio link encoder
- Disable PSR-SU on some OLED panels
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peichen Huang [Mon, 23 Dec 2024 03:09:52 +0000 (11:09 +0800)]
drm/amd/display: refactor dio link encoder assigning
[WHY]
We would like to have new dio encoder assigning flow.
Which should be aligned with hpo assigning and have
simple logic and data representation.
[HOW}
1. A new config option to enable/disable the new code.
2. Encoder-link mapping is in res_ctx and assigned encoder.
is accessed through pipe_ctx.
3. assign dio encoder when add stream to ctx
Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hansen Dsouza [Wed, 15 Jan 2025 19:21:24 +0000 (14:21 -0500)]
drm/amd/display: Add boot option to reduce PHY SSC for HBR3
[Why]
Spread on DPREFCLK by 0.3 percent can have a negative effect on sink
when PHY SSC is also spread by 0.3 percent
[How]
Add boot option for DMU to lower PHY SSC
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Chung [Fri, 10 Jan 2025 08:09:45 +0000 (16:09 +0800)]
drm/amd/display: Disable PSR-SU on some OLED panel
[Why]
PSR-SU may cause some glitching randomly on some OLED panel.
[How]
Disable the PSR-SU for certain PSR-SU OLED panel.
Reviewed-by: Sun peng Li <sunpeng.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Austin Zheng [Mon, 13 Jan 2025 19:13:51 +0000 (14:13 -0500)]
drm/amd/display: Account For OTO Prefetch Bandwidth When Calculating Urgent Bandwidth
[Why]
1) The current calculations for OTO prefetch bandwidth do not consider the number of DPP pipes in use.
As a result, OTO prefetch bandwidth may be larger than the vactive bandwidth if multiple DPP pipes are used.
OTO prefetch bandwidth should never exceed the vactive bandwidth.
2) Mode programming may be mismatched with mode support
In cases where mode support has chosen to use the equalized (equ) prefetch schedule,
mode programming may end up using oto prefetch schedule instead.
The bandwidth required to do the oto schedule may end up being higher than the equ schedule.
This can cause the required urgent bandwidth to exceed the available urgent bandwidth.
[How]
Output the oto prefetch bandwidth and incorperate it into the urgent bandwidth calculations
even if the prefetch schedule being used is not the oto schedule.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhikai Zhai [Thu, 9 Jan 2025 08:11:48 +0000 (16:11 +0800)]
drm/amd/display: Update Cursor request mode to the beginning prefetch always
[Why]
The double buffer cursor registers is updated by the cursor
vupdate event. There is a gap between vupdate and cursor data
fetch if cursor fetch data reletive to cursor position.
Cursor corruption will happen if we update the cursor surface
in this gap.
[How]
Modify the cursor request mode to the beginning prefetch always
and avoid wraparound calculation issues.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Fri, 10 Jan 2025 16:35:46 +0000 (11:35 -0500)]
drm/amd/display: Update CR AUX RD interval interpretation
[Why]
DP spec updated to have the CR AUX RD interval match the EQ AUX RD
interval interpretation of DPCD 0000Eh/0220Eh for 8b/10b non-LTTPR mode
and LTTPR transparent mode cases.
[How]
Update interpretation of DPCD 0000Eh/0220Eh for CR AUX RD interval
during 8b/10b link training.
Reviewed-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Chung [Mon, 13 Jan 2025 06:22:31 +0000 (14:22 +0800)]
drm/amd/display: Initial psr_version with correct setting
[Why & How]
The initial setting for psr_version is not correct while
create a virtual link.
The default psr_version should be DC_PSR_VERSION_UNSUPPORTED.
Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx10: Add cleaner shader for GFX10.1.10
This commit adds the cleaner shader microcode for GFX10.1.0 GPUs. The
cleaner shader is a piece of GPU code that is used to clear or
initialize certain GPU resources, such as Local Data Share (LDS), Vector
General Purpose Registers (VGPRs), and Scalar General Purpose Registers
(SGPRs).
Clearing these resources is important for ensuring data isolation
between different workloads running on the GPU. Without the cleaner
shader, residual data from a previous workload could potentially be
accessed by a subsequent workload, leading to data leaks and incorrect
computation results.
The cleaner shader microcode is represented as an array of 32-bit words
(`gfx_10_1_0_cleaner_shader_hex`). This array is the binary
representation of the cleaner shader code, which is written in a
low-level GPU instruction set.
When the cleaner shader feature is enabled, the AMDGPU driver loads this
array into a specific location in the GPU memory. The GPU then reads
this memory location to fetch and execute the cleaner shader
instructions.
The cleaner shader is executed automatically by the GPU at the end of
each workload, before the next workload starts. This ensures that all
GPU resources are in a clean state before the start of each workload.
This addition is part of the cleaner shader feature implementation. The
cleaner shader feature helps resource utilization by cleaning up GPU
resources after they are used. It also enhances security and reliability
by preventing data leaks between workloads.
Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Skvortsov [Tue, 21 Jan 2025 03:00:22 +0000 (22:00 -0500)]
drm/amdgpu: Skip err_count sysfs creation on VF unsupported RAS blocks
VFs are not able to query error counts for all RAS blocks. Rather than
returning error for queries on these blocks, skip sysfs the creation
all together.
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Mark amdgpu.gttsize parameter as deprecated and show warnings on use
When not set `gttsize` module parameter by default will get the
value to use for the GTT pool from the TTM page limit, which is
set by a separate module parameter.
This inevitably leads to people not sure which one to set when they
want more addressable memory for the GPU, and you'll end up seeing
instructions online saying to set both.
Add some messages to try to guide people both who are using or misusing
the parameters and mark the parameter as deprecated with the plan to
drop it after the next LTS kernel release.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Decrease message about seamless boot enabled to debug
The message in amdgpu_dm about seamless boot is about an ASIC version
check and module parameter check. It doesn't actually mean that seamless
boot will work.
Push this message into debug to avoid being disingenuous about it working
until it's been tested.
drm/amd/display: Add debug messages for dc_validate_boot_timing()
dc_validate_boot_timing() runs through an exhaustive list of checks to
determine whether a boot stream can be marked as seamless. When the
checks fail, a user will be left guessing what the reason was
Add debug statements that will be helpful to validate the specific
reason.
Jiang Liu [Mon, 13 Jan 2025 03:40:12 +0000 (11:40 +0800)]
amdgpu/soc15: enable asic reset for dGPU in case of suspend abort
When GPU suspend is aborted, do the same for dGPU as APU to reset
soc15 asic. Otherwise it may cause following errors:
[ 547.229463] amdgpu 0001:81:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_0.2.1.0 test failed (-110)
Aric Cyr [Mon, 13 Jan 2025 01:44:53 +0000 (20:44 -0500)]
drm/amd/display: 3.2.317
This version brings along following fixes:
- Reverse the visual confirm recouts
- Exclude clkoffset and ips setting for dcn351 specific
- Fix cursor programming problems
- Increase block_sequence array size
- Use Nominal vBlank to determine vstartup if Provided
- Fix clock frequencies incorrect problems for dcn401
- Add SDP programming for UHBR link as well
- Support "Broadcast RGB" drm property
Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peterson Guo [Thu, 5 Dec 2024 23:51:25 +0000 (18:51 -0500)]
drm/amd/display: Reverse the visual confirm recouts
[WHY]
When checking if a pipe can disable cursor to prevent duplicate cursors,
having visual confirm on will prevent disabling cursors on planes which
cover the bottom of the screen.
[HOW]
When checking if a plane can disable visual confirm, the pipe first
reverses these calculations before doing the checks.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Peterson Guo <peterson.guo@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 10 Jan 2025 15:45:03 +0000 (10:45 -0500)]
drm/amd/display: Exclude clkoffset and ips setting for dcn351 specific
Exclude clock offset and IPS setting for dcn351 specific only.
Reviewed-by: Syed Hassan <syed.hassan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
It's possible to generate more than 50 steps in hwss_build_fast_sequence,
for example with a 6-pipe asic where all pipes are in one MPC chain. This
overflows the block_sequence buffer and corrupts block_sequence_steps,
causing a crash.
[How]
Expand block_sequence to 100 items. A naive upper bound on the possible
number of steps for a 6-pipe asic, ignoring the potential for steps to be
mutually exclusive, is 91 with current code, therefore 100 is sufficient.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Austin Zheng [Tue, 7 Jan 2025 22:49:36 +0000 (17:49 -0500)]
drm/amd/display: Use Nominal vBlank If Provided Instead Of Capping It
[Why/How]
vBlank used to determine the max vStartup is based on the smallest between
the vblank provided by the timing and vblank in ip_caps.
Extra vblank time is not considered if the vblank provided by the timing ends
up being higher than what's defined by the ip_caps
Use 1 less than the vblank size in case the timing is interlaced
so vstartup will always be less than vblank_nom.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Wed, 8 Jan 2025 20:25:41 +0000 (15:25 -0500)]
drm/amd/display: Populate register address for dentist for dcn401
[WHY&HOW]
Address was not previously populated which can result in incorrect
clock frequencies being read on boot.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Tue, 8 Oct 2024 05:08:23 +0000 (13:08 +0800)]
drm/amd/display: Add AS SDP programming for UHBR link rate.
Add SDP programming for UHB link as well.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Tue, 7 Jan 2025 16:00:11 +0000 (11:00 -0500)]
drm/amd/display: log destination of vertical interrupt
[Why]
Knowing the destination of OTG's vertical interrupt 2 is useful for
debugging, but it is not currently included in the OTG state readback
logic
[How]
Read the OTG interrupt destination register to get the vertical interrupt
2 destination on ASICs that have this register when reading back the OTG
state from hardware
Reviewed-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yan Li [Tue, 7 Jan 2025 14:28:16 +0000 (09:28 -0500)]
drm/amd/display: Support "Broadcast RGB" drm property
[WHY]
The source device outputs a full RGB signal, but TV may
be set to use limited RGB. The mismatch in color
range leads to a degradation in image quality.
Display driver should have the ability to switch
between the full and limited RGB to match TV's settings.
[HOW]
Add support of the linux DRM "Broadcast RGB" property, which
indicates the Quantization Range (Full vs Limited) used.
User space can set this property to be "Automatic", "Full"
or "Limited 16:235" to adjust the output color range.
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Yan Li <yan.li@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon/ci_dpm: Remove needless NULL checks of dpm tables
This patch removes useless NULL pointer checks in functions like
ci_set_private_data_variables_based_on_pptable() and
ci_setup_default_dpm_tables().
The pointers in question are initialized as addresses to existing
structures such as rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk by
utilizing & operator and therefore are not in danger of being NULL.
Fix this by removing extra checks thus cleaning the code a tiny bit.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
Fixes: cc8dbbb4f62a ("drm/radeon: add dpm support for CI dGPUs (v2)") Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Wed, 1 Jan 2025 08:53:31 +0000 (14:23 +0530)]
drm/amdgpu: Use active umc info from discovery
There could be configs where some UMC instances are harvested. This
information is obtained through discovery data and populated in
umc.active_mask. Avoid reassigning this as AID mask, instead use the
mask directly while iterating through umc instances. This is to avoid
accesses to harvested UMC instances.
Amber Lin [Mon, 6 Jan 2025 15:56:29 +0000 (10:56 -0500)]
drm/amdgpu: Set noretry default for GC 9.5.0
Set GC 9.5.0 noretry default as 1 for better performance. It can be
changed by the administrator using amdgpu.noretry=0 or by the user using
HSA_XNACK=1 environment variable.
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviwanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / thirdparty / linux.git / log
