Michal Simek [Wed, 14 Mar 2018 10:02:24 +0000 (11:02 +0100)]
tools: xilinx: Fix zynq/zynqmp image recognition
There is an issue to recognize zynq or zynqmp image because header
checking is just the same. That's why zynqmp images are recognized as
zynq one.
Check unused fields which are initialized to zero in zynq format
(__reserved1 0x38 and __reserved2 0x44) which are initialized for
zynqmp. This should ensure that images are properly recognized by:
./tools/mkimage -l spl/boot.bin
Also show image type as ZynqMP instead of Zynq which is confusing.
Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 15 Mar 2018 10:14:19 +0000 (11:14 +0100)]
kwbimage: Fix out of bounds access
The kwbimage format is reading beyond its header structure if it
misdetects a Xilinx Zynq image and tries to read it. Fix it by
sanity checking that the header we want to read fits inside our
file size.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Luca Ceresoli [Mon, 12 Mar 2018 16:18:38 +0000 (17:18 +0100)]
arm64: zynqmp: Enable booting to ATF
U-Boot is now able to boot to ARM Trusted Firmware (ATF). The boot
flow is SPL(EL3) loads ATF and full u-boot and jump to ATF(EL3) which
pass control to full u-boot(EL2). This has been tested on zcu106, so
enable it in this defconfig.
To generate an image that triggers this booting flow, you need to pass
'-O arm-trusted-firmware' to mkimage.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Luca Ceresoli [Mon, 12 Mar 2018 16:18:37 +0000 (17:18 +0100)]
arm64: zynqmp: zcu106: fix SPL MMC booting
The U-Boot SPL generated with the current zcu106 defconfig cannot boot
from MMC:
[...]
U-Boot SPL 2018.01 (Feb 21 2018 - 17:47:14)
EL Level: EL3
Trying to boot from MMC1
sdhci_transfer_data: Error detected in status(0x408020)!
spl_load_image_fat_os: error reading image u-boot.bin, err - -2
spl_load_image_fat: error reading image u-boot.img, err - -6
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Fix by lowering the rpll value. The new value for the RPLL_CTRL
register comes from the current psu_init_gpl.c from the HDF file at
https://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp
(generated by Vivado v2017.4).
RPLL and sdio1_ref clocks before and after this change:
- Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz
- New values: RPLL 1.16 GHz, sdio1_ref 233 MHz
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Mar 2018 15:02:21 +0000 (16:02 +0100)]
scsi: Add per-device private data for scsi uclass
This patch is doing what was done by
"dm: ahci: Correct uclass private data"
(sha1: bfc1c6b4838501d10aa48c0e92eaf70976f4b2dd)
with reverting pointer to allocated space.
It is questionable if sata_ceva should use UCLASS_SCSI or move to
UCLASS_SATA but this investigation hasn't been done yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Sat, 10 Mar 2018 12:22:23 +0000 (17:52 +0530)]
arm64: zynqmp: nand: Fixed NAND write issue
In commit 67faecc3059b ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Mon, 5 Mar 2018 09:54:59 +0000 (15:24 +0530)]
arm64: zynqmp: nand: Fixed NAND erase issue for size 1GiB or more
NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds pytest for zynqaes commands. It tests
loading encrypted image back to DDR and tests loading
encrypted bitstream to PL using "zynqaes load" command.
This test needs to be executed only in bootmode, if not it
wil be skipped.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynq: Poll for PCFG_DONE if encrypted image is bitstream
This patch polls for PCFG_DONE if encrypted image is bitstream
to ensure that bitstream programming is successful. This also
invokes missing zynq_slcr_devcfg_enable() to bring up axi interface
after programming is done.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynq: aes: Use flush_dcache_range() instead of cache on/off
Use flush_dcache_range() instead of dcache disable and
enable as its more meaningful to flush a region than
disabling cache and enabling it back. This fixes the
issue of GEM failure after using zynq aes.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: zynq: aes: Make source and destination bytes to words
Convert source and destination bytes into words length as
zynq_decrypt_load() expects it in terms of words instead
of bytes. This fixes the issue of zynqaes comamnd failure
while decrypting an encrypted image.
Note: roundup can work even without % 4 check before but expectation is
that src and dest is already aligned properly.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
pytest: fpga: Add pytest case for fpga loads command
This patch adds pytest for fpga loads command. This
command is used to verify and load secure bitstreams
on to FPGA. This patch adds two test cases
1. Load authenticated bitstream
2. Load authenticated and encrypted bitstream. Encryption
is with user key.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 2 Mar 2018 07:26:41 +0000 (08:26 +0100)]
test/py: Remove test_qspi_boot_images
Test was designed in a way that jtag boot will load images for qspi boot
but this is not needed anymore. Loading images to qspi is done in
different way.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Add support for verifying secure images
This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Tue, 27 Feb 2018 12:21:30 +0000 (17:51 +0530)]
arm: zynq: Removed CONFIG_SYS_MALLOC_LEN for mini configuration
This patch removed CONFIG_SYS_MALLOC_LEN from the header file as it
was already handled through Kconfig. During nand write operation,
CONFIG_SYS_MALLOC_LEN defined in header file was giving End of Memory
error.
nand write is working fine with the CONFIG_SYS_MALLOC_LEN defined
in cse_nand defconfig.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Mon, 26 Feb 2018 08:52:50 +0000 (14:22 +0530)]
arm64: zynqmp: mini-emmc: Added clock configuration in the device tree
This patch added clock configuration for mini emmc in the
device tree and enabled CONFIG_MMC_SDHCI_ZYNQ in defconfig.
Without CONFIG_MMC_SDHCI_ZYNQ, the device was failed to
register. Without this clk configuration, mmc device was
failed to get clk. CONFIG_DOS_PARTITION will be enabled
through Kconfig and hence removed from header file.
After adding all these changes, emmc is working fine.
This patch fixes the issue with qspi_write_twice by properly
calculating the sizes, offsets and by erasing the region
before writing to it. This also removes unnecessary
erase block. Thsi fixes the issue of CRC failures in
qspi_write_twice.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynqmp: Change kernel and fdt offsets in default environment
This patch changes the kernel and fdt offsets in default environment
as the current offset of 1MB doesn't fit boot image till u-boot due to
increased size of u-boot and other bootimages.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Split emmc configuration into emmc0 and emmc1
This patch splits the current mini emmc configuration into emmc0
and emmc1 configurations because emmc is probed at run time and on
systems which have only one interface mini configuration is failing on
unused interface. For example clock is not enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Dont run any phy detection logic for GMII case
This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 15 Feb 2018 05:54:41 +0000 (11:24 +0530)]
arm64: zynqmp: Changed scratch address used by the alternate memory test
This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the
accessible DDR address used by alternate memory test.
Before this, 0xfffc0000 address was used, which is the OCM
address and not enabled in MMU table. So, whenever trying
to access 0xfffc0000 address, got Synchronous Abort exception.
After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate
memory test is working fine.
Keep origin setting just for mini configurations.
Michal Simek [Mon, 12 Feb 2018 07:15:01 +0000 (08:15 +0100)]
arm64: zynqmp: Move bootargs setting to Kconfig
bootargs should be setup via Kconfig. There are still xilinx commands
which are changing command line based on bootmode which are not moved.
Moving to distro default is probably the best thing to do.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Michal Simek [Fri, 9 Feb 2018 10:04:56 +0000 (11:04 +0100)]
arm64: zynqmp: Cleanup zc12XX defconfigs
The patch
"Kconfig: Select networking commands only when NET is enabled"
(sha1: 99dcbdd8a3c3b6b9d7a4adb32bce73e51e51b7c9)
introduced dependency on NET which is not enabled on zc12xx targets.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 8 Feb 2018 07:58:59 +0000 (08:58 +0100)]
omap4: sdp4430: Enable CONFIG_NET for this platform
Distro default configuration contains also dhcp and pxe setting which
can't working without enabling CONFIG_NET.
EFI is not required that's why it is not enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixed spi-flash sandbox compilation warnings.
There is a variable bank_addr which was set but unused.
Defined this variable on the basis of configs and used
according to that configs.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Thu, 8 Feb 2018 07:28:55 +0000 (12:58 +0530)]
arm: cse-nand: Added pre-relocation property in cse-nand dts
This patch added u-boot,dm-pre-reloc property in the
dts of cse-nand. Without this property, the device was not
getting probe and timer initialization was getting
fail. This property enable the pre-relocation support.
Philipp Tomsich [Fri, 2 Feb 2018 11:01:44 +0000 (12:01 +0100)]
spl: fit: move fdt_record_loadable out of ARCH_FIXUP_FDT_MEMORY guard
The fdt_record_loadable()-function was wedged between other functions
that were guarded by ARCH_FIXUP_FDT_MEMORY. This could lead to linker
errors on some configurations.
With this change, fdt_record_loadable() is moved out of the
ARCH_FIXUP_FDT_MEMORY guard (plus I tried to retain alphabetical
ordering for functions by placing it appropriately).
References: 9f45aeb ("spl: fit: implement fdt_record_loadable") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reported-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ulf Magnusson [Tue, 30 Jan 2018 13:02:01 +0000 (14:02 +0100)]
arm64: zynqmp: Fix misspelled choice default
There is no JTAG symbol in the "Boot mode" choice. JTAG_MODE was
probably intended.
No functional changes. Kconfig choices fall back on using the first
(visible) symbol in the choice as the default if the default symbol is
not visible.
Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib),
which prints the following warning:
warning: the default selection JTAG (undefined) of <choice> (defined at arch/arm/cpu/armv8/zynqmp/Kconfig:107) is not contained in the choice
I've added a corresponding warning to the C tools too, which is
currently in linux-next: https://patchwork.kernel.org/patch/9983667/
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 23 Jan 2018 13:51:15 +0000 (14:51 +0100)]
test: py: Create qspi write continue test
test_qspi_write_twice() is not checking if read back is rewriting
location around start and end in DDR.
Test is doing these steps:
- erasing qspi
- crc32 over full qspi size in DDR
- sf write with 3 writes
- first write inside page size
- second write with size over page size
- third write with rest of data till total size
- sf read the whole qspi back to different DDR location
- crc32 over it
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch typecasts and accesses rx buf properly as
an unaligned rxbuf, typecasting with u16 and accessing
it causes data abort excpetion and this patch fixes it.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq_qspi: Read only one byte at a time from txbuf
Read only one byte at a time from txbuf as txbuf may not be
aligned and accessing more than a byte at a time may cause
alignment issues. This fixes the issue of data abort exception
while writing to flash device.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vipul Kumar [Tue, 16 Jan 2018 10:48:00 +0000 (16:18 +0530)]
mtd: spi-nor: Added support to check addressing mode before calling clean_bar()
SPI erase, write and read operations were not happening properly and due to
this compare operation was getting failed. This patch checks addressing
mode before calling clean_bar() function. There is no need to set bank
address in 4 bytes addressing mode. This is to be inline with write_bar()
function.
Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 10 Jan 2018 08:36:09 +0000 (09:36 +0100)]
arm64: zynqmp: Prepare psu_init rework
Move generic functions to common location psu_spl_init.c. Function
declarations are added to private header.
These changes are done in connection to the fact that still files from
HDF can be copied over and compilation should pass.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 15 Jan 2018 08:59:54 +0000 (09:59 +0100)]
arm64: zynqmp: Remove zcu100-revA/revB board
None is going to run this revA board again. RevB/revC/revD are reworked
and different.
There were only some revBs with ES2 which are also no longer used.
If someone wants to run revA or revB please revert this patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Provide a config to not map DDR region in MMU table
DDR less systems are possible for configuration like mini qspi
and making DDR region as normal memory may cause speculative
access which results u-boot hang if DDR is absent. So, this
patch fixes the issue by not making DDR memory region
entry into MMU table.
Future solution is to prepare MMU table per memory node in dts instead
of hard code DDR addresses.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / thirdparty / u-boot.git / log
