Jithu Joseph [Wed, 22 Mar 2023 00:33:52 +0000 (17:33 -0700)]
platform/x86/intel/ifs: Reorganize driver data
The struct holding device driver data contained both read only(ro)
and read write(rw) fields.
Separating ro fields from rw fields was recommended as
a preferable design pattern during review[1].
Group ro fields into a separate const struct. Associate it to
the miscdevice being registered by keeping its pointer in the
same container struct as the miscdevice.
Nikita Kravets [Mon, 20 Mar 2023 22:55:09 +0000 (01:55 +0300)]
platform/x86: Add new msi-ec driver
Add a new driver to allow various MSI laptops' functionalities to be
controlled from userspace. This includes such features as power
profiles (aka shift modes), fan speed, charge thresholds, LEDs, etc.
This driver contains EC memory configurations for different firmware
versions and exports battery charge thresholds to userspace (note,
that start and end thresholds control the same EC parameter
and are always 10% apart).
Hans de Goede [Mon, 27 Mar 2023 13:03:06 +0000 (15:03 +0200)]
Merge remote-tracking branch 'intel-speed-select/intel-sst' into review-hans
Summary of changes:
Till the commit:
"tools/power/x86/intel-speed-select: Get punit core mapping
information"
All patches just lays foundation for adding new hardware interface
in addition to existing MSR/MMIO interface.
All patches prefixed with "Abstract" just adds individual hardware
callback for functions called from the core processing.
The mailbox processing is abstracted to a new file with callbacks.
In addition some changes to reduce duplicated code for display
of TRL level.
Patch "Introduce Punit ID concept and add related API" add further
abstraction in addition to existing package and die scope.
-----------
tools/power/x86/intel-speed-select: Get punit core mapping information
-Adds a new way to get package/die/punit information for each CPU.
-----------
Introduce TPMI interface support
- Implement all abstracted callbacks above to use TPMI IOCTL interface.
-----------
tools/power/x86/intel-speed-select: Display punit info
- With TPMI the granularity is per punit, which can be multiple in a
package/die.
----------
tools/power/x86/intel-speed-select: Remove cpu mask display for non-cpu
power domain
tools/power/x86/intel-speed-select: Display fact info for non-cpu power
domain
-There are some power domains with no CPUs, the above patches adds CPU
as invalid for these domains
----------
tools/power/x86/intel-speed-select: Use cgroup v2 isolation
- Adds new option to use Cgroup CPU isolation instead of offline of CPUs
----------
tools/power/x86/intel-speed-select: Change TRL display for Emerald Rapids
- Emerald Rapid has multiple TRL levels and moves away from TRL level
based on instruction type
tools/power/x86/intel-speed-select: Change TRL display for Emerald Rapids
Emerald Rapids doesn't specify TRL (Turbo Ratio Limits) based instruction
types. Instead it specifies 5 TRL levels, which can be anyone of the
instruction types.
Increase TRL levels to 5 for Emerald Rapids. Also change display to show
by level number. Show only non zero level values.
tools/power/x86/intel-speed-select: Display AMX base frequency
AMX frequency is present in non TPMI platforms also. When platform
supports, the value is non zero. So, display AMX base frequency when
non zero, irrespective of platform API version.
tools/power/x86/intel-speed-select: Use cgroup v2 isolation
On supported systems, it is possiible to isolate CPUs instead of
CPU online/offline. This is optional and can be specified using
-g option when running as daemon or in combination with -o option
for SST-PP level change.
CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away
from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon.
The IRQ balance daemon is also capable to parse thermal HFI messages to
move IRQs away from CPUS, which are supposed be isolated. But this
requires version released after July 2022.
Zhang Rui [Mon, 8 Aug 2022 16:01:00 +0000 (00:01 +0800)]
tools/power/x86/intel-speed-select: Introduce TPMI interface support
TPMI (Topology Aware Register and PM Capsule Interface) creates a
flexible, extendable and software-PCIe-driver-enumerable MMIO interface
for PM features.
SST feature is exposed via the TPMI interface on newer Xeon platforms.
Kernel TPMI based SST driver provides a series of new IOCTLs for userspace
to use.
Introduce support for the platforms that do SST control via TPMI interface.
Compared with previous platforms, Newer Xeons also supports multi-punit in a
package/die, including cpu punit and non-cpu punit. These have already
been handled in the generic code.
tools/power/x86/intel-speed-select: Get punit core mapping information
Get punit core mapping information using format of MSR 0x54. Based
on the API version, decode is done using new format. The new format
also include a power domain ID. TPMI SST information is for each
power domain.
Zhang Rui [Sat, 20 Aug 2022 12:14:15 +0000 (20:14 +0800)]
tools/power/x86/intel-speed-select: Move send_mbox_cmd to isst-core-mbox.c
After the previous cleanup, there is no user of send_mbox_cmd outside of
isst-core-mbox.c.
Thus move send_mbox_cmd to isst-core-mbox.c as internal functions.
isst_get_pbf_info_complete does nothing but just free the core_mask.
Remove the function and do free core_mask directly and free core mask in
the caller.
isst_fill_platform_info fills platform specific information.
And it is the proper place to set platform specific callbacks, as done in
next patch.
As the platform specific callbacks are needed in all cases, including
isst_print_platform_information.
The best way to achieve both is to invoke isst_fill_platform_info
unconditionally, and make isst_print_platform_information leverage the
data already filled.
Zhang Rui [Sat, 20 Aug 2022 10:38:11 +0000 (18:38 +0800)]
tools/power/x86/intel-speed-select: Move mbox functions to isst-core.c
isst-config.c should only contain generic code.
Move mbox functions which are platform specific code to isst-core.c.
As there are some platform specific parameters set via generic
application options, introduce isst_update_platform_param to pass these
parameters to platform specific code.
for_each_online_package_in_set is actually used to invoke callback for
each power domain.
This is not a problem when there is a single power domain within a
package/die, but it does not reflect the truth in multi-punit case.
Rename for_each_online_package_in_set to
for_each_online_power_domain_in_set.
Zhang Rui [Wed, 17 Aug 2022 17:06:45 +0000 (01:06 +0800)]
tools/power/x86/intel-speed-select: Introduce support for multi-punit
New platforms may have more than 1 punit in a Package/Die, thus it can
have multiple power domains in a Package/Die. Package id and die id is not
sufficient to refer to a specific Power domain.
Introduce support for multi-punit per package/die.
Zhang Rui [Sat, 20 Aug 2022 10:33:01 +0000 (18:33 +0800)]
tools/power/x86/intel-speed-select: Follow TRL nameing for FACT info
SST-TF high priority core count and ratios and low priority core ratios
are also per TRL level.
Cleanup the code to follow the same nameing convention as TRL.
This removes hardcoded TRL level names and variables.
TRL supports different levels including SSE/AVX2/AVX512.
Avoid using hardcoded level name and structure fields, so that a loop can
be used to parse each TRL level instead. This reduces several lines of
source code.
Hans de Goede [Mon, 20 Mar 2023 10:38:15 +0000 (11:38 +0100)]
platform/x86/intel: vsec: Use intel_vsec_dev_release() to simplify init() error cleanup
On auxiliary_device_init(auxdev) failure we need to do the exact same
cleanup steps as on device.release(), so use the intel_vsec_dev_release()
callback for this.
Discovered Intel VSEC/DVSEC capabilities are enabled by default and only
get disabled by quirk. Instead, remove such quirks and only enable support
for capabilities that have been explicitly added to a new capabilities
field. While here, also reorder the device info structures alphabetically.
Hans de Goede [Mon, 13 Mar 2023 13:02:41 +0000 (14:02 +0100)]
platform/x86: pcengines-apuv2: Drop platform:pcengines-apuv2 module-alias
The driver auto-loads based on the DMI modaliases and this platform
modalias is not necessary and broken:
1. Not necessary since the driver itself creates the platform_device,
so it is already loaded when the modalias might be used
2. From a quick scan of the code it does not create any platform-devices
called "platform:pcengines-apuv2"
To support S3/S4 with TPMI interface add suspend/resume callbacks.
Here HW state is stored in suspend callback and restored during
resume callback.
The hardware state which needs to be stored/restored:
- CLOS configuration
- CLOS Association
- SST-CP enable/disable status
- SST-PP perf level setting
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Suggested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Pragya Tanwar <pragya.tanwar@intel.com> Link: https://lore.kernel.org/r/20230308070642.1727167-9-srinivas.pandruvada@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The support of Intel Speed Select Technology - Turbo Frequency (SST-TF)
feature enables the ability to set different “All core turbo ratio
limits” to cores based on the priority. By using this feature, some cores
can be configured to get higher turbo frequency by designating them as
high priority at the cost of lower or no turbo frequency on the low
priority cores.
One new IOCTLs are added:
ISST_IF_GET_TURBO_FREQ_INFO : Get information about turbo frequency
buckets
Once an instance is identified, read or write from correct MMIO
offset for a given field as defined in the specification.
For details on SST-TF operations using intel-speed-selet utility,
refer to:
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
The Intel Speed Select Technology - Base Frequency (SST-BF) feature lets
the user control base frequency. If some critical workload threads demand
constant high guaranteed performance, then this feature can be used to
execute the thread at higher base frequency on specific sets of CPUs
(high priority CPUs) at the cost of lower base frequency (low priority
CPUs) on other CPUs.
Two new IOCTLs are added:
ISST_IF_GET_BASE_FREQ_INFO : Get frequency information for high and
low priority CPUs
ISST_IF_GET_BASE_FREQ_CPU_MASK : CPUs capable of higher frequency
Once an instance is identified, read or write from correct MMIO
offset for a given field as defined in the specification.
For details on SST-BF operations using intel-speed-selet utility,
refer to:
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
This Intel Speed Select Technology - Performance Profile (SST-PP) feature
introduces a mechanism that allows multiple optimized performance profiles
per system. Each profile defines a set of CPUs that need to be online and
rest offline to sustain a guaranteed base frequency.
Five new IOCTLs are added:
ISST_IF_PERF_LEVELS : Get number of performance levels
ISST_IF_PERF_SET_LEVEL : Set to a new performance level
ISST_IF_PERF_SET_FEATURE : Activate SST-BF/SST-TF for a performance level
ISST_IF_GET_PERF_LEVEL_INFO : Get parameters for a performance level
ISST_IF_GET_PERF_LEVEL_CPU_MASK : Get CPU mask for a performance level
Once an instance is identified, read or write from correct MMIO
offset for a given field as defined in the specification.
For details on SST PP operations using intel-speed-selet utility,
refer to:
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
Intel Speed Select Technology Core Power (SST-CP) is an interface that
allows users to define per core priority. This defines a mechanism to
distribute power among cores when there is a power constrained
scenario. This defines a class of service (CLOS) configuration.
Three new IOCTLs are added:
ISST_IF_CORE_POWER_STATE : Enable/Disable SST-CP
ISST_IF_CLOS_PARAM : Configure CLOS parameters
ISST_IF_CLOS_ASSOC : Associate CPUs to a CLOS
To associate CPUs to CLOS, either Linux CPU numbering or PUNIT numbering
scheme can be used, using parameter punit_cpu_map (1: for PUNIT numbering
0 for Linux CPU number).
There is no change to IOCTL to get PUNIT CPU number for a CPU.
Introduce get_instance() function, which is used by majority of IOCTLs
processing to convert a socket and power domain to
tpmi_per_power_domain_info * instance. This instance has all the MMIO
offsets stored to read a particular field.
Once an instance is identified, read or write from correct MMIO
offset for a given field as defined in the specification.
For details on SST CP operations using intel-speed-selet utility,
refer to:
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
platform/x86: ISST: Parse SST MMIO and update instance
SST registers are presented to OS in multi-layer structures starting
with a SST header showing version information freezing current
definition.
For details on SST terminology refer to
Documentation/admin-guide/pm/intel-speed-select.rst
under the kernel documentation
SST TPMI details are published in the following document:
https://github.com/intel/tpmi_power_management/blob/main/SST_TPMI_public_disclosure_FINAL.docx
SST MMIO structure layout follows:
SST-HEADER
SST-CP Header
SST-CP CONTROL
SST-CP STATUS
SST-CP CONFIG0
SST-CP CONFIG1
...
...
SST-PP Header
SST-PP OFFSET_0
SST-PP OFFSET_1
SST_PP_0_INFO
SST_PP_1_INFO
SST_PP_2_INFO
SST_PP_3_INFO
SST-PP CONTROL
SST-PP STATUS
Each register bank contains information to get to next lower level
information. This information is parsed and stored in the struct
tpmi_per_power_domain_info for each domain. This information is
used to process each SST requests.
platform/x86: ISST: Enumerate TPMI SST and create framework
Enumerate TPMI SST driver and create basic framework to add more
features.
The basic user space interface is still same as the legacy using
/dev/isst_interface. Users of "intel-speed-select" utility should
be able to use same commands as prior gens without being aware
of new underlying hardware interface.
TPMI SST driver enumerates on device "intel_vsec.tpmi-sst". Since there
can be multiple instances and there is one common SST core, split
implementation into two parts: A common core part and an enumeration
part. The enumeration driver is loaded for each device instance and
register with the TPMI SST core driver.
On very first enumeration the TPMI SST core driver register with SST
core driver to get IOCTL callbacks. The api_version is incremented
for IOCTL ISST_IF_GET_PLATFORM_INFO, so that user space can issue
new IOCTLs.
Each TPMI package contains multiple power domains. Each power domain
has its own set of SST controls. For each domain map the MMIO memory
and update per domain struct tpmi_per_power_domain_info. This information
will be used to implement other SST interfaces.
Implement first IOCTL commands to get number of TPMI SST instances
and instance mask as some of the power domains may not have any
SST controls.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Pragya Tanwar <pragya.tanwar@intel.com> Link: https://lore.kernel.org/r/20230308070642.1727167-3-srinivas.pandruvada@linux.intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
To map Linux CPU numbering scheme to hardware CPU numbering scheme
MSR 0x53 is getting used. But for new generation of CPUs, this MSR
is not valid. Since this is model specific MSR, this is possible.
A new MSR 0x54 is defined for this purpose. User space can use the
API version to distinguish format from MSR 0x53.
Intel speed select utility is updated to use the new format based
on the API version.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Reviewed-by: Zhang Rui <rui.zhang@intel.com> Tested-by: Pragya Tanwar <pragya.tanwar@intel.com> Link: https://lore.kernel.org/r/20230308070642.1727167-2-srinivas.pandruvada@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Maximilian Luz [Sat, 4 Mar 2023 19:46:09 +0000 (20:46 +0100)]
platform/surface: aggregator_tabletsw: Properly handle different posture source IDs
The device posture subsystem (POS) can provide different posture
sources. Different sources can provide different posture states and
sources can be identified by their ID.
For example, screen posture of the Surface Laptop Studio (SLS), which is
currently the only supported source, uses a source ID of 0x03. The
Surface Pro 9 uses the same subsystem for its Type-Cover, however,
provides different states for that under the ID 0x00.
To eventually support the Surface Pro 9 and potential future devices, we
need to properly disambiguate between source IDs. Therefore, add the
source ID to the state we carry and determine the tablet-mode state (as
well as state names) based on that.
Hans de Goede [Fri, 3 Mar 2023 22:19:28 +0000 (23:19 +0100)]
platform/x86: Add intel_bytcrc_pwrsrc driver
Add a new driver for the power-, wake- and reset-source functionality
of the Bay Trail (BYT) version of the Crystal Cove PMIC.
The main functionality here is detecting which power-sources (USB /
DC in / battery) are active. This is normally exposed to userspace as
a power_supply class charger device with an online sysfs attribute.
But if a charger is online or not is already exposed on BYT-CRC devices
through either an ACPI AC power_supply device, or through a native driver
for the battery charger chip (e.g. a BQ24292i).
So instead of adding duplicate info under the power_supply class this
driver exports the info through debugfs and likewise adds debugfs files
for the reset- and wake-source info / registers.
Despite this driver only exporting debugfs bits it is still useful to
have this driver because it clears the wake- and reset-source registers
after reading them. Not clearing these can have undesirable side-effects.
Specifically if the WAKESRC register contains 0x01 (wake by powerbutton)
on reboot then the firmware on some tablets turns the reboot into
a poweroff. I guess this may be necessary to make long power-presses turn
into a poweroff somehow?
Hans de Goede [Tue, 7 Mar 2023 12:05:40 +0000 (13:05 +0100)]
backlight: apple_bl: Use acpi_video_get_backlight_type()
On some MacBooks both the apple_bl and the apple-gmux backlight drivers
may be able to export a /sys/class/backlight device.
To avoid having 2 backlight devices for one LCD panel until now
the apple-gmux driver has been calling apple_bl_unregister() to move
the apple_bl backlight device out of the way when it loads.
Similar problems exist on other x86 laptops and all backlight drivers
which may be used on x86 laptops have moved to using
acpi_video_get_backlight_type() to determine whether they should load
or not.
Switch apple_bl to this model too, so that it is consistent with all
the other x86 backlight drivers.
Besides code-simplification and consistency this has 2 other benefits:
1) It removes a race during boot where userspace will briefly see
an apple_bl backlight and then have it disappear again, leading to e.g.:
https://bbs.archlinux.org/viewtopic.php?id=269920
2) This allows user to switch between the drivers by passing
acpi_backlight=apple_gmux or acpi_backlight=vendor on the kernel
commandline.
Commit fc83fbc80e1a ("platform/x86: apple-gmux: refactor gmux types")
neglected to update the documentation of apple_gmux_detect's arguments.
Update the documentation to reflect that commit's changes.
include/linux/apple-gmux.h:99: warning:
Function parameter or member 'type_ret' not described in 'apple_gmux_detect'
include/linux/apple-gmux.h:99: warning:
Excess function parameter 'indexed_ret' description in 'apple_gmux_detect'
Make apple-gmux backlight registration honor the acpi_backlight=...
kernel commandline option which is used to select the backlight
control method on x86/ACPI devices.
platform/x86: apple-gmux: support MMIO gmux on T2 Macs
In some newer dual gpu MacBooks, the T2 Coprocessor functions as the
gmux, and the Intel side can interract with this new gmux type through
MMIO. Add support for these gmux controllers to the apple-gmux driver.
We start using the GMSP(0) acpi method on these gmux's when clearing
interrupts, as this prevents a flood of status=0 interrupts that can't
be cleared. It's unknown if this helps or hinders older gmux types, so
it isn't enabled for those.
Interestingly, the ACPI table only allocates 8 bytes for GMUX, but we
actually need 16, and as such we request 16 with request_mem_region.
Reading and writing from ports:
16 bytes from 0xfe0b0200 are used. 0x0 to 0x4 are where data
to read appears, and where data to write goes. Writing to 0xe
sets the gmux port being accessed, and writing to 0xf sends commands.
These commands are 0x40 & data_length for write, and data_length for
read, where data_length is 1, 2 or 4. Once byte base+0xf is 0, the
command is done.
Issues:
As with other retina models, we can't switch DDC lines so
switching at runtime doesn't work if the inactive gpu driver
already disabled eDP due to it not being connected when that
driver loaded.
Additionally, turning on the dgpu back on on the MacBookPro16,1 does
not work.
platform/x86: apple-gmux: use first bit to check switch state
On T2 Macs with MMIO gmux, when GMUX_PORT_SWITCH_DISPLAY is read, it can
have values of 2, 3, 4, and 5. Odd values correspond to the discrete gpu,
and even values correspond to the integrated gpu. The current logic is
that only 2 corresponds to IGD, but this doesn't work for T2 Macs.
Instead, check the first bit to determine the connected gpu.
As T2 Macs with gmux only can switch the internal display, it is
untested if this change (or a similar change) would be applicable
to GMUX_PORT_SWITCH_DDC and GMUX_PORT_SWITCH_EXTERNAL.
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