Alexey Klimov [Thu, 27 Jun 2024 00:36:54 +0000 (01:36 +0100)]
pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
Account for more than only 23 GPIOs in LPASS Low Power Island pinctrl
generic driver. The previous value 23 was chosen to satisfy existing
SoC-specific drivers. However SM4250 LPI pinctrl uses more than 23 GPIOs
and its probe routine fails on:
if (WARN_ON(data->npins > MAX_NR_GPIO))
return -EINVAL;
Patrick Rudolph [Wed, 26 Jun 2024 08:45:23 +0000 (10:45 +0200)]
pinctrl: cy8c95x0: Update cache modification
In the previous review cycle the regmap cache update code was
questioned since it seems and odd way of using regmap_update_bits().
Thus update the regmap cache modification code to better explain
what it does and why it's done. This is no functional change, but
it's improving code maintainability.
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series
Hardware User's Manual still has two alternate pins named both TCLK3
and TCLK4. To differentiate, the pin control driver uses "TCLK[34]" and
"TCLK[34]_X". In addition, there are alternate pins without suffix, and
with an "_A" or "_B" suffix.
Increase uniformity by adopting R-Car V4M naming:
- Rename "TCLK2_B" to "TCLK2_C",
- Rename "TCLK[12]_A" to "TCLK[12]_B",
- Rename "TCLK[12]" to "TCLK[12]_A",
- Rename "TCLK[34]_A" to "TCLK[34]_C",
- Rename "TCLK[34]_X" to "TCLK[34]_A",
- Rename "TCLK[34]" to "TCLK[34]_B".
The suffixes of the IRQ identifiers for external interrupts 0-3
are inconsistent:
- "IRQ0" and "IRQ0_A",
- "IRQ1" and "IRQ1_A",
- "IRQ2" and "IRQ2_A",
- "IRQ3" and "IRQ3_B".
The suffixes for external interrupts 4 and 5 do follow conventional
naming:
- "IRQ4A" and IRQ4_B",
- "IRQ5".
Fix this by adopting R-Car V4M naming:
- Rename "IRQ[0-2]_A" to "IRQ[0-2]_B",
- Rename "IRQ[0-3]" to "IRQ[0-3]_A".
(H)SCIF instance 3 has two alternate pin groups: "hscif3" and
"hscif3_a", resp. "scif3" and "scif3_a", but the actual meanings of the
pins within the groups do not match.
Increase uniformity by adopting R-Car V4M naming:
- Rename "hscif3_a" to "hscif3_b",
- Rename "hscif3" to "hscif3_a",
- Rename "scif3" to "scif3_b".
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series
Hardware User's Manual still has two alternate pin groups (GP0_14-18
and GP1_6-10) each named both HSCIF1 and SCIF1. To differentiate, the
pin control driver uses "(h)scif1" and "(h)scif1_x", which were
considered temporary names until the conflict was sorted out.
Fix this by adopting R-Car V4M naming:
- Rename "(h)scif1" to "(h)scif1_a",
- Rename "(h)scif1_x" to "(h)scif1_b".
Adopt the R-Car V4M naming "(h)scif1_a" and "(h)scif1_b" to increase
uniformity.
The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series
Hardware User's Manual still has two alternate pins named both
"FXR_TXEN[AB]". To differentiate, the pin control driver uses
"FXR_TXEN[AB]" and "FXR_TXEN[AB]_X", which were considered temporary
names until the conflict was sorted out.
Fix this by adopting R-Car V4M naming:
- Rename "FXR_TXEN[AB]" to "FXR_TXEN[AB]_A",
- Rename "FXR_TXEN[AB]_X" to "FXR_TXEN[AB]_B".
The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin
but served as a flag indicating that the pins of a port have different
capabilities.
To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside
`RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally,
introduce new macros for packing variable port configurations:
- `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG`
with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations
for a packed port.
- `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines
`RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle
variable pin configurations for a sparse port.
Due to the above change the configuration macros have been reorganized
as follows:
- Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`,
`PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one
to accommodate the removal of `PIN_CFG_VARIABLE`.
Lad Prabhakar [Tue, 18 Jun 2024 17:48:29 +0000 (18:48 +0100)]
pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62)
Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`,
to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`.
Previously, these bit masks were placed higher up in the bit range, which
did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these
masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any
conflicts. The updated masks are now:
- `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`)
- `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`)
Jeff Johnson [Tue, 11 Jun 2024 04:21:05 +0000 (21:21 -0700)]
pinctrl: add missing MODULE_DESCRIPTION() macros
When ARCH=x86, make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/bcm/pinctrl-bcm4908.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_i2c.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08_spi.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/pinctrl-mcp23s08.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pinctrl/meson/pinctrl-meson.o
Add the missing invocation of the MODULE_DESCRIPTION() macro to all
files which have a MODULE_LICENSE().
This includes many meson drivers which, although they did not produce
a warning with the x86 allmodconfig configuration, may cause this
warning with ARM or ARM64 configurations.
Sean Anderson [Mon, 10 Jun 2024 22:35:50 +0000 (18:35 -0400)]
pinctrl: zynqmp: Support muxing individual pins
While muxing groups of pins at once can be convenient for large
interfaces, it can also be rigid. This is because the group is set to
all pins which support a particular function, even though not all pins
may be used. For example, the sdhci0 function may be used with a 8-bit
eMMC, 4-bit SD card, or even a 1-bit SD card. In these cases, the extra
pins may be repurposed for other uses, but this is not currently
allowed.
There is not too much point in pin "groups" when there are not actual
pin groups at the hardware level. The pins can all be muxed
individually, so there's no point in adding artificial groups on top.
Just mux the pins like the hardware allows.
To this effect, add a new group for each pin which can be muxed. These
groups are part of each function the pin can be muxed to. We treat group
selectors beyond the number of groups as "pin" groups. To set this up,
we initialize groups before functions, and then create a bitmap of used
pins for each function. These used pins are appended to the function's
list of groups.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev> Reviewed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240610223550.2449230-3-sean.anderson@linux.dev Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yang Yingliang [Thu, 6 Jun 2024 02:37:04 +0000 (10:37 +0800)]
pinctrl: ti: ti-iodelay: fix possible memory leak when pinctrl_enable() fails
This driver calls pinctrl_register_and_init() which is not
devm_ managed, it will leads memory leak if pinctrl_enable()
fails. Replace it with devm_pinctrl_register_and_init().
And add missing of_node_put() in the error path.
Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-4-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yang Yingliang [Thu, 6 Jun 2024 02:37:03 +0000 (10:37 +0800)]
pinctrl: single: fix possible memory leak when pinctrl_enable() fails
This driver calls pinctrl_register_and_init() which is not
devm_ managed, it will leads memory leak if pinctrl_enable()
fails. Replace it with devm_pinctrl_register_and_init().
And call pcs_free_resources() if pinctrl_enable() fails.
Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-3-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Yang Yingliang [Thu, 6 Jun 2024 02:37:02 +0000 (10:37 +0800)]
pinctrl: core: fix possible memory leak when pinctrl_enable() fails
In devm_pinctrl_register(), if pinctrl_enable() fails in pinctrl_register(),
the "pctldev" has not been added to dev resources, so devm_pinctrl_dev_release()
can not be called, it leads memory leak.
Introduce pinctrl_uninit_controller(), call it in the error path to free memory.
Fixes: 5038a66dad01 ("pinctrl: core: delete incorrect free in pinctrl_enable()") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20240606023704.3931561-2-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andrew Jeffery [Fri, 31 May 2024 03:02:47 +0000 (12:32 +0930)]
dt-bindings: pinctrl: aspeed: Use block syntax for function and groups
The expansion makes the documents a lot longer, but it's easier to
review changes to functions and groups when we're not having to deal
with line wrapping.
pinctrl: keembay: Fix func conversion in keembay_build_functions()
A recent refactoring to use the func member in struct function_desc
missed converting one uses of name in keembay_build_functions(),
resulting in a build failure:
drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_build_functions':
drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no member named 'name'
1630 | if (!fdesc->name) {
| ^~
Perform the same conversion to resolve the build error.
Fixes: 73ee52205e5a ("pinctrl: keembay: Convert to use func member") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20240611-pinctrl-keembay-fix-func-conversion-v1-1-3197f2ded3f7@kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406131133.WwdetfBL-lkp@intel.com/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Peng Fan [Tue, 21 May 2024 06:25:59 +0000 (14:25 +0800)]
pinctrl: imx: support SCMI pinctrl protocol for i.MX95
The generic pinctrl-scmi.c driver could not be used for i.MX95 because
i.MX95 SCMI firmware not supports functions, groups or generic
'Pin Configuration Type and Enumerations' listed in SCMI Specification.
i.MX95 System Control Management Interface(SCMI) firmware only supports
below pin configuration types which are OEM specific types:
192: PIN MUX
193: PIN CONF
194: DAISY ID
195: DAISY VAL
To Support fsl,pins property together with SCMI OEM protocol, add this
driver.
Peng Fan [Tue, 21 May 2024 06:25:58 +0000 (14:25 +0800)]
pinctrl: scmi: add blocklist
i.MX95 will have its own pinctrl scmi driver, so need block
pinctrl-scmi driver for i.MX95, otherwise there will be two pinctrl
devices for a single scmi protocol@19.
Peng Fan [Tue, 21 May 2024 06:25:57 +0000 (14:25 +0800)]
dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM extensions
i.MX95 Pinctrl is managed by System Control Management Interface(SCMI)
firmware using OEM extensions. No functions, no groups are provided by
the firmware. So add i.MX95 specific properties.
To keep aligned with current i.MX pinctrl bindings, still use "fsl,pins"
for i.MX95.
Richard Acayan [Thu, 23 May 2024 23:06:20 +0000 (19:06 -0400)]
pinctrl: qcom: sdm670: add pdc wakeirq map
The PDC was hooked up as a wakeup parent in the DTS in
commit 71f080633d1e ("arm64: dts: qcom: sdm670: Hook up PDC as
wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it
had no effect. Add the mapping for wakeup interrupts on the PDC to their
corresponding pins.
Configuring a pin IRQ as dual-edge would break it unless the
wakeirq_dual_edge_errata flag is set.
Patrick Rudolph [Tue, 21 May 2024 15:25:57 +0000 (17:25 +0200)]
pinctrl: cy8c95x0: Use single I2C lock
Currently there are 3 locks being used when accessing the chip, one
in the driver and one in each regmap. Reduce that to one driver only
lock that protects all regmap and regcache accesses.
Andy Shevchenko [Thu, 30 May 2024 08:55:19 +0000 (11:55 +0300)]
pinctrl: mediatek: moore: Convert to use func member
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Andy Shevchenko [Thu, 30 May 2024 08:55:18 +0000 (11:55 +0300)]
pinctrl: keembay: Convert to use func member
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Andy Shevchenko [Thu, 30 May 2024 08:55:17 +0000 (11:55 +0300)]
pinctrl: ingenic: Convert to use func member
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Andy Shevchenko [Thu, 30 May 2024 08:55:16 +0000 (11:55 +0300)]
pinctrl: imx: Convert to use func member
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.
Andy Shevchenko [Thu, 30 May 2024 08:55:15 +0000 (11:55 +0300)]
pinctrl: pinmux: Embed struct pinfunction into struct function_desc
struct function_desc is a particular version of the struct pinfunction
with associated opaque data. Start switching pin control core and
drivers to use it explicitly.
Swati Agarwal [Mon, 27 May 2024 10:57:15 +0000 (12:57 +0200)]
pinctrl: pinctrl-zynqmp: Use pin numbers stored in pin descriptor
Use pin numbers stored in the pin descriptors instead of index value while
creating the pin groups. Pin Id's are not same as Index values for Xilinx
Versal platform, so use the pin values from descriptor which works for both
ZynqMP and Versal platforms.
Weihao Li [Mon, 27 May 2024 02:20:36 +0000 (10:20 +0800)]
pinctrl: ralink: mt76x8: fix pinmux function
The current version of the pinctrl driver has some issues:
1. Duplicated "gpio" pmx function
The common code will add a "gpio" pmx functon to every pin group, so
it's not necessary to define a separate "gpio" pmx function in pin
groups.
2. Duplicated pmx function name
There are some same function name in different pin groups, which will
cause some problems. For example, when we want to use PAD_GPIO0 as
refclk output function, the common clk framework code will search the
entire pin function lists, then return the first one matched, in this
case the matched function list only include the PAD_CO_CLKO pin group
because there are three "refclk" pin function, which is added by
refclk_grp, spi_cs1_grp and gpio_grp.
To solve this problem, a simple way is just add a pingrp refix to
function name like mt7620 pinctrl driver does.
3. Useless "-" or "rsvd" functon
It's really unnecessary to add a reserved pin mux function to the
function lists, because we never use it.
pinctrl: pinctrl-tps6594: make tps65224_muxval_remap and tps6594_muxval_remap as static to fix sparse warning
pinctrl: tps6594: Fix sparse warning.
warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static?
warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static?
pinctrl: core: reset gpio_device in loop in pinctrl_pins_show()
We were not resetting the pointer to the associated gpio_device once
we are done displaying a pin's information.
This meant that once we reached the end of a gpio-range, if there
were pins right after it that did not belong to any known range,
they would be associated with the previous range's gpio device.
This resulted in those pins appearing as <4294966783:old_gdev> instead
of the expected <0:?> (due to gpio_num being -1).
pinctrl: core: take into account the pins array in pinctrl_pins_show()
We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges
struct for determining if a pin matched a GPIO number.
This value is present only if the 'pins' array is not NULL,
and is 0 otherwise. This means that GPIO ranges declared using
gpiochip_add_pingroup_range(), thus making use of pins, were always matched
by the pins in the range [0-npins] even if they contained pins in a
completely separate range.
Jacky Huang [Tue, 21 May 2024 01:24:45 +0000 (01:24 +0000)]
dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node
Add a compatible 'syscon' to the system management node since the system
control registers are mapped by this driver. The other driver must access
the system control registers through 'regmap' using a phandle that
references this node.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20240521012447.42211-2-ychuang570808@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Peng Fan [Mon, 13 May 2024 09:20:46 +0000 (17:20 +0800)]
dt-bindings: pinctrl: imx: Support i.MX91 IOMUXC
i.MX91 and i.MX93 share similar design. They could share same dt-binding
doc, so rename fsl,imx93-pinctrl.yaml to fsl,imx9-pinctrl.yaml and add
i.MX91 compatible string
Add documentation for the pin controller found on the Renesas RZ/V2H(P)
(R9A09G057) SoC. The RZ/V2H PFC varies slightly compared to the RZ/G2L
family:
- Additional bits need to be set during pinmuxing,
- The GPIO pin count is different.
Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
added for the RZ/V2H(P) SoC.
Also, add the 'renesas,output-impedance' property. The drive strength
settings on RZ/V2H(P) depend on the different power rails coming out from
the PMIC (connected via I2C). These power rails (required for drive
strength) can be 1.2V, 1.8V, or 3.3V.
The 'renesas,output-impedance' property, as documented, can be
[0, 1, 2, 3], these correspond to register bit values that can
be set in the PFC_IOLH_mn register, which adjusts the drive
strength value and is pin-dependent.
As power rail information may not be available very early in the boot
process, the 'renesas,output-impedance' property is added instead of
reusing the 'output-impedance-ohms' property.
Also, allow bias-disable, bias-pull-down and bias-pull-up properties
as these can be used to configure the pins.
Lad Prabhakar [Thu, 30 May 2024 17:38:53 +0000 (18:38 +0100)]
pinctrl: renesas: rzg2l: Add support for pull-up/down
Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.
Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.
Lad Prabhakar [Thu, 30 May 2024 17:38:51 +0000 (18:38 +0100)]
pinctrl: renesas: rzg2l: Add function pointers for OEN register access
Introduce function pointers oen_read() and oen_write(), in the struct
rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before
writing to the PFC_OEN register is necessary, and the PFC_OEN register
has more bits compared to the RZ/G2L family. To handle these
differences between RZ/G2L and RZ/V2H(P) and to reuse the existing code
for RZ/V2H(P), these function pointers are introduced.
Additionally, populate these function pointers with appropriate data for
existing SoCs.
Lad Prabhakar [Thu, 30 May 2024 17:38:50 +0000 (18:38 +0100)]
pinctrl: renesas: rzg2l: Add function pointer for PMC register write
Introduces pmc_writeb() function pointer, in the struct
rzg2l_pinctrl_data to facilitate writing to the PMC register. On the
RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC
registers is required, whereas this is not the case for the existing
RZ/G2L family. This addition enables the reuse of existing code for
RZ/V2H(P). Additionally, populate this function pointer with
appropriate data for existing SoCs.
Note that this functionality is only handled in rzg2l_gpio_request(), as
PMC unlock/lock during PFC setup will be taken care of in the
pwpr_pfc_lock_unlock() function pointer.
Lad Prabhakar [Thu, 30 May 2024 17:38:49 +0000 (18:38 +0100)]
pinctrl: renesas: rzg2l: Add function pointer for PFC register locking
On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
writing to both PFC and PMC registers. Additionally, BIT(7) B0WI is
undocumented for the PWPR register on RZ/V2H(P) SoC. To accommodate these
differences across SoC variants, introduce the pwpr_pfc_lock_unlock()
function pointer.
Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false)
is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is
now called after PMC read/write this is to keep changes minimal for
RZ/V2H(P) SoC.
Lad Prabhakar [Thu, 30 May 2024 17:38:48 +0000 (18:38 +0100)]
pinctrl: renesas: rzg2l: Validate power registers for SD and ETH
On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
resulting in invalid register offsets. Ensure that the register offsets
are valid before any read/write operations are performed. If the power
registers are not available, both SD and ETH will be set to '0'.
projects / thirdparty / kernel / linux.git / log
