jason [Fri, 11 Jan 2019 22:37:01 +0000 (22:37 +0000)]
PR c++/88312 - pack expansion of decltype.
The standard doesn't really talk about an expression depending on the number
of elements of a pack, but that's definitely an important form of template
argument dependence.
* pt.c (instantiation_dependent_r): A template non-type parameter
pack is instantiation-dependent.
jason [Fri, 11 Jan 2019 22:36:20 +0000 (22:36 +0000)]
PR c++/88613 - ICE with use of const var in lambda.
The issue here was that we were cp_folding a location wrapper around a
lambda capture proxy before it had been mark_rvalue_used. I considered
adding mark_rvalue_use calls to build_new_op_1, but it seems appropriate to
have them in cp_fold_maybe_rvalue when we know we're trying to produce an
rvalue.
The change to mark_use is for a related issue: when we change the operand of
the location wrapper from VAR_DECL to INTEGER_CST, we need the TREE_CODE of
the location wrapper to change as well, from VIEW_CONVERT_EXPR to
NON_LVALUE_EXPR.
jakub [Fri, 11 Jan 2019 21:03:53 +0000 (21:03 +0000)]
PR middle-end/85956
PR lto/88733
* tree-inline.h (struct copy_body_data): Add adjust_array_error_bounds
field.
* tree-inline.c (remap_type_1): Formatting fix. If TYPE_MAX_VALUE of
ARRAY_TYPE's TYPE_DOMAIN is newly error_mark_node, replace it with
a dummy "omp dummy var" variable if id->adjust_array_error_bounds.
* omp-low.c (new_omp_context): Set cb.adjust_array_error_bounds.
fortran/
* trans-openmp.c: Include attribs.h.
(gfc_walk_alloc_comps, gfc_omp_clause_linear_ctor): Handle
VAR_DECL max bound with "omp dummy var" attribute like NULL or
error_mark_node - recompute number of elts independently.
testsuite/
* c-c++-common/gomp/pr85956.c: New test.
* g++.dg/gomp/pr88733.C: New test.
burnus [Fri, 11 Jan 2019 19:40:13 +0000 (19:40 +0000)]
PR C++/88114 Gen destructor of an abstract class
PR C++/8811
* decl2.c (maybe_emit_vtables): If needed, generate code for
the destructor of an abstract class.
(mark_used): Update comment for older function-name change.
vmakarov [Fri, 11 Jan 2019 19:25:31 +0000 (19:25 +0000)]
2019-01-11 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/87305
* lra-assigns.c
(setup_live_pseudos_and_spill_after_risky_transforms): Add code
for little endian pseudos used as paradoxical subreg.
jakub [Fri, 11 Jan 2019 19:04:32 +0000 (19:04 +0000)]
PR tree-optimization/88693
* tree-ssa-strlen.c (get_min_string_length): Don't set *full_string_p
for STRING_CSTs that don't contain any NUL characters in the first
TREE_STRING_LENGTH bytes.
law [Fri, 11 Jan 2019 18:44:00 +0000 (18:44 +0000)]
PR 88777
PR 88614
* genattrtab.c (min_fn): Don't translate values.
(min_attr_value): Return INT_MAX when the value can't be calculated.
Return minimum among any values that can be calculated.
(max_attr_value): Adjust.
sje [Fri, 11 Jan 2019 15:53:02 +0000 (15:53 +0000)]
2019-01-11 Steve Ellcey <sellcey@marvell.com>
* config/aarch64/aarch64.c (aarch64_simd_call_p): New function.
(aarch64_remove_extra_call_preserved_regs): New function.
(TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New macro.
* doc/tm.texi.in (TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New hook.
* doc/tm.texi: Regenerate.
* final.c (get_call_reg_set_usage): Call new hook.
* target.def (remove_extra_call_preserved_regs): New hook.
* targhooks.c (default_remove_extra_call_preserved_regs): New function.
* targhooks.h (default_remove_extra_call_preserved_regs): New function.
vries [Fri, 11 Jan 2019 11:46:43 +0000 (11:46 +0000)]
[nvptx] Don't allow vector_length 64 with num_workers 16
When using a compiler build with:
...
+#define PTX_DEFAULT_VECTOR_LENGTH PTX_CTA_SIZE
...
consider a test-case:
...
int
main (void)
{
#pragma acc parallel vector_length (64)
#pragma acc loop worker
for (unsigned int i = 0; i < 32; i++)
#pragma acc loop vector
for (unsigned int j = 0; j < 64; j++)
;
return 0;
}
...
If num_workers is 16, either because:
- we add a "num_workers (16)" clause on the parallel directive, or
- we set "GOMP_OPENACC_DIM=:16:", or
- the libgomp plugin chooses 16 num_workers
we run into an illegal instruction at runtime, because a bar.sync instruction
tries to use a barrier 16. The instruction is illegal, because ptx supports
only 16 barriers per CTA, and the valid range is 0..15.
The problem is that with a warp-multiple vector length, we use a code generation
scheme with a per-worker barrier. And because barrier zero is reserved for
per-cta barrier, only the remaining 15 barriers can be used as per-worker
barrier, and consequently we can't use num_workers larger than 15.
This problem occurs only for vector_length 64. For vector_length 32, we use a
different code generation scheme, and for vector_length >= 96, the maximum
num_workers is not big enough not to trigger this problem.
Also, this problem only occurs for num_workers 16. As explained above,
num_workers 15 is safe to use, and 16 is already the maximum num_workers for
vector_length 64.
This patch fixes the problem in both the compiler (handling "num_workers (16)")
and in the libgomp nvptx plugin (with and without "GOMP_OPENACC_DIM=:16:").
vries [Fri, 11 Jan 2019 11:46:06 +0000 (11:46 +0000)]
[libgomp, testsuite, openacc] Remove -foffload=-w in reduction-[1-5].c
Before the commit "[libgomp, testsuite, openacc] Don't use const int for
dimensions", the "const int" construct was used to set launch dimensions in
reductions-[1-5].c. In the case of -xc -O0, the const int is implemented as a
variable by the C front-end. Consequently, the nvptx back-end generated
warnings that vector_length was overridden to be hard-coded, rather than left to
be set at runtime. The test-cases silenced these warnings by switching off all
warnings in the accelerator compiler using "-foffload=-w".
Given that no warnings occur anymore, remove the "-foffload=-w" setting.
jbeulich [Fri, 11 Jan 2019 11:20:40 +0000 (11:20 +0000)]
x86-64: {,V}CVT{,U}SI2Sx are ambiguous without suffix
For 64-bit these should not be emitted without suffix in AT&T mode (as
being ambiguous that way); the suffixes are benign for 32-bit. For
consistency also omit the suffix in Intel mode for {,V}CVTSI2SxQ.
The omission has originally (prior to rev 260691) lead to wrong code
being generated for the 64-bit unsigned-to-float/double conversions (as
gas guesses an L suffix instead of the required Q one when the operand
is in memory). In all remaining cases (being changed here) the omission
would "just" lead to warnings with future gas versions.
As a result, arrange to check for the L suffixes in 32-bit test cases.
In order for related test cases to actually test what they're supposed
to test, add (seemingly unrelated) a few empty "asm volatile()".
Presumably there are more where constant propagation voids the intended
effect of the tests, but these are ones helping make sure the assembler
actually still assembles correctly the output after the changes here.
redi [Fri, 11 Jan 2019 10:25:46 +0000 (10:25 +0000)]
Fix incorrect linker script patterns
The recent changes to support operator<<(nullptr_t) changed the glob
patterns for existing operator<<(T) overloads, but did so incorrectly so
they still matched the new symbols. That broke Solaris bootstrap. This
patch replaces each of the existing globs by two more precise ones,
which match the old symbols but not the new ones.
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Correct recent changes to
basic_ostream::operator<< patterns.
vmakarov [Thu, 10 Jan 2019 21:02:50 +0000 (21:02 +0000)]
2019-01-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/87305
* lra-assigns.c
(setup_live_pseudos_and_spill_after_risky_transforms): Check
allocation for big endian pseudos used as paradoxical subregs and
spill them if it is wrong.
* lra-constraints.c (lra_constraints): Add a comment.
sudi [Thu, 10 Jan 2019 17:29:54 +0000 (17:29 +0000)]
[Committed, AArch64] Disable tests for ilp32.
Currently Return Address Signing is only supported in lp64. Thus the
tests that I added recently (that enables return address signing by the
mbranch-protection=standard option), should also be exempted from testing in
ilp32. This patch adds the needed dg-require-effective-target directive in the
tests.
jakub [Thu, 10 Jan 2019 15:44:16 +0000 (15:44 +0000)]
PR middle-end/84877
PR bootstrap/88450
* function.c (assign_stack_local_1): Revert the 2018-11-21 changes.
(assign_parm_setup_block): Do the argument slot realignment here
instead.
redi [Thu, 10 Jan 2019 13:49:31 +0000 (13:49 +0000)]
Define __cpp_lib_erase_if feature test macro
The C++2a draft specifies the value 201811L for this, but as an
extension we return the number of elements erased. This is expected to
be standardised, so the macro has the value 201900L until a proper value
is specified in the draft.
redi [Thu, 10 Jan 2019 13:14:57 +0000 (13:14 +0000)]
Implement LWG 2221: formatted output operator for nullptr
2019-01-10 Ville Voutilainen <ville.voutilainen@gmail.com>
Jonathan Wakely <jwakely@redhat.com>
Implement LWG 2221
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Tighten patterns.
(GLIBCXX_3.4.26): Add new exports.
* include/Makefile.am: Add ostream-inst.cc. Move string-inst.cc to
correct list of sources.
* include/Makefile.in: Regenerate.
* include/std/ostream (operator<<(nullptr_t)): New member function.
* src/c++17/ostream-inst.cc: New file.
* testsuite/27_io/basic_ostream/inserters_other/char/lwg2221.cc: New
test.
ktkachov [Thu, 10 Jan 2019 11:36:42 +0000 (11:36 +0000)]
ARM: fix -masm-syntax-unified (PR88648)
This allows to use unified asm syntax when compiling for the
ARM instruction. This matches documentation and seems what the
initial patch was intended doing when the flag got added.
2019-01-10 Stefan Agner <stefan@agner.ch>
PR target/88648
* config/arm/arm.c (arm_option_override_internal): Force
opts->x_inline_asm_unified to true only if TARGET_THUMB2_P.
* gcc.target/arm/pr88648-asm-syntax-unified.c: Add test to
check if -masm-syntax-unified gets applied properly.
redi [Thu, 10 Jan 2019 11:12:00 +0000 (11:12 +0000)]
Include name of test in filesystem-test.XXXXXX filenames
Also fix some tests that were not cleaning up after themselves, as
identified by the change to nonexistent_path.
* testsuite/util/testsuite_fs.h (nonexistent_path): Include name
of the source file containing the caller.
* testsuite/27_io/filesystem/iterators/directory_iterator.cc: Remove
directories created by test.
* testsuite/27_io/filesystem/iterators/recursive_directory_iterator.cc:
Likewise.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Likewise.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.
jakub [Thu, 10 Jan 2019 10:56:56 +0000 (10:56 +0000)]
PR tree-optimization/88775
* include/bits/stl_function.h (greater<_Tp*>::operator(),
less<_Tp*>::operator(), greater_equal<_Tp*>::operator(),
less_equal<_Tp*>::operator()): Use __builtin_is_constant_evaluated
instead of __builtin_constant_p if available. Don't bother with
the pointer comparison in C++11 and earlier.
ian [Wed, 9 Jan 2019 23:38:55 +0000 (23:38 +0000)]
PR go/86343
* go-gcc.cc (Gcc_backend::set_placeholder_struct_type): Go back to
build_distinct_type_copy, but copy the fields so that they have
the right DECL_CONTEXT.
This removes updates the removal date of all deprecations in phobos.
Many of the marked functions have passed their end dates, and are now
absent in upstream.
ebotcazou [Wed, 9 Jan 2019 14:34:20 +0000 (14:34 +0000)]
PR target/84010
* config/sparc/sparc.c (sparc_legitimize_tls_address): Only use Pmode
consistently in TLS address generation and adjust code to the renaming
of patterns. Mark calls to __tls_get_addr as const.
* config/sparc/sparc.md (tgd_hi22): Turn into...
(tgd_hi22<P:mode>): ...this and use Pmode throughout.
(tgd_lo10): Turn into...
(tgd_lo10<P:mode>): ...this and use Pmode throughout.
(tgd_add32): Merge into...
(tgd_add64): Likewise.
(tgd_add<P:mode>): ...this and use Pmode throughout.
(tldm_hi22): Turn into...
(tldm_hi22<P:mode>): ...this and use Pmode throughout.
(tldm_lo10): Turn into...
(tldm_lo10<P:mode>): ...this and use Pmode throughout.
(tldm_add32): Merge into...
(tldm_add64): Likewise.
(tldm_add<P:mode>): ...this and use Pmode throughout.
(tldm_call32): Merge into...
(tldm_call64): Likewise.
(tldm_call<P:mode>): ...this and use Pmode throughout.
(tldo_hix22): Turn into...
(tldo_hix22<P:mode>): ...this and use Pmode throughout.
(tldo_lox10): Turn into...
(tldo_lox10<P:mode>): ...this and use Pmode throughout.
(tldo_add32): Merge into...
(tldo_add64): Likewise.
(tldo_add<P:mode>): ...this and use Pmode throughout.
(tie_hi22): Turn into...
(tie_hi22<P:mode>): ...this and use Pmode throughout.
(tie_lo10): Turn into...
(tie_lo10<P:mode>): ...this and use Pmode throughout.
(tie_ld64): Use DImode throughout.
(tie_add32): Merge into...
(tie_add64): Likewise.
(tie_add<P:mode>): ...this and use Pmode throughout.
(tle_hix22_sp32): Merge into...
(tle_hix22_sp64): Likewise.
(tle_hix22<P:mode>): ...this and use Pmode throughout.
(tle_lox22_sp32): Merge into...
(tle_lox22_sp64): Likewise.
(tle_lox22<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub_sp32): Merge into...
(*tldo_ldub_sp64): Likewise.
(*tldo_ldub<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub1_sp32): Merge into...
(*tldo_ldub1_sp64): Likewise.
(*tldo_ldub1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub2_sp32): Merge into...
(*tldo_ldub2_sp64): Likewise.
(*tldo_ldub2<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsb1_sp32): Merge into...
(*tldo_ldsb1_sp64): Likewise.
(*tldo_ldsb1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsb2_sp32): Merge into...
(*tldo_ldsb2_sp64): Likewise.
(*tldo_ldsb2<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub3_sp64): Use DImode throughout.
(*tldo_ldsb3_sp64): Likewise.
(*tldo_lduh_sp32): Merge into...
(*tldo_lduh_sp64): Likewise.
(*tldo_lduh<P:mode>): ...this and use Pmode throughout.
(*tldo_lduh1_sp32): Merge into...
(*tldo_lduh1_sp64): Likewise.
(*tldo_lduh1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsh1_sp32): Merge into...
(*tldo_ldsh1_sp64): Likewise.
(*tldo_ldsh1<P:mode>): ...this and use Pmode throughout.
(*tldo_lduh2_sp64): Use DImode throughout.
(*tldo_ldsh2_sp64): Likewise.
(*tldo_lduw_sp32): Merge into...
(*tldo_lduw_sp64): Likewise.
(*tldo_lduw<P:mode>): ...this and use Pmode throughout.
(*tldo_lduw1_sp64): Use DImode throughout.
(*tldo_ldsw1_sp64): Likewise.
(*tldo_ldx_sp64): Likewise.
(*tldo_stb_sp32): Merge into...
(*tldo_stb_sp64): Likewise.
(*tldo_stb<P:mode>): ...this and use Pmode throughout.
(*tldo_sth_sp32): Merge into...
(*tldo_sth_sp64): Likewise.
(*tldo_sth<P:mode>): ...this and use Pmode throughout.
(*tldo_stw_sp32): Merge into...
(*tldo_stw_sp64): Likewise.
(*tldo_stw<P:mode>): ...this and use Pmode throughout.
(*tldo_stx_sp64): Use DImode throughout.
sudi [Wed, 9 Jan 2019 14:32:06 +0000 (14:32 +0000)]
[AArch64, 6/6] Enable BTI: Add configure option.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch is adding a new configure option for enabling BTI and
Return Address Signing by default.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.c (aarch64_override_options): Add case to
check configure option to set BTI and Return Address Signing.
* configure.ac: Add --enable-standard-branch-protection and
--disable-standard-branch-protection.
* configure: Regenerated.
* doc/install.texi: Document the same.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: Update test to not add command line
option when configure with bti.
* gcc.target/aarch64/bti-2.c: Likewise.
* lib/target-supports.exp
(check_effective_target_default_branch_protection):
Add configure check for --enable-standard-branch-protection.
sudi [Wed, 9 Jan 2019 14:21:22 +0000 (14:21 +0000)]
[AArch64, 5/6] Enable BTI : Add new pass for BTI.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch adds a new pass called "bti" which is triggered by the command
line argument -mbranch-protection whenever "bti" is turned on.
The pass iterates through the instructions and adds appropriated BTI
instructions based on the following:
* Add a new "BTI C" at the beginning of a function, unless its already
protected by a "PACIASP". We exempt the functions that are only called
directly.
* Add a new "BTI J" for every target of an indirect jump, jump table
targets, non-local goto targets or labels that might be referenced by
variables, constant pools, etc (NOTE_INSN_DELETED_LABEL).
Since we have already changed the use of indirect tail calls to only x16 and
x17, we do not have to use "BTI JC".
(check patch 3/6).
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
if bti is enabled.
* config/aarch64/aarch64-bti-insert.c: New file.
* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
pass.
* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
new bti pass.
* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: New test.
* gcc.target/aarch64/bti-2.c: New test.
* gcc.target/aarch64/bti-3.c: New test.
* lib/target-supports.exp
(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.
sudi [Wed, 9 Jan 2019 14:14:28 +0000 (14:14 +0000)]
[AArch64, 4/6] Enable BTI: Add new <type> to -mbranch-protection.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This pass updates the CLI of -mbranch-protection to add "bti" as a new
type of branch protection and also add it its definition of "none" and
"standard". The option does not really do anything functional.
The functional changes are in the next patch. I am initializing the target
variable aarch64_enable_bti to 2 since I am also adding a configure option
in a later patch and a value different from 0 and 1 would help identify if its
already been updated.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
* config/aarch64/aarch64.c (aarch64_handle_no_branch_protection):
Disable bti for -mbranch-protection=none.
(aarch64_handle_standard_branch_protection): Enable bti for
-mbranch-protection=standard.
(aarch64_handle_bti_protection): Enable bti for "bti" in the string to
-mbranch-protection.
(aarch64_bti_enabled): Check if bti is enabled.
* config/aarch64/aarch64.opt: Declare target variable.
* doc/invoke.texi: Add bti to the -mbranch-protection documentation.
sudi [Wed, 9 Jan 2019 14:10:58 +0000 (14:10 +0000)]
[AArch64, 3/6] Restrict indirect tail calls to x16 and x17
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch changes the registers that are allowed for indirect tail calls.
We are choosing to restrict these to only x16 or x17.
Indirect tail calls are special in a way that they convert a call statement
(BLR instruction) to a jump statement (BR instruction). For the best possible
use of Branch Target Identification Mechanism, we would like to place a
"BTI C" (call) at the beginning of the function which is only
compatible with BLRs and BR X16/X17. In order to make indirect tail calls
compatible with this scenario, we are restricting the TAILCALL_ADDR_REGS.
In order to use x16/x17 for this purpose, we also had to change the use
of these registers in the epilogue/prologue handling. For this purpose
we are now using x12 and x13 named as EP0_REGNUM and EP1_REGNUM as
scratch registers for epilogue and prologue.
*** gcc/ChangeLog***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): Use new
epilogue/prologue scratch registers EP0_REGNUM and EP1_REGNUM.
(aarch64_expand_epilogue): Likewise.
(aarch64_output_mi_thunk): Likewise
* config/aarch64/aarch64.h (REG_CLASS_CONTENTS): Change
TAILCALL_ADDR_REGS to x16 and x17.
* config/aarch64/aarch64.md: Define EP0_REGNUM and EP1_REGNUM.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/test_frame_17.c: Update to check for EP0_REGNUM
instead of IP0_REGNUM and add test case.
sudi [Wed, 9 Jan 2019 14:08:01 +0000 (14:08 +0000)]
[AArch64, 2/6] Add new arch command line feaures from ARMv8.5-A
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch add all the command line feature that are added by ARMv8.5.
Optional extensions to armv8.5-a:
+rng : Random number Generation Instructions.
+memtag : Memory Tagging Extension.
ARMv8.5-A features that are optional to older arch:
+sb : Speculation barrier instruction.
+ssbs: Speculative Store Bypass Safe instruction.
+predres: Execution and Data Prediction Restriction instructions.
All of the above only effect the assembler and have already gone in the
trunk of binutils.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-option-extensions.def: Define
AARCH64_OPT_EXTENSION for memtag, rng, sb, ssbs and predres.
* gcc/config/aarch64/aarch64.h (AARCH64_FL_RNG): New.
(AARCH64_FL_MEMTAG, ARCH64_FL_SB, AARCH64_FL_SSBS): New.
(AARCH64_FL_PREDRES): New.
(AARCH64_FL_FOR_ARCH8_5): Add AARCH64_FL_SB, AARCH64_FL_SSBS and
AARCH64_FL_PREDRES by default.
* gcc/doc/invoke.texi: Document rng, memtag, sb, ssbs and predres.
* gcc.target/aarch64/sve/copysign_1.c: New test for SVE vectorized
copysign.
* gcc.target/aarch64/sve/copysign_1_run.c: Likewise.
* gcc.target/aarch64/sve/xorsign_1.c: New test for SVE vectorized
xorsign.
* gcc.target/aarch64/sve/xorsign_1_run.c: Likewise.
redi [Wed, 9 Jan 2019 10:46:52 +0000 (10:46 +0000)]
Fix failing prettyprinter test
The failure for "p2" went unnoticed due to the pre-existing failures for
variables with similar names, like "p" and "q". This fixes the failure,
and gives the filesystem::path variables better names.
* testsuite/libstdc++-prettyprinters/cxx17.cc: Fix expected output
for filesystem::path. Give variables more distinctive names.
The IBM128 long double format isn't foldable in constant expressions, so
conditionally skip the std::complex<long double> cases when they'll
fail.
PR libstdc++/88204
* testsuite/26_numerics/complex/operators/more_constexpr.cc: Do not
test std::complex<long double> if long double format is IBM128.
* testsuite/26_numerics/complex/requirements/more_constexpr.cc:
Likewise.
vries [Wed, 9 Jan 2019 00:07:55 +0000 (00:07 +0000)]
[libgomp, testsuite, openacc] Don't use const int for dimensions
Const int is handled differently at -O0 for -xc and -xc++, which can cause noise
in testsuite/libgomp.oacc-c-c++-common test-cases (which are both run for c and
c++) if const int is used for launch dimensions.
vries [Wed, 9 Jan 2019 00:07:45 +0000 (00:07 +0000)]
[nvptx, libgomp] Don't launch with num_workers == 0
When using a compiler build with:
...
+#define PTX_DEFAULT_VECTOR_LENGTH PTX_CTA_SIZE
+#define PTX_MAX_VECTOR_LENGTH PTX_CTA_SIZE
...
and running the libgomp testsuite, we run into an execution failure in
parallel-loop-1.c, due to a cuda launch failure:
...
nvptx_exec: kernel f6_none_none$_omp_fn$0: launch gangs=480, workers=0, \
vectors=1024
libgomp: cuLaunchKernel error: invalid argument
...
because workers == 0.
The workers variable is set to 0 here in nvptx_exec:
...
workers = blocks / actual_vectors;
...
because actual_vectors is 1024, and blocks is 768:
...
cuOccupancyMaxPotentialBlockSize: grid = 10, block = 768
...
Fix this by ensuring that workers is at least one.
2019-01-09 Tom de Vries <tdevries@suse.de>
* plugin/plugin-nvptx.c (nvptx_exec): Make sure to launch with at least
one worker.
ian [Wed, 9 Jan 2019 00:05:12 +0000 (00:05 +0000)]
compiler: use int type for len & cap in slice value
Slice value expression has backend type a struct of a pointer and
two ints. Make sure the len and cap are converted to int when
creating slice value expression.
redi [Tue, 8 Jan 2019 23:15:49 +0000 (23:15 +0000)]
Pretty printer test fixes and improvements
Test that StdUniquePtrPrinter correctly prints std::unique_ptr objects
using the old layout, prior to the PR libstdc++/77990 changes.
The printer test for a valueless std::variant started to fail because
the PR libstdc++/87431 fix meant it no longer became valueless. Change
the test to use a type that is not trivially copyable, so that the
exception causes it to become valueless.
* testsuite/libstdc++-prettyprinters/compat.cc: Test printer support
for old std::unique_ptr layout.
* testsuite/libstdc++-prettyprinters/cxx17.cc: Fix std::variant test
to become valueless. Add filesystem::path tests.
redi [Tue, 8 Jan 2019 23:00:46 +0000 (23:00 +0000)]
PR libstdc++/87855 fix optional for types with non-trivial copy/move
When the contained value is not trivially copy (or move) constructible
the union's copy (or move) constructor will be deleted, and so the
_Optional_payload delegating constructors are invalid. G++ fails to
diagnose this because it incorrectly performs copy elision in the
delegating constructors. Clang does diagnose it (llvm.org/PR40245).
The solution is to avoid performing any copy (or move) when the
contained value's copy (or move) constructor isn't trivial. Instead the
contained value can be constructed by calling _M_construct. This is OK,
because the relevant constructor doesn't need to be constexpr when the
contained value isn't trivially copy (or move) constructible.
Additionally, this patch removes a lot of code duplication in the
_Optional_payload partial specializations and the _Optional_base partial
specialization, by hoisting it into common base classes.
The Python pretty printer for std::optional needs to be adjusted to
support the new layout. Retain support for the old layout, and add a
test to verify that the support still works.
PR libstdc++/87855
* include/std/optional (_Optional_payload_base): New class template
for common code hoisted from _Optional_payload specializations. Use
a template for the union, to allow a partial specialization for
types with non-trivial destructors. Add constructors for in-place
initialization to the union.
(_Optional_payload(bool, const _Optional_payload&)): Use _M_construct
to perform non-trivial copy construction, instead of relying on
non-standard copy elision in a delegating constructor.
(_Optional_payload(bool, _Optional_payload&&)): Likewise for
non-trivial move construction.
(_Optional_payload): Derive from _Optional_payload_base and use it
for everything except the non-trivial assignment operators, which are
defined as needed.
(_Optional_payload<false, C, M>): Derive from the specialization
_Optional_payload<true, false, false> and add a destructor.
(_Optional_base_impl::_M_destruct, _Optional_base_impl::_M_reset):
Forward to corresponding members of _Optional_payload.
(_Optional_base_impl::_M_is_engaged, _Optional_base_impl::_M_get):
Hoist common members from _Optional_base.
(_Optional_base): Make all members and base class public.
(_Optional_base::_M_get, _Optional_base::_M_is_engaged): Move to
_Optional_base_impl.
* python/libstdcxx/v6/printers.py (StdExpOptionalPrinter): Add
support for new std::optional layout.
* testsuite/libstdc++-prettyprinters/compat.cc: New test.
janus [Tue, 8 Jan 2019 19:29:01 +0000 (19:29 +0000)]
2019-01-08 Janus Weil <janus@gcc.gnu.org>
PR fortran/88047
* class.c (gfc_find_vtab): For polymorphic typespecs, the components of
the class container may not be available (in case of invalid code).
2019-01-08 Janus Weil <janus@gcc.gnu.org>
PR fortran/88047
* gfortran.dg/class_69.f90: New test case.
mpolacek [Tue, 8 Jan 2019 17:37:51 +0000 (17:37 +0000)]
PR c++/88548 - this accepted in static member functions.
* parser.c (cp_debug_parser): Adjust printing of
local_variables_forbidden_p.
(cp_parser_new): Set local_variables_forbidden_p to 0 rather than false.
(cp_parser_primary_expression): When checking
local_variables_forbidden_p, use THIS_FORBIDDEN or
LOCAL_VARS_FORBIDDEN.
(cp_parser_lambda_body): Update the type of
local_variables_forbidden_p. Set it to 0 rather than false.
(cp_parser_condition): Adjust call to cp_parser_declarator.
(cp_parser_explicit_instantiation): Likewise.
(cp_parser_init_declarator): Likewise.
(cp_parser_declarator): New parameter. Use it.
(cp_parser_direct_declarator): New parameter. Use it to set
local_variables_forbidden_p. Adjust call to cp_parser_declarator.
(cp_parser_type_id_1): Adjust call to cp_parser_declarator.
(cp_parser_parameter_declaration): Likewise.
(cp_parser_default_argument): Update the type of
local_variables_forbidden_p. Set it to LOCAL_VARS_AND_THIS_FORBIDDEN
rather than true.
(cp_parser_member_declaration): Tell cp_parser_declarator if we saw
'static' or 'friend'.
(cp_parser_exception_declaration): Adjust call to cp_parser_declarator.
(cp_parser_late_parsing_default_args): Update the type of
local_variables_forbidden_p. Set it to LOCAL_VARS_AND_THIS_FORBIDDEN
rather than true.
(cp_parser_cache_defarg): Adjust call to cp_parser_declarator.
(cp_parser_objc_class_ivars): Likewise.
(cp_parser_objc_struct_declaration): Likewise.
(cp_parser_omp_for_loop_init): Likewise.
* parser.h (cp_parser): Change the type of local_variables_forbidden_p
to unsigned char.
(LOCAL_VARS_FORBIDDEN, LOCAL_VARS_AND_THIS_FORBIDDEN, THIS_FORBIDDEN):
Define.
marxin [Tue, 8 Jan 2019 14:45:28 +0000 (14:45 +0000)]
Use proper type in linear transformation in tree-switch-conversion (PR tree-optimization/88753).
2019-01-08 Martin Liska <mliska@suse.cz>
PR tree-optimization/88753
* tree-switch-conversion.c (switch_conversion::build_one_array):
Come up with local variable constructor. Convert first to
type of constructor values.
2019-01-08 Martin Liska <mliska@suse.cz>
PR tree-optimization/88753
* gcc.dg/tree-ssa/pr88753.c: New test.
redi [Tue, 8 Jan 2019 13:25:19 +0000 (13:25 +0000)]
PR libstdc++/88066 use <> for includes not ""
Using #include "..." to include a header in the same directory fails if
the user compiles with -I-, so always use something like <bits/...> for
internal headers.
I haven't added tests for this, because dg-options adds options to the
end, and the position of -I- matters (if it's at the end then the tests
won't find any headers in the build tree, as they're specified by -I
options earlier in the flags). It's been manually tested though.
PR libstdc++/88066
* include/bits/locale_conv.h: Use <> for includes not "".
* include/ext/random: Likewise.
* include/ext/vstring.h: Likewise.
rguenth [Tue, 8 Jan 2019 13:05:47 +0000 (13:05 +0000)]
2019-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/86554
* tree-ssa-sccvn.c (eliminate_dom_walker, rpo_elim,
rpo_avail): Move earlier.
(visit_nary_op): When value-numbering to expressions
with different overflow behavior make sure there's an
available expression on the path.
* gcc.dg/torture/pr86554-1.c: New testcase.
* gcc.dg/torture/pr86554-2.c: Likewise.
projects / thirdparty / gcc.git / log
