QMC driver requires fsl_soc.h to use function get_immrbase().
This header is provided by powerpc architecture and the functions
it declares are defined only when FSL_SOC is selected.
This dependency tentatively ensure that FSL_SOC is there when doing a
COMPILE_TEST.
CPM1 is only selected by PPC_8xx and cannot be selected manually.
CPM1 selects FSL_SOC
QUICC_ENGINE on the other hand can be selected by ARM or ARM64 which
doesn't select FSL_SOC. QUICC_ENGINE can also be selected with just
COMPILE_TEST.
It is therefore possible to end up with CPM_QMC selected
without FSL_SOC.
So fix it by making it depend on FSL_SOC at all time.
The rest of the above dependency is the same as the one for CPM_TSA on
which CPM_QMC also depends, so it can go away, leaving only a simple
dependency on FSL_SOC.
Merge tag 'soc_fsl-6.12-2' of https://github.com/chleroy/linux into soc/drivers
- A series from Hervé Codina that bring support for the newer version
of QMC (QUICC Multi-channel Controller) and TSA (Time Slots Assigner)
found on MPC 83xx micro-controllers.
- Misc changes for qbman freescale drivers for removing a redundant
warning and using iommu_paging_domain_alloc()
* tag 'soc_fsl-6.12-2' of https://github.com/chleroy/linux: (38 commits)
soc: fsl: qbman: Remove redundant warnings
soc: fsl: qbman: Use iommu_paging_domain_alloc()
MAINTAINERS: Add QE files related to the Freescale QMC controller
soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware
soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation
soc: fsl: qe: Add missing PUSHSCHED command
soc: fsl: qe: Add resource-managed muram allocators
soc: fsl: cpm1: qmc: Introduce qmc_version
soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC
soc: fsl: cpm1: qmc: Handle RPACK initialization
soc: fsl: cpm1: qmc: Rename qmc_chan_command()
soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version
soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version
soc: fsl: cpm1: qmc: Re-order probe() operations
soc: fsl: cpm1: qmc: Introduce qmc_data structure
dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) QMC controller
soc: fsl: cpm1: qmc: Add missing spinlock comment
soc: fsl: cpm1: qmc: Fix 'transmiter' typo
soc: fsl: cpm1: qmc: Remove unneeded parenthesis
soc: fsl: cpm1: qmc: Fix blank line and spaces
...
================
This series add support for the QUICC Engine (QE) version of TSA and QMC
components.
CPM1 version is already supported and, as the QE version of those
component are pretty similar to the CPM1 version, the series extend
the already existing drivers to support for the QE version.
The TSA and QMC components are tightly coupled and so the series
provides modifications on both components.
Of course, this series can be split if it is needed. Let me know.
The series is composed of:
- Patches 1 and 2: Fixes related to TRNSYNC in the QMC driver
- Patches 3..6: Fixes of checkpatch detected issues in the TSA driver
- Patch 7: The QE TSA device-tree binding
- Patches 8..13: TSA driver preparations for adding support for QE
- Patches 14 and 15: The support for QE in TSA + MAINTAINERS update
- Patch 16: A TSA API improvement needed for the QE QMC driver
- Patch 17: A clarification in the QE QMC driver
- Patches 18..22: Fixes of checkpatch detected issues in the QMC driver
- Patch 23: The QE QMC device-tree binding
- Patches 24..31: QMC driver preparations for adding support for QE
- Patches 32 and 33: Missing features additions in QE code
- Patches 34..36: The QMC support for QE in QMC + MAINTAINERS update
Compared to the previous iteration, this v2 series updates device-tree
bindings and fixes issues detected by kernel test robots.
Related to the QE QMC device-tree binding, I kept the unit address in
decimal and the 3 compatible strings.
================
Xiaolei Wang [Fri, 2 Aug 2024 02:16:51 +0000 (10:16 +0800)]
soc: fsl: qbman: Remove redundant warnings
This warning was added by commit 07f86917a450 ("soc/fsl/qbman: Use
shared-dma-pool for QMan private memory allocations") but
RESERVEDMEM_OF_DECLARE usage was removed by
commit 3e62273ac63a ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE
usage") . For non-popwerpc platforms, such as ls1043, this warning
is redundant. ls1043 itself uses shared-dma-mem.
Fixes: 3e62273ac63a ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage") Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com> Link: https://lore.kernel.org/r/20240802021651.3854295-1-xiaolei.wang@windriver.com
[chleroy: Added more details in commit message] Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Herve Codina [Thu, 8 Aug 2024 07:11:27 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Herve Codina [Thu, 8 Aug 2024 07:11:26 +0000 (09:11 +0200)]
soc: fsl: qe: Add missing PUSHSCHED command
The PUSHSCHED command is missing in the QE header file.
This command is supported on MPC8321 and is used to modify the start
address for the task running on a given peripheral. It is needed for the
QMC in order to perform the re-initialization procedure and so, ensure
the correct UCC setup in that case.
Simply add the missing command in the commands list available in the QE
header file.
Introduce devm_cpm_muram_alloc() and devm_cpm_muram_alloc_fixed(), the
resource-managed version of cpm_muram_alloc and cpm_muram_alloc_fixed().
These resource-managed versions simplify the user avoiding the need to
call cpm_muram_free(). Indeed, the allocated area returned by these
functions will be automatically freed on driver detach.
Herve Codina [Thu, 8 Aug 2024 07:11:24 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Introduce qmc_version
Current code handles the CPM1 version of QMC.
In order to prepare the support for the QUICC Engine (QE) version of
QMC, introduce qmc_version to identify versions. This will enable the
code to make the distinction between several QMC implementations.
Herve Codina [Thu, 8 Aug 2024 07:11:23 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC
Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the mode bitfield are different and the
0x0A value defined for the QMC mode is CPM1 specific.
In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.
Herve Codina [Thu, 8 Aug 2024 07:11:20 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version
Current code handles the CPM1 version of QMC and initialize the QMC used
SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication
Controllers) instead of the SCC (Serial Communication Controllers) used
in the CPM1 version. These controllers serve the same purpose and are
used in the same way but their inializations are slightly different.
In order to prepare the support for QE version of QMC, introduce
qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in
CPM1) and isolate the CPM1 specific SCC initialization in a specific
function.
Also introduce qmc_exit_xcc() for consistency to revert operations done
in qmc_init_xcc().
Herve Codina [Thu, 8 Aug 2024 07:11:19 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version
Current code handles the CPM1 version of QMC. Resources initialisations
(i.e. retrieving base addresses and offsets of different parts) will
be slightly different in the QUICC Engine (QE) version. Indeed, in QE
version, some resources need to be allocated and are no more "staticaly"
defined.
In order to prepare the support for QE version, introduce
qmc_init_resource() to initialize those resources and isolate the CPM1
specific operations in a specific function.
Herve Codina [Thu, 8 Aug 2024 07:11:18 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Re-order probe() operations
Current code handles CPM1 version of QMC. In the QUICC Engine (QE)
version, some operations done at probe() need to be done in a different
order.
In order to prepare the support for the QE version, changed the sequence
of operation done at probe():
- Retrieve the tsa_serial earlier, before initializing resources.
- Group SCC initialisation and do this initialization when it is really
needed in the probe() sequence.
Having the QE compatible sequence in the CPM1 version does not lead to
any issue and works correctly without any regressions.
Herve Codina [Thu, 8 Aug 2024 07:11:17 +0000 (09:11 +0200)]
soc: fsl: cpm1: qmc: Introduce qmc_data structure
Current code handles CPM1 version of QMC. Some hardcoded values are used
several times to initialize the QMC state machine. In the QUICC Engine
(QE) version of QMC, these values are different.
In order to prepare the support for the QE version of QMC and avoid the
copy of the hardcoded values, introduce the qmc_data structure to define
these version specific values.
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Last point, the QE QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
TSA consumers in CPM1 implementation don't need to know about the serial
device number used by the TSA component. In QUICC Engine implementation,
this information is needed.
Improve the TSA API with tsa_serial_get_num() in order to provide this
information.
Herve Codina [Thu, 8 Aug 2024 07:11:07 +0000 (09:11 +0200)]
soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementation
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers).
Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs
instead of 2 and allows to configure the logic level of sync signals.
At a lower level, compared against CPM TSA implementation, some
registers are slightly different even if same features are present.
Herve Codina [Thu, 8 Aug 2024 07:11:06 +0000 (09:11 +0200)]
soc: fsl: cpm1: tsa: Introduce tsa_version
Current code handles CPM1 version of TSA.
In order to prepare the support for the QUICC Engine (QE) version of
TSA, introduce tsa_version to identify versions. This will enable the
code to make the distinction between several TSA implementations.
Herve Codina [Thu, 8 Aug 2024 07:11:05 +0000 (09:11 +0200)]
soc: fsl: cpm1: tsa: Isolate specific CPM1 part from tsa_serial_{dis}connect()
Current code handles the CPM1 version of TSA. Connecting and
disconnecting the SCC to/from the TSA consists in handling SICR register
which is CPM1 specific. The connection and disconnection operation in
the QUICC Engine (QE) version are slightly different.
In order to prepare the support for the QE version, clearly identify
SICR register as specific to CPM1 and isolate its handling done in
connect and disconnect functions.
Herve Codina [Thu, 8 Aug 2024 07:11:04 +0000 (09:11 +0200)]
soc: fsl: cpm1: tsa: Introduce tsa_setup() and its CPM1 compatible version
Current code handles the CPM1 version of TSA. Setting up TSA consists in
handling SIMODE and SIGMR registers. These registers are CPM1 specific.
Setting up the QUICC Engine (QE) version of TSA is slightly different.
In order to prepare the support for QE version, clearly identify these
registers as CPM1 compatible and isolate their handling in a CPM1
specific function.
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Herve Codina [Thu, 8 Aug 2024 07:10:58 +0000 (09:10 +0200)]
soc: fsl: cpm1: tsa: Fix blank line and spaces
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: spaces preferred around that '/' (ctx:VxV)
CHECK: spaces preferred around that '+' (ctx:VxV)
CHECK: spaces preferred around that '-' (ctx:VxV)
Herve Codina [Thu, 8 Aug 2024 07:10:54 +0000 (09:10 +0200)]
soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent mode
The TRNSYNC feature is available (and enabled) only in transparent mode.
Since commit 7cc9bda9c163 ("soc: fsl: cpm1: qmc: Handle timeslot entries
at channel start() and stop()") TRNSYNC register is updated in
transparent and hdlc mode. In hdlc mode, the address of the TRNSYNC
register is used by the QMC for other internal purpose. Even if no weird
results were observed in hdlc mode, touching this register in this mode
is wrong.
Merge tag 'tegra-for-6.12-firmware' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
firmware: tegra: Changes for v6.12-rc1
The changes in this set remove some unused code and simplify error paths
using scoped helpers.
* tag 'tegra-for-6.12-firmware' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
firmware: tegra: bpmp: Use scoped device node handling to simplify error paths
firmware: tegra: bpmp: Drop unused mbox_client_to_bpmp()
Merge tag 'scmi-updates-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm SCMI updates for v6.12
Few main features include:
1. SCMI transport as stand-alone drivers
Currently the SCMI transport layer is being built embedded into in
the core SCMI stack. Some of these transports, despite being currently
part of the main SCMI module, are indeed also registered with different
subsystems like optee or virtio, and actively probed also by those.
This leads to a few awkward and convoluted tricks to properly handle
such interactions at boot time in the SCMI stack.
This change adds the new logic to the core SCMI stack so that each
existing transport is transitioned to be a standi-alone driver. With
that all the probe deferral and awkward retries between the SCMI
core stack and the transports has been removed, since no more needed.
2. Support for obtaining transport descriptors from the devicetree
SCMI platform firmwares might have different designs depending on
the platform. Some of the transport descriptors rely on such design.
E.g. the maximum receive channel timeout value might vary depending
on the specific underlying hardware and firmware design choices.
This change adds support for max-rx-timeout-ms property to describe
the transport needs of a specific platform design. It will be extended
in the future to obtain other such hardware/firmware dependent
transport related descriptors.
3. NXP i.MX95 specific SCMI vendor protocol extensions
SCMI specification allows vendor or platform-specific extensions to
the interface. NXP i.MX95 System Manager(SM) that implements SCMI
extends the interface to implement couple of vendor/platform specific
protocol, namely:
a. Battery Backed Module(BBM) Protocol
This protocol is intended provide access to the battery-backed
module. This contains persistent storage (GPR), an RTC, and the
ON/OFF button. The protocol can also provide access to similar
functions implemented via external board components.
b. MISC Protocol for misc settings
This includes controls that are misc settings/actions that must
be exposed from the SM to agents. They are device specific and
are usually define to access bit fields in various mix block
control modules, IOMUX_GPR, and other GPR/CSR owned by the SM.
4. SCMI debug/tracking metrics
Since SCMI involves interaction with the entity(software, firmware
and/or hardware) providing services or features, it is quite useful
to track certain metrics(for pure debugging purposes) like how many
messages were sent or received, were there any failures, what kind
of failures, ..etc. This feature adds support for the same via debugfs.
Apart from these main features, there are some miscellaneous updates, fixes
and cleanups.
* tag 'scmi-updates-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (31 commits)
rtc: support i.MX95 BBM RTC
input: keyboard: support i.MX95 BBM module
firmware: imx: Add i.MX95 MISC driver
firmware: arm_scmi: Add initial support for i.MX MISC protocol
firmware: arm_scmi: Add initial support for i.MX BBM protocol
firmware: arm_scmi: Add NXP i.MX95 SCMI documentation
dt-bindings: firmware: Add i.MX95 SCMI Extension protocol
firmware: arm_scmi: Replace comma with the semicolon
firmware: arm_scmi: Replace the use of of_node_put() to __free(device_node)
firmware: arm_scmi: Fix trivial whitespace/coding style issues
firmware: arm_scmi: Use max-rx-timeout-ms from devicetree
dt-bindings: firmware: arm,scmi: Introduce property max-rx-timeout-ms
firmware: arm_scmi: Remove const from transport descriptors
firmware: arm_scmi: Simplify with scoped for each OF child loop
firmware: arm_scmi: Update various protocols versions
firmware: arm_scmi: Remove legacy transport-layer code
firmware: arm_scmi: Make VirtIO transport a standalone driver
firmware: arm_scmi: Make OPTEE transport a standalone driver
firmware: arm_scmi: Make SMC transport a standalone driver
firmware: arm_scmi: Make MBOX transport a standalone driver
...
Merge tag 'ffa-updates-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm FF-A updates for v6.12
The main addition this time is the basic support for FF-A v1.2
specification which includes support for newly added:
1. FFA_MSG_SEND_DIRECT_{REQ,RESP}2
2. FFA_PARTITION_INFO_GET_REGS
3. FFA_YIELD support in direct messaging
Apart from these, the changes include support to fetch the Rx/Tx buffer
size using FFA_FEATURES, addition of the FF-A FIDs for v1.2 and some
coding style cleanups.
* tag 'ffa-updates-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_ffa: Fetch the Rx/Tx buffer size using ffa_features()
firmware: arm_ffa: Add support for FFA_YIELD in direct messaging
firmware: arm_ffa: Add support for FFA_MSG_SEND_DIRECT_{REQ,RESP}2
firmware: arm_ffa: Add support for FFA_PARTITION_INFO_GET_REGS
firmware: arm_ffa: Move the function ffa_features() earlier
firmware: arm_ffa: Update the FF-A command list with v1.2 additions
firmware: arm_ffa: Some coding style fixes
Merge tag 'memory-controller-drv-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
Memory controller drivers for v6.12
1. Tegra210 EMC: Driver refactoring and rework.
2. Tegra186 EMC: Drop unused function.
3. FSL WEIM: Correct fsl,weim-cs-timing property to properly validate it
as an array.
4. TI AEMIF: Drop platform data support.
5. TI EMIF: Switch to of_property_read_bool().
6. Several cleanups in multiple drivers: TI AEMIF and EMIF, Tegra
EMC/MC, Atmel EBI, Samsung Exynos5422 DMC, STM32 FMC2 EBI, OMAP GPMC,
PL172 and PL1353 SMC. These are mostly code simplifying around
probe() like using
- devm_clk_get_enabled(),
- dev_err_probe(),
- scoped device node handling (cleanup.h),
- scoped for each OF child loops,
- scoped/guard locks.
* tag 'memory-controller-drv-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (35 commits)
memory: mtk-smi: Use devm_clk_get_enabled()
memory: pl353-smc: simplify with devm_clk_get_enabled()
memory: pl353-smc: simplify with dev_err_probe()
memory: pl172: simplify with devm_clk_get_enabled()
memory: pl172: simplify with dev_err_probe()
memory: omap-gpmc: simplify locking with guard()
memory: emif: simplify locking with guard()
memory: emif: drop unused 'irq_state' member
memory: ti-aemif: Revert "memory: ti-aemif: don't needlessly iterate over child nodes"
memory: ti-aemif: simplify with scoped for each OF child loop
memory: ti-aemif: simplify with dev_err_probe()
memory: tegra30-emc: simplify with scoped for each OF child loop
memory: tegra20-emc: simplify with scoped for each OF child loop
memory: tegra124-emc: simplify with scoped for each OF child loop
memory: tegra-mc: simplify with scoped for each OF child loop
memory: stm32-fmc2-ebi: simplify with dev_err_probe()
memory: stm32-fmc2-ebi: simplify with scoped for each OF child loop
memory: samsung: exynos5422-dmc: use scoped device node handling to simplify error paths
memory: samsung: exynos5422-dmc: simplify dmc->dev usage
memory: atmel-ebi: simplify with scoped for each OF child loop
...
Marek Behún [Sat, 31 Aug 2024 09:20:47 +0000 (11:20 +0200)]
firmware: turris-mox-rwtm: Use container_of() instead of hwrng .priv member
Use container_of() to get driver private structure from hwnrg structure,
instead of the hwrng's .priv member, as suggested by Herbert for another
driver.
Marek Behún [Sat, 31 Aug 2024 09:20:35 +0000 (11:20 +0200)]
firmware: turris-mox-rwtm: Use macro constant instead of hardcoded 4096
The 4096 bytes limit in mox_hwrng_read() is due to the DMA buffer being
allocated to one PAGE_SIZE bytes. Use new local macro constant
RWTM_DMA_BUFFER_SIZE at allocation time and when used in mox_hwrng_read().
Use SZ_4K instead of PAGE_SIZE. Although PAGE_SIZE is never set to a
larger value on Armada 3720, it theoretically could, and this would be a
waste of space.
Enable compile testing for broader build coverage. None of the drivers
use anything from "asm", so code should build everywhere.
CONFIG_PLAT_VERSATILE is being selected by driver dependencies
(CONFIG_ARCH_INTEGRATOR and CONFIG_ARCH_REALVIEW), so directory can be
always added to Makefile targets without impacting other configurations.
Peng Fan [Fri, 23 Aug 2024 09:05:22 +0000 (17:05 +0800)]
rtc: support i.MX95 BBM RTC
The BBM module provides RTC feature. To i.MX95, this module is managed by
System Manager and exported System Control Management Interface(SCMI).
Linux could use i.MX SCMI BBM Extension protocol to use RTC feature.
This driver is to use SCMI interface to get/set RTC.
Peng Fan [Fri, 23 Aug 2024 09:05:23 +0000 (17:05 +0800)]
input: keyboard: support i.MX95 BBM module
The BBM module provides BUTTON feature. To i.MX95, this module
is managed by System Manager and exported using System Management
Control Interface(SCMI). Linux could use i.MX SCMI BBM Extension
protocol to use BUTTON feature.
This driver is to use SCMI interface to enable pwrkey.
Peng Fan [Fri, 23 Aug 2024 09:05:19 +0000 (17:05 +0800)]
firmware: arm_scmi: Add initial support for i.MX MISC protocol
i.MX95 System Manager(SM) firmware includes a SCMI vendor protocol, SCMI
MISC protocol which includes controls that are misc settings/actions that
must be exposed from the SM to agents. They are device specific and are
usually define to access bit fields in various mix block control modules,
IOMUX_GPR, and other General Purpose registers, Control Status Registers
owned by the SM.
Peng Fan [Fri, 23 Aug 2024 09:05:18 +0000 (17:05 +0800)]
firmware: arm_scmi: Add initial support for i.MX BBM protocol
i.MX95 has a battery-backed module(BBM), which has persistent storage
(GPR), an RTC, and the ON/OFF button. The System Manager(SM) firmware
use SCMI vendor protocol(SCMI BBM) to let agent be able to use GPR, RTC
and ON/OFF button.
Add i.MX SCMI Extension protocols bindings for:
- Battery Backed Module(BBM) Protocol
This contains persistent storage (GPR), an RTC, and the ON/OFF button.
The protocol can also provide access to similar functions implemented via
external board components.
- MISC Protocol.
This includes controls that are misc settings/actions that must be
exposed from the SM to agents. They are device specific and are usually
define to access bit fields in various mix block control modules,
IOMUX_GPR, and other GPR/CSR owned by the SM.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Message-Id: <20240823-imx95-bbm-misc-v2-v8-1-e600ed9e9271@nxp.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Sudeep Holla [Tue, 27 Aug 2024 14:38:37 +0000 (15:38 +0100)]
firmware: arm_scmi: Replace the use of of_node_put() to __free(device_node)
Use __free for device_node values, and thus drop calls to of_node_put.
The goal is simplify of_node reference cleanup by using this scope-based
of_node_put() cleanup to simplify function exit handling. When using __free
a resource is allocated within a block, it is automatically freed at the
end of the block.
This cleanup aligns well with the recent change in shmem.c to use __free
instead of explicit of_node_put() calls.
s5p-mfc bindings to json-schema is already merged with
this commit 538af6e5856b ("dt-bindings: media: s5p-mfc:
convert bindings to json-schema"). Remove s5p-mfc.txt
file.
Fixes: 538af6e5856b ("dt-bindings: media: s5p-mfc: convert bindings to json-schema") Signed-off-by: Aakarsh Jain <aakarsh.jain@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240808134432.50073-1-aakarsh.jain@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Rong Qianfeng [Wed, 21 Aug 2024 03:25:57 +0000 (11:25 +0800)]
memory: mtk-smi: Use devm_clk_get_enabled()
Replace devm_clk_get() and clk_prepare_enable() with
devm_clk_get_enabled() in .probe().
Fix the bug of missing clk_disable_unprepare() in .remove() by
using devm_clk_get_enabled() that can disables and unprepares
it automatically on driver detach.
Fixes: 3c8f4ad85c4b ("memory/mediatek: add support for mt2701") Cc: honghui.zhang@mediatek.com Signed-off-by: Rong Qianfeng <rongqianfeng@vivo.com> Reviewed-by: Yong Wu <yong.wu@mediatek.com> Link: https://lore.kernel.org/r/20240821032558.43052-1-rongqianfeng@vivo.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
memory: pl172: simplify with devm_clk_get_enabled()
Use devm_clk_get_enabled() to drop clock prepare/unprepare parts and
make code simpler. Change to dev_err_probe() in handling clk_get_rate()
error to make it even simpler.
Simplify error handling (less gotos) over locks with guard().
The driver used file-scope variable 'irq_state' for storing IRQ state
with spin_lock_irqsave, so move it into respective local scopes. This
should be equivalent, but more readable (less global variables).
The first-level children of the aemif node are not the device nodes (ones
containing the 'compatible' property) but the chip-select nodes which
instead have their own children.
of_platform_populate() will skip such nodes so we must indeed iterate
over the direct children of the aemif node. The problem here is that we
never call of_platform_depopulate() as it takes the root device as
argument. We only have an unpopulated chip-select nodes so we will leak
these devices if any of the calls to of_platform_populate() fails.
I don't have a batter idea right now but my patch was not correct so we
need to revert it. While at it: at least use the scoped variant of the
OF node iterator. Down the line, we should find a better solution to fix
this potential resource leak in error path.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240824080235.56472-1-brgl@bgdev.pl Fixes: 23a641d5c2bc ("memory: ti-aemif: don't needlessly iterate over child nodes") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Alex Bee [Thu, 23 May 2024 18:56:32 +0000 (20:56 +0200)]
soc: rockchip: grf: Set RK3128's vpu main clock
RK3128 has a setting in GRF which selects whether the vpu attached iommu
uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The
default is vepu but some part of the vendor firmware sets it to vdpu.
In order to be independent on whether any of those vendor firmware blobs is
used to boot the SoC reset "vpu main clock" setting to it's default value.
projects / thirdparty / kernel / linux.git / log
