jakub [Sat, 2 Dec 2017 07:58:57 +0000 (07:58 +0000)]
PR tree-optimization/83170
PR tree-optimization/83241
* gimple-ssa-store-merging.c
(imm_store_chain_info::try_coalesce_bswap): Update vuse field from
gimple_vuse (ins_stmt) in case it has changed.
(imm_store_chain_info::output_merged_store): Likewise.
jakub [Sat, 2 Dec 2017 07:54:47 +0000 (07:54 +0000)]
PR target/78643
PR target/80583
* expr.c (get_inner_reference): If DECL_MODE of a non-bitfield
is BLKmode for vector field with vector raw mode, use TYPE_MODE
instead of DECL_MODE.
segher [Sat, 2 Dec 2017 01:33:39 +0000 (01:33 +0000)]
rs6000: Improve fusion assembler output
This improves the output for load and store fusion a little. In most
cases it removes the comment output, because that makes the generated
assembler code hard to read, and equivalent info is available with -dp
anyway. For the vector loads it puts the comment on the second insn,
where it doesn't interfere with other debug comments.
* config/rs6000/rs6000-protos.h (emit_fusion_addis): Remove last two
parameters from prototype.
* config/rs6000/rs6000.c (emit_fusion_addis): Remove last two
parameters. Don't print a comment.
(emit_fusion_gpr_load): Adjust.
(emit_fusion_load_store): Adjust.
* config/rs6000/rs6000.md (*fusion_p9_<mode>_constant): Adjust.
* config/rs6000/vsx.md (two peepholes): Print the "vector load fusion"
comment on the second line.
gcc/testsuite/
* gcc.target/powerpc/fusion.c: Add -dp to options. Adjust the expected
output.
* gcc.target/powerpc/fusion3.c: Ditto.
* gcc.target/powerpc/fusion4.c: Ditto.
segher [Sat, 2 Dec 2017 01:20:08 +0000 (01:20 +0000)]
final: Improve output for -dp and -fverbose-asm
This improves the assembler output (for -dp and -fverbose-asm) in
several ways. It always prints the insn_cost. It does not print
"[length = NN]" but "[c=NN l=NN]", to save space. It does not add one
to the instruction alternative number (everything else starts counting
those at 0, too). And finally, it tries to keep things lined up in
columns a bit better.
* final.c (output_asm_name): Print insn_cost. Shorten output. Print
which_alternative instead of which_alternative + 1.
(output_asm_insn): Print an extra tab if the template is short.
ian [Sat, 2 Dec 2017 00:46:00 +0000 (00:46 +0000)]
runtime: export cgoCheck functions
The functions cgoCheckPointer and cgoCheckResult are called by code
generated by cgo. That means that we need to export them using
go:linkname, as otherwise they are local symbols. The cgo code
currently uses weak references to only call the symbols if they are
defined, which is why it has been working--the cgo code has not been
doing any checks.
ian [Sat, 2 Dec 2017 00:38:54 +0000 (00:38 +0000)]
compiler: avoid GCC middle-end control warnings
GCC has started emitting "control reaches end of non-void function"
warnings. Avoid them for Go by 1) marking the builtin function panic
and the compiler-generated function __go_runtime_error as not
returning and 2) adding a default case to the switch used for select
statements that simply calls __builtin_unreachable.
meissner [Fri, 1 Dec 2017 23:52:20 +0000 (23:52 +0000)]
[gcc]
2017-12-01 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81959
* config/rs6000/rs6000.c (rs6000_address_for_fpconvert): Check for
whether we can allocate pseudos before trying to fix an address.
* config/rs6000/rs6000.md (float_<mode>si2_hw): Make sure the
memory address is indexed or indirect.
(floatuns_<mode>si2_hw2): Likewise.
[gcct/testsuite]
2017-12-01 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81959
* gcc.target/powerpc/pr81959.c: New test.
ian [Fri, 1 Dec 2017 23:12:13 +0000 (23:12 +0000)]
compiler: introduce size threshold for nil checks
Add a new control variable to the Gogo class that stores the size
threshold for nil checks. This value can be used to control the
policy for deciding when a given deference operation needs a check and
when it does not. A size threshold of -1 means that every potentially
faulting dereference needs an explicit check (and branch to error
call). A size threshold of K (where K > 0) means that if the size of
the object being dereferenced is >= K, then we need a check.
libcpp/
* expr.c (interpret_float_suffix): Ignore 'i' in C++14 and up.
(interpret_int_suffix): Likewise.
gcc/cp/
* parser.c (cp_parser_userdef_numeric_literal): Be helpful about
'i' in C++14 and up.
wilco [Fri, 1 Dec 2017 19:54:29 +0000 (19:54 +0000)]
[AArch64] Fix address printing on ILP32
Fix address printing for ILP32. The md file uses 'a' in assembler
templates for symbolic addresses in adrp/add, which end up calling
aarch64_print_operand_address. However in ILP32 these are not valid
memory addresses (being ptr_mode rather than Pmode), so the assert
triggers. Since it is incorrect to use symbols in memory addresses
(besides literal pool accesses), change the 'a' to 'c' in the md file.
Skip one failing test in ILP32 which combines the 'p' modifier with the 'a'
assembler template to fake a memory reference.
gcc/
* config/aarch64/aarch64.md (call_insn): Use %c rather than %a.
(call_value_insn): Likewise.
(sibcall_insn): Likewise.
(sibcall_value_insn): Likewise.
(movsi_aarch64): Likewise.
(movdi_aarch64): Likewise.
(add_losym_): Likewise.
(ldr_got_small_): Likewise.
(ldr_got_small_sidi): Likewise.
(ldr_got_small_28k_): Likewise.
(ldr_got_small_28k_sidi): Likewise.
* config/aarch64/aarch64.c (aarch64_print_address_internal):
Move output_addr_const to symbolic case. Add error check.
testsuite/
* gcc.dg/asm-4.c: Skip on AArch64 with ILP32 as test is incorrect.
redi [Fri, 1 Dec 2017 16:10:31 +0000 (16:10 +0000)]
Fix narrowing conversions in string_view types
* include/experimental/string_view (basic_string_view::_S_compare):
Use value-init so narrowing conversions are not ill-formed.
* include/std/string_view (basic_string_view::_S_compare): Likewise.
krebbel [Fri, 1 Dec 2017 15:33:15 +0000 (15:33 +0000)]
S/390: Split MVC instruction for better forwarding
Certain lengths used in an MVC instruction might disable operand
forwarding. Split MVCs into up to 2 forwardable ones if possible.
gcc/ChangeLog:
2017-12-01 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/predicates.md (plus16_Q_operand): New predicate.
* config/s390/s390.md: Disable MVC merging peephole if it would
disable operand forwarding.
(new peephole2): Split MVCs if it would turn them into up to 2
forwardable MVCs.
pault [Fri, 1 Dec 2017 15:05:55 +0000 (15:05 +0000)]
2017-12-01 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82605
* resolve.c (get_pdt_constructor): Initialize 'cons' to NULL.
(resolve_pdt): Correct typo in prior comment. Emit an error if
any parameters are deferred and the object is neither pointer
nor allocatable.
PR fortran/82606
* decl.c (gfc_get_pdt_instance): Continue if the parameter sym
is not present or has no name. Select the parameter by name
of component, rather than component order. Remove all the other
manipulations of 'tail' when building the pdt instance.
(gfc_match_formal_arglist): Emit and error if a star is picked
up in a PDT decl parameter list.
PR fortran/82622
* trans-array.c (set_loop_bounds): If a GFC_SS_COMPONENT has an
info->end, use it rather than falling through to
gcc_unreachable.
(structure_alloc_comps): Check that param->name is non-null
before comparing with the component name.
* trans-decl.c (gfc_get_symbol_decl): Do not use the static
initializer for PDT symbols.
(gfc_init_default_dt): Do nothing for PDT symbols.
* trans-io.c (transfer_array_component): Parameterized array
components use the descriptor ubound since the shape is not
available.
PR fortran/82719
PR fortran/82720
* trans-expr.c (gfc_conv_component_ref): Do not use the charlen
backend_decl of pdt strings. Use the hidden component instead.
* trans-io.c (transfer_expr): Do not do IO on "hidden" string
lengths. Use the hidden string length for pdt string transfers
by adding it to the se structure. When finished nullify the
se string length.
PR fortran/82866
* decl.c (gfc_match_formal_arglist): If a name is not found or
star is found, while reading a type parameter list, emit an
immediate error.
(gfc_match_derived_decl): On reading a PDT parameter list, on
failure to match call gfc_error_recovery.
PR fortran/82978
* decl.c (build_struct): Character kind defaults to 1, so use
kind_expr whatever is the set value.
(gfc_get_pdt_instance): Ditto.
* trans-array.c (structure_alloc_comps): Copy the expression
for the PDT string length before parameter substitution. Use
this expression for evaluation and free it after use.
2017-12-01 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82605
* gfortran.dg/pdt_4.f03 : Incorporate the new error.
PR fortran/82606
* gfortran.dg/pdt_19.f03 : New test.
* gfortran.dg/pdt_21.f03 : New test.
PR fortran/82622
* gfortran.dg/pdt_20.f03 : New test.
* gfortran.dg/pdt_22.f03 : New test.
PR fortran/82719
PR fortran/82720
* gfortran.dg/pdt_23.f03 : New test.
PR fortran/82866
* gfortran.dg/pdt_24.f03 : New test.
PR fortran/82978
* gfortran.dg/pdt_10.f03 : Correct for error in coding the for
kind 4 component and change the kind check appropriately.
* gfortran.dg/pdt_25.f03 : New test.
rguenth [Fri, 1 Dec 2017 13:33:40 +0000 (13:33 +0000)]
2017-12-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/83232
* tree-vect-data-refs.c (vect_analyze_data_ref_accesses): Fix
detection of same access. Instead of breaking the group here
do not consider the duplicate. Add comment explaining real fix.
jakub [Fri, 1 Dec 2017 08:17:06 +0000 (08:17 +0000)]
PR c/79153
* tree.h (SWITCH_BREAK_LABEL_P): Define.
* gimplify.c (collect_fallthrough_labels): Handle GIMPLE_BIND
starting with a GIMPLE_SWITCH and ending with GIMPLE_LABEL with
SWITCH_BREAK_LABEL_P set on the label.
(gimplify_switch_expr): Set SWITCH_BREAK_LABEL_P on the label
added for default case if it was missing and not all cases covered.
Wrap GIMPLE_SWITCH and the switch_body_seq into a GIMPLE_BIND if
switch_body_seq ends with a GIMPLE_LABEL with SWITCH_BREAK_LABEL_P
set on the label.
* tree-chrec.c (evolution_function_is_univariate_p): Add return true;
to avoid -Wimplicit-fallthrough warning.
* config/i386/i386.c (ix86_expand_special_args_builtin): Add
FALLTHRU comment to avoid -Wimplicit-fallthrough warning.
c/
* c-parser.c: Include tree-iterator.h.
(c_parser_switch_statement): Emit LABEL_EXPR for the break label
into SWITCH_BODY instead of after it and set SWITCH_BREAK_LABEL_P
on it.
cp/
* cp-gimplify.c (genericize_switch_stmt): Emit LABEL_EXPR for the
break label into SWITCH_BODY instead of after it and set
SWITCH_BREAK_LABEL_P on it.
* parser.c (cp_parser_objc_expression): Add FALLTHRU comment to avoid
-Wimplicit-fallthrough warning.
fortran/
* match.c (gfc_match): Add FALLTHRU comment to avoid
-Wimplicit-fallthrough warning.
testsuite/
* c-c++-common/Wimplicit-fallthrough-7.c: Adjust expected warning
line.
* c-c++-common/Wimplicit-fallthrough-36.c: New test.
jakub [Fri, 1 Dec 2017 08:11:56 +0000 (08:11 +0000)]
PR sanitizer/81275
* tree-cfg.c (group_case_labels_stmt): Don't optimize away
C++ FE implicitly added __builtin_unreachable () until -Wreturn-type
is diagnosed.
jakub [Thu, 30 Nov 2017 23:43:10 +0000 (23:43 +0000)]
PR c/83222
* c-tree.h (decl_constant_value_1): Declare.
* c-typeck.c (decl_constant_value_1): New function.
(decl_constant_value): Use it.
* c-fold.c (c_fully_fold_internal): If in_init, use
decl_constant_value_1 instead of decl_constant_value.
PR sanitizer/81697
* asan.c (asan_protect_global): Add new ignore_decl_rtl_set_p
parameter. Return true if ignore_decl_rtl_set_p is true and other
conditions are satisfied.
* asan.h (asan_protect_global): Add new parameter.
* varasm.c (categorize_decl_for_section): Pass true as second parameter
to asan_protect_global calls.
meissner [Thu, 30 Nov 2017 20:52:27 +0000 (20:52 +0000)]
2017-11-30 Michael Meissner <meissner@linux.vnet.ibm.com>
PR libgcc/83112
* config/rs6000/float128-ifunc.c (__addkf3_resolve): Use the
correct type for all ifunc resolvers to silence -Wattribute-alias
warnings. Eliminate the forward declaration of the resolver
functions which is no longer needed.
(__subkf3_resolve): Likewise.
(__mulkf3_resolve): Likewise.
(__divkf3_resolve): Likewise.
(__negkf2_resolve): Likewise.
(__eqkf2_resolve): Likewise.
(__nekf2_resolve): Likewise.
(__gekf2_resolve): Likewise.
(__gtkf2_resolve): Likewise.
(__lekf2_resolve): Likewise.
(__ltkf2_resolve): Likewise.
(__unordkf2_resolve): Likewise.
(__extendsfkf2_resolve): Likewise.
(__extenddfkf2_resolve): Likewise.
(__trunckfsf2_resolve): Likewise.
(__trunckfdf2_resolve): Likewise.
(__fixkfsi_resolve): Likewise.
(__fixkfdi_resolve): Likewise.
(__fixunskfsi_resolve): Likewise.
(__fixunskfdi_resolve): Likewise.
(__floatsikf_resolve): Likewise.
(__floatdikf_resolve): Likewise.
(__floatunsikf_resolve): Likewise.
(__floatundikf_resolve): Likewise.
(__extendkftf2_resolve): Likewise.
(__trunctfkf2_resolve): Likewise.
PR libgcc/83103
* config/rs6000/quad-float128.h (TF): Don't define if long double
is IEEE 128-bit floating point.
(TCtype): Define as either TCmode or KCmode, depending on whether
long double is IEEE 128-bit floating point.
(__mulkc3_sw): Add declarations for software/hardware versions of
complex multiply/divide.
(__divkc3_sw): Likewise.
(__mulkc3_hw): Likewise.
(__divkc3_hw): Likewise.
* config/rs6000/_mulkc3.c (_mulkc3): If we are building ifunc
handlers to switch between using software emulation and hardware
float128 instructions, build the complex multiply/divide functions
for both software and hardware support.
* config/rs6000/_divkc3.c (_divkc3): Likewise.
* config/rs6000/float128-ifunc.c (__mulkc3_resolve): Likewise.
(__divkc3_resolve): Likewise.
(__mulkc3): Likewise.
(__divkc3): Likewise.
* config/rs6000/t-float128-hw (fp128_hardfp_src): Likewise.
(fp128_hw_src): Likewise.
(fp128_hw_static_obj): Likewise.
(fp128_hw_shared_obj): Likewise.
(_mulkc3-hw.c): Create _mulkc3-hw.c and _divkc3-hw.c from
_mulkc3.c and _divkc3.c, changing the function name.
(_divkc3-hw.c): Likewise.
* config/rs6000/t-float128 (clean-float128): Delete _mulkc3-hw.c
and _divkc3-hw.c.
claziss [Thu, 30 Nov 2017 14:42:12 +0000 (14:42 +0000)]
[ARC] Don't allow the last ZOL insn to be in a delay slot.
The ARC ZOL implementation doesn't allow the last instruction to be a
control instruction or part of a delay slot. Thus, we add a note to
the last ZOL instruction which will prevent it to finish into a delay
slot.
* config/arc/arc.c (hwloop_optimize): Prevent the last
ZOL instruction to end into a delay slot.
* config/arc/arc.md (cond_delay_insn): Check if the instruction
can be placed into a delay slot against reg_note.
(in_delay_slot): Likewise.
claziss [Thu, 30 Nov 2017 14:41:49 +0000 (14:41 +0000)]
[ARC] Use TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV.
Sometimes the memory equivalent is not valid due to a large offset.
For example replacing the ap register with its fp/sp-equivalent during
LRA step. To solve this we introduced TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV.
ian [Thu, 30 Nov 2017 05:03:29 +0000 (05:03 +0000)]
compiler: don't make map zero value constant
The map zero value is a common symbol, and it doesn't really make
sense to have a constant common symbol. Current GCC has started to
reject this case, probably as part of the fix for PR 83100.
segher [Wed, 29 Nov 2017 22:42:37 +0000 (22:42 +0000)]
combine: Do not throw away unneeded arms of parallels (PR83156)
The fix for PR82621 makes us not split an I2 if one of the results of
those SETs is unused, since combine does not handle that properly. But
this results in degradation for i386 (or more in general, for any
target that does not have patterns for parallels with an unused result
as a CLOBBER instead of a SET for that result).
This patch instead makes us not split only if one of the results is set
again before I3. That fixes PR83156 and also fixes PR82621.
Unfortunately it undoes the nice optimisations that the previous patch
did on powerpc.
PR rtl-optimization/83156
PR rtl-optimization/82621
* combine.c (try_combine): Don't split an I2 if one of the dests is
set again before I3. Allow unused dests.
segher [Wed, 29 Nov 2017 22:30:24 +0000 (22:30 +0000)]
rs6000: Add second variant of adde
This adds a second variant of the adde insn pattern, this one with the
CA register as the second operand. The existing pattern has it as the
third operand. It would be ideal if RTL was always canonicalised like
that, but it isn't (and that is not trivial), and this is a simple and
harmless patch.
vmakarov [Wed, 29 Nov 2017 22:19:25 +0000 (22:19 +0000)]
2017-11-29 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/80818
* lra.c (collect_non_operand_hard_regs): New arg insn. Pass it
recursively. Use insn code for clobber.
(lra_set_insn_recog_data): Pass the new arg to
collect_non_operand_hard_regs.
(add_regs_to_insn_regno_info): Pass insn instead of uid. Use insn
code for clobber.
(lra_update_insn_regno_info): Pass insn to
add_regs_to_insn_regno_info.
wilson [Wed, 29 Nov 2017 22:14:17 +0000 (22:14 +0000)]
Riscv patterns to optimize away some redundant zero/sign extends.
gcc/
* config/riscv/riscv.c (SINGLE_SHIFT_COST): New.
(riscv_rtx_costs): Case ZERO_EXTRACT, match new pattern, and return
SINGLE_SHIFT_COST. Case LT and ZERO_EXTEND, likewise. Case ASHIFT,
use SINGLE_SHIFT_COST.
* config/riscv/riscv.md (lshrsi3_zero_extend_1): New.
(lshrsi3_zero_extend_2, lshrsi3_zero_extend_3): New.
dmalcolm [Wed, 29 Nov 2017 22:07:32 +0000 (22:07 +0000)]
C++: improve location of static_assert errors
gcc/cp/ChangeLog:
* parser.c (cp_parser_unary_expression): Generate a location for
"noexcept".
(cp_parser_trait_expr): Generate and return a location_t,
converting the return type from tree to cp_expr.
(cp_parser_static_assert): Pass location of the condition to
finish_static_assert, rather than that of the "static_assert"
token, where available.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1y/static_assert3.C: New test case.
libstdc++-v3/ChangeLog:
* testsuite/20_util/duration/literals/range.cc: Update expected
line of a static_assert failure.
danielh [Wed, 29 Nov 2017 15:41:45 +0000 (15:41 +0000)]
[SPARC] Prevent -mfix-ut699 from generating b2bst errata sequences
The sequence
st
fdivd / fsqrtd
std
was generated in some cases with -mfix-ut699 when there was
a st before the div/sqrt. This sequence could trigger the b2bst errata.
Now the following safe sequence is generated instead:
st
nop
fdivd / fsqrtd
std
2017-11-29 Martin Aberg <maberg@gaisler.com>
gcc/
* config/sparc/sparc.md (divdf3_fix): Add NOP and adjust length
to prevent b2bst errata sequence.
(sqrtdf2_fix): Likewise.
danielh [Wed, 29 Nov 2017 15:37:19 +0000 (15:37 +0000)]
[SPARC] Errata workaround for GRLIB-TN-0013
This patch provides a workaround for the errata described in GRLIB-TN-0013.
If the workaround is enabled it will:
* Prevent div and sqrt instructions in the delay slot.
* Insert NOPs to prevent the sequence (div/sqrt) -> (two or three floating
point operations or loads) -> (div/sqrt).
* Not insert NOPs if any of the floating point operations have a dependency
on the destination register of the first (div/sqrt).
* Not insert NOPs if one of the floating point operations is a (div/sqrt).
* Insert NOPs to prevent (div/sqrt) followed by a branch.
It is applicable to GR712RC, UT700, and UT699.
2017-11-29 Daniel Cederman <cederman@gaisler.com>
gcc/
* config/sparc/sparc.c (fpop_reg_depend_p): New function.
(div_sqrt_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0013 errata for
certain LEON3 processors.
(pass_work_around_errata::gate): Also test sparc_fix_lost_divsqrt.
(sparc_option_override): Set sparc_fix_lost_divsqrt appropriately.
* config/sparc/sparc.md (fix_lost_divsqrt): New attribute.
(in_branch_delay): Prevent div and sqrt in delay slot if
fix_lost_divsqrt.
* config/sparc/sparc.opt (sparc_fix_lost_divsqrt): New variable.
danielh [Wed, 29 Nov 2017 15:23:40 +0000 (15:23 +0000)]
[SPARC] Errata workaround for GRLIB-TN-0010
This patch provides a workaround for the errata described in GRLIB-TN-0010.
If the workaround is enabled it will:
* Insert a NOP between load instruction and atomic
instruction (swap, ldstub, casa).
* Insert a NOP at branch target if load in delay slot
and atomic instruction at branch target.
It is applicable to UT700.
2017-11-29 Daniel Cederman <cederman@gaisler.com>
gcc/
* config/sparc/sparc.c (atomic_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0010 errata for
UT700.
* config/sparc/sync.md (atomic_compare_and_swap_leon3_1): Make
instruction referable in atomic_insns_p.
danielh [Wed, 29 Nov 2017 15:15:48 +0000 (15:15 +0000)]
[SPARC] Errata workaround for GRLIB-TN-0012
This patch provides a workaround for the errata described in GRLIB-TN-0012.
If the workaround is enabled it will:
* Prevent any floating-point operation from being placed in the
delay slot of an annulled integer branch.
* Place a NOP at the branch target of an integer branch if it is
a floating-point operation or a floating-point branch.
It is applicable to GR712RC.
2017-11-29 Daniel Cederman <cederman@gaisler.com>
gcc/
* config/sparc/sparc.c (fpop_insn_p): New function.
(sparc_do_work_around_errata): Insert NOP instructions to
prevent sequences that could trigger the TN-0012 errata for
GR712RC.
(pass_work_around_errata::gate): Also test sparc_fix_gr712rc.
* config/sparc/sparc.md (fix_gr712rc): New attribute.
(in_branch_annul_delay): Prevent floating-point instructions
in delay slot of annulled integer branch.
rguenth [Wed, 29 Nov 2017 14:38:06 +0000 (14:38 +0000)]
2017-11-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/83202
* tree-vect-slp.c (scalar_stmts_set_t): New typedef.
(bst_fail): Use it.
(vect_analyze_slp_cost_1): Add visited set, do not account SLP
nodes vectorized to the same stmts multiple times.
(vect_analyze_slp_cost): Allocate a visited set and pass it down.
(vect_analyze_slp_instance): Adjust.
(scalar_stmts_to_slp_tree_map_t): New typedef.
(vect_schedule_slp_instance): Add a map recording the SLP node
representing the vectorized stmts for a set of scalar stmts.
Avoid code-generating redundancies.
(vect_schedule_slp): Allocate map and pass it down.
* gcc.dg/vect/costmodel/x86_64/costmodel-pr83202.c: New testcase.
nathan [Wed, 29 Nov 2017 13:22:44 +0000 (13:22 +0000)]
[PATCH] complex type canonicalization
https://gcc.gnu.org/ml/gcc-patches/2017-11/msg02453.html
PR c++/83817
* tree.c (build_complex_type): Fix canonicalization. Only fill in
type if it is new.
wilco [Wed, 29 Nov 2017 12:22:06 +0000 (12:22 +0000)]
[AArch64] Fix ICE due to store_pair_lanes
The recently added store_pair_lanes causes ICEs in output_operand.
This is due to aarch64_classify_address treating it like a 128-bit STR
rather than a STP. The valid immediate offsets don't fully overlap,
causing it to return false. Eg. offset 264 is a valid 8-byte STP offset
but not a valid 16-byte STR offset since it isn't a multiple of 16.
The original instruction isn't passed in the printing code, so the context
is unclear. The solution is to add a new operand formatting specifier
which is used for LDP/STP instructions like this. This, like the Uml
constraint that applies to store_pair_lanes, uses PARALLEL when calling
aarch64_classify_address so that it knows it is an STP.
Also add the 'z' specifier for future use by load/store pair instructions.
gcc/
* config/aarch64/aarch64.c (aarch64_print_operand): Add new
cases for printing LDP/STP memory addresses.
(aarch64_print_address_internal): Renamed from
aarch64_print_operand_address, added parameter, add Pmode check.
(aarch64_print_ldpstp_address): New function for LDP/STP addresses.
(aarch64_print_operand_address): Indirect to
aarch64_print_address_internal.
* config/aarch64/aarch64-simd.md (store_pair_lanes): Use new
'y' operand output specifier.
projects / thirdparty / gcc.git / log
