Ian Lance Taylor [Fri, 10 Apr 2020 00:42:37 +0000 (17:42 -0700)]
compiler: look up composite literal keys in the global namespace
A composite literal key may not have a global definition, so
Gogo::define_global_names may not see it. In order to correctly
handle the case in which a predeclared identifier is used as a
composite literal key, do an explicit check of the global namespace.
Fritz Reese [Thu, 9 Apr 2020 20:55:44 +0000 (16:55 -0400)]
PR fortran/87923 -- fix ICE when resolving I/O tags and simplify io.c
2020-04-06 Fritz Reese <foreese@gcc.gnu.org>
This patch reorganizes I/O checking code. Checks which were done in the
matching phase which do not affect the match result are moved to the
resolution phase. Checks which were duplicated in both the matching phase
and resolution phase have been reduced to one check in the resolution phase.
Another section of code which used a global async_io_dt flag to check for
and assign the asynchronous attribute to variables used in asynchronous I/O
has been simplified.
Furthermore, this patch improves error reporting and expands test coverage
of I/O tags:
- "TAG must be an initialization expression" reported by io.c
(check_io_constraints) is replaced with an error from expr.c
(gfc_reduce_init_expr) indicating _why_ the expression is not a valid
initialization expression.
- Several distinct error messages regarding the check for scalar
+ character + default kind have been unified to one message reported by
resolve_tag or check_*_constraints.
gcc/fortran/ChangeLog:
2020-04-09 Fritz Reese <foreese@gcc.gnu.org>
PR fortran/87923
* gfortran.h (gfc_resolve_open, gfc_resolve_close): Add
locus parameter.
(gfc_resolve_dt): Add code parameter.
* io.c (async_io_dt, check_char_variable, is_char_type): Removed.
(resolve_tag_format): Add locus to error message regarding
zero-sized array in FORMAT tag.
(check_open_constraints, check_close_constraints): New functions
called at resolution time.
(gfc_match_open, gfc_match_close, match_io): Move checks which don't
affect the match result to new functions check_open_constraints,
check_close_constraints, check_io_constraints.
(gfc_resolve_open, gfc_resolve_close): Call new functions
check_open_constraints, check_close_constraints after all tags have
been independently resolved. Remove duplicate constraints which are
already verified by resolve_tag. Explicitly pass locus to all error
reports.
(compare_to_allowed_values): Add locus parameter and provide
explicit locus all error reports.
(match_open_element, match_close_element, match_file_element,
match_dt_element, match_inquire_element): Remove redundant special
cases for ASYNCHRONOUS and IOMSG tags.
(gfc_resolve_dt): Remove redundant special case for format
expression. Call check_io_constraints, forwarding an I/O list as
the io_code parameter if present.
(check_io_constraints): Change return type to bool. Pass explicit
locus to error reports. Move generic checks after tag-specific
checks, since errors are no longer buffered. Move simplification of
format string to match_io. Remove redundant checks which are
verified by resolve_tag. Remove usage of async_io_dt flag and
explicitly mark symbols used in asynchronous I/O with the
asynchronous attribute.
* resolve.c (resolve_transfer, resolve_fl_namelist): Remove checks
for async_io_dt flag. This is now done in io.c
(check_io_constraints).
(gfc_resolve_code): Pass code locus to gfc_resolve_open,
gfc_resolve_close, gfc_resolve_dt.
Jason Merrill [Thu, 9 Apr 2020 03:59:30 +0000 (23:59 -0400)]
c++: constexpr static data member instantiation [PR94523]
Here due to my recent change to store_init_value we were expanding the
initializer of aw knowing that we were initializing aw. When
cxx_eval_call_expression finished the constructor, it wanted to look up the
value of aw to set TREE_READONLY on it, but we haven't set DECL_INITIAL yet,
so decl_constant_value tried to instantiate the initializer again. And
infinite recursion. Stopped by optimizing the case of asking for the value
of ctx->object, which is ctx->value. It also would have worked to look in
the values hash table, so let's move that up before decl_constant_value as
well.
gcc/cp/ChangeLog
2020-04-09 Jason Merrill <jason@redhat.com>
PR c++/94523
* constexpr.c (cxx_eval_constant_expression) [VAR_DECL]: Look at
ctx->object and ctx->global->values first.
Jonathan Wakely [Thu, 9 Apr 2020 21:24:57 +0000 (22:24 +0100)]
libstdc++: Implement LWG 3324 for [cmp.alg] function objects (LWG 3324)
LWG 3324 changed the [cmp.alg] types to use std::compare_three_way
instead of the <=> operator, but we were still using the old
specification. In order to make the existing tests pass the N::X type
needs to be equality comparable, so that three_way_comparable is
satisfied and compare_three_way can be used.
As part of this change I noticed that the compare_three_way call
operator was unconditionally noexcept, which is incorrect.
* libsupc++/compare (compare_three_way): Fix noexcept-specifier.
(strong_order, weak_order, partial_order): Replace uses of <=> with
compare_three_way function object (LWG 3324).
* testsuite/18_support/comparisons/algorithms/partial_order.cc: Add
equality operator so that X satisfies three_way_comparable.
* testsuite/18_support/comparisons/algorithms/strong_order.cc:
Likewise.
* testsuite/18_support/comparisons/algorithms/weak_order.cc: Likewise.
Jonathan Wakely [Thu, 9 Apr 2020 20:10:32 +0000 (21:10 +0100)]
libstdc++: Add comparison operators to std::unique_ptr
Some more C++20 changes from P1614R2, "The Mothership has Landed".
This includes the proposed resolution for LWG 3426 to fix the three-way
comparison with nullptr_t.
The existing tests for unique_ptr comparisons don't actually check the
results, only that the expressions compile and are convertible to bool.
This also adds a test for the results of those comparisons for C++11 and
up.
* include/bits/unique_ptr.h (operator<=>): Define for C++20.
* testsuite/20_util/default_delete/48631_neg.cc: Adjust dg-error line.
* testsuite/20_util/default_delete/void_neg.cc: Likewise.
* testsuite/20_util/unique_ptr/comparison/compare.cc: New test.
* testsuite/20_util/unique_ptr/comparison/compare_c++20.cc: New test.
MSP430: Indiciate that the epilogue_helper insn does not fallthru
This fixes an ICE in rtl_verify_fallthru, at cfgrtl.c:2970
gcc.c-torture/execute/20071210-1.c for -mcpu=msp430 at -O2
and above.
The epilogue_helper insn was treated as a regular insn which will
fallthru, so when a barrier is emitted after it, RTL verification failed
as rtl_verify_fallthru.
gcc/ChangeLog:
2020-04-09 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/msp430/msp430.c (msp430_expand_epilogue): Use emit_jump_insn
when to emit the epilogue_helper insn.
* config/msp430/msp430.md (epilogue_helper): Add a return insn to the
RTL pattern.
Jakub Jelinek [Thu, 9 Apr 2020 19:21:24 +0000 (21:21 +0200)]
cselib, var-tracking: Improve debug info after the cselib sp tracking changes [PR94495]
On the https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94495#c5
testcase GCC emits worse debug info after the PR92264 cselib.c
changes.
The difference at -O2 -g -dA in the assembly is (when ignoring debug info):
# DEBUG g => [argp]
# DEBUG k => [argp+0x20]
# DEBUG j => [argp+0x18]
# DEBUG a => di
# DEBUG b => si
# DEBUG c => dx
# DEBUG d => cx
# DEBUG h => [argp+0x8]
# DEBUG e => r8
# DEBUG i => [argp+0x10]
# DEBUG f => r9
...
.LVL4:
+ # DEBUG h => [sp+0x10]
+ # DEBUG i => [sp+0x18]
+ # DEBUG j => [sp+0x20]
+ # DEBUG k => [sp+0x28]
# DEBUG c => entry_value
# SUCC: EXIT [always] count:1073741824 (estimated locally)
ret
.LVL5:
+ # DEBUG k => [argp+0x20]
# DEBUG a => bx
# DEBUG b => si
# DEBUG c => dx
# DEBUG d => cx
# DEBUG e => r8
# DEBUG f => r9
+ # DEBUG h => [argp+0x8]
+ # DEBUG i => [argp+0x10]
+ # DEBUG j => [argp+0x18]
This means that before the changes, h, i, j, k could be all expressed
in DW_AT_location directly with DW_OP_fbreg <some_offset>, but now we need
to use a location list, where in the first part of the function and last
part of the function (everything except the ret instruction) we use that
DW_OP_fbreg <some_offset>, but for the single ret instruction we instead
say those values live in something pointed by stack pointer + offset.
It is true, but only because stack pointer + offset is equal to DW_OP_fbreg
<some_offset> at that point.
The var-tracking pass has for !frame_pointer_needed functions code to
canonicalize stack pointer uses in the insns before it hands it over
to cselib to cfa_base_rtx + offset depending on the stack depth at each
point. The problem is that on the last epilogue pop insn (the one right
before ret) the canonicalization is sp = argp - 8 and add_stores records
a MO_VAL_SET operation for that argp - 8 value (which is the
SP_DERIVED_VALUE_P VALUE the cselib changes canonicalize sp based accesses
on) and thus var-tracking from that point onwards tracks that that VALUE
(2:2) now lives in sp. At the end of function it of course needs to forget
it again (or it would need on any changes to sp). But when processing
that uop, we note that the VALUE has changed and anything based on it
changed too, so emit changes for everything. Before that var-tracking
itself doesn't track it in any register, so uses cselib and cselib knows
through the permanent equivs how to compute it using argp (i.e. what
will be DW_OP_fbreg).
The following fix has two parts. One is it detects if cselib can compute
a certain VALUE using the cfa_base_rtx and for such VALUEs doesn't add
the MO_VAL_SET operation, as it is better to express them using cfa_base_rtx
rather than temporarily through something else. And the other is make sure
we reuse in !frame_pointer_needed the single SP_DERIVED_VALUE_P VALUE in
other extended basic blocks too (and other VALUEs) too. This can be done
because we have computed the stack depths at the start of each basic block
in vt_stack_adjustments and while cselib_reset_table is called at the end
of each extended bb, which throws away all hard registers (but the magic
cfa_base_rtx) and so can hint cselib.c at the start of the ebb what VALUE
the sp hard reg has. That means fewer VALUEs during var-tracking and more
importantly that they will all have the cfa_base_rtx + offset equivalency.
I have performed 4 bootstraps+regtests (x86_64-linux and i686-linux,
each with this patch (that is the new cselib + var-tracking variant) and
once with that patch reverted as well as all other cselib.c changes from
this month; once that bootstrapped, I've reapplied the cselib.c changes and
this patch and rebuilt cc1plus, so that the content is comparable, but built
with the pre-Apr 2 cselib.c+var-tracking.c (that is the old cselib one)).
Below are readelf -WS cc1plus | grep debug_ filtered to only have debug
sections whose size actually changed, followed by dwlocstat results on
cc1plus. This shows that there was about 3% shrink in those .debug*
sections for 32-bit and 1% shrink for 64-bit, with minor variable coverage
changes one or the other way that are IMHO insignificant.
PR debug/94495
* cselib.h (cselib_record_sp_cfa_base_equiv,
cselib_sp_derived_value_p): Declare.
* cselib.c (cselib_record_sp_cfa_base_equiv,
cselib_sp_derived_value_p): New functions.
* var-tracking.c (add_stores): Don't record MO_VAL_SET for
cselib_sp_derived_value_p values.
(vt_initialize): Call cselib_record_sp_cfa_base_equiv at the
start of extended basic blocks other than the first one
for !frame_pointer_needed functions.
This patch implements the "arm_sve_vector_bits" attribute, which can be
used to create fixed-length versions of an SVE type while maintaining
their "SVEness". For example, when __ARM_FEATURE_SVE_BITS==256:
The attribute itself is quite simple. However, it means that we now
need to implement the full PCS rules for scalable types, whereas
previously we only needed to handle scalable types that were built
directly into the compiler. See:
2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* doc/sourcebuild.texi (aarch64_sve_hw, aarch64_sve128_hw)
(aarch64_sve256_hw, aarch64_sve512_hw, aarch64_sve1024_hw)
(aarch64_sve2048_hw): Document.
* config/aarch64/aarch64-protos.h
(aarch64_sve::handle_arm_sve_vector_bits_attribute): Declare.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_SVE_VECTOR_OPERATIONS when SVE is enabled.
* config/aarch64/aarch64-sve-builtins.cc (matches_type_p): New
function.
(find_type_suffix_for_scalar_type): Use it instead of comparing
TYPE_MAIN_VARIANTs.
(function_resolver::infer_vector_or_tuple_type): Likewise.
(function_resolver::require_vector_type): Likewise.
(handle_arm_sve_vector_bits_attribute): New function.
* config/aarch64/aarch64.c (pure_scalable_type_info): New class.
(aarch64_attribute_table): Add arm_sve_vector_bits.
(aarch64_return_in_memory_1):
(pure_scalable_type_info::piece::get_rtx): New function.
(pure_scalable_type_info::num_zr): Likewise.
(pure_scalable_type_info::num_pr): Likewise.
(pure_scalable_type_info::get_rtx): Likewise.
(pure_scalable_type_info::analyze): Likewise.
(pure_scalable_type_info::analyze_registers): Likewise.
(pure_scalable_type_info::analyze_array): Likewise.
(pure_scalable_type_info::analyze_record): Likewise.
(pure_scalable_type_info::add_piece): Likewise.
(aarch64_some_values_include_pst_objects_p): Likewise.
(aarch64_returns_value_in_sve_regs_p): Use pure_scalable_type_info
to analyze whether the type is returned in SVE registers.
(aarch64_takes_arguments_in_sve_regs_p): Likwise whether the type
is passed in SVE registers.
(aarch64_pass_by_reference_1): New function, extracted from...
(aarch64_pass_by_reference): ...here. Use pure_scalable_type_info
to analyze whether the type is a pure scalable type and, if so,
whether it should be passed by reference.
(aarch64_return_in_msb): Return false for pure scalable types.
(aarch64_function_value_1): Fold back into...
(aarch64_function_value): ...this function. Use
pure_scalable_type_info to analyze whether the type is a pure
scalable type and, if so, which registers it should use. Handle
types that include pure scalable types but are not themselves
pure scalable types.
(aarch64_return_in_memory_1): New function, split out from...
(aarch64_return_in_memory): ...here. Use pure_scalable_type_info
to analyze whether the type is a pure scalable type and, if so,
whether it should be returned by reference.
(aarch64_layout_arg): Remove orig_mode argument. Use
pure_scalable_type_info to analyze whether the type is a pure
scalable type and, if so, which registers it should use. Handle
types that include pure scalable types but are not themselves
pure scalable types.
(aarch64_function_arg): Update call accordingly.
(aarch64_function_arg_advance): Likewise.
(aarch64_pad_reg_upward): On big-endian targets, return false for
pure scalable types that are smaller than 16 bytes.
(aarch64_member_type_forces_blk): New function.
(aapcs_vfp_sub_candidate): Exit early for built-in SVE types.
(aarch64_short_vector_p): Return false for VECTOR_TYPEs that
correspond to built-in SVE types. Do not rely on a vector mode
if the type includes an pure scalable type. When returning true,
assert that the mode is not an SVE mode.
(aarch64_vfp_is_call_or_return_candidate): Do not check for SVE
built-in types here. When returning true, assert that the type
does not have an SVE mode.
(aarch64_can_change_mode_class): Don't allow anything to change
between a predicate mode and a non-predicate mode. Also don't
allow changes between SVE vector modes and other modes that
might be bigger than 128 bits.
(aarch64_invalid_binary_op): Reject binary operations that mix
SVE and GNU vector types.
(TARGET_MEMBER_TYPE_FORCES_BLK): Define.
aarch64: Add a separate "SVE sizeless type" attribute
It's more convenient for a later patch if sizelessness is represented
separately from "SVEness". "SVEness" is an ABI property that carries
forward into gimple and beyond, and continues to matter during LTO.
Sizelessness is just a frontend restriction and can be ignored after
that.
2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_attribute_table): Add
"SVE sizeless type".
* config/aarch64/aarch64-sve-builtins.cc (make_type_sizeless)
(sizeless_type_p): New functions.
(register_builtin_types): Apply make_type_sizeless to the type.
(register_tuple_type): Likewise.
(verify_type_context): Use sizeless_type_p instead of builin_type_p.
arm_cde.h includes the arm_mve_types.h header, which declares some C++
overloaded functions.
There is a superfluous `extern "C"` statement in arm_cde.h, which
encompasses these functions. This means that if compiling for C++, the
overloaded functions are declared, but are declared without name
mangling. Hence all the function names are the same and we have many
conflicting declarations.
Testing Done:
Regression tested for arm-none-eabi.
gcc/ChangeLog:
2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/arm/arm_cde.h: Remove `extern "C"` when compiling for
C++.
gcc/testsuite/ChangeLog:
2020-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
This is yet another old option that would have been somewhat useful back
before the D front-end implementation was able to support compiling
without the Druntime library.
Now however, -fno-druntime makes the gcstub package redundant, so the
option has been removed, along with the package itself.
The cmse-15.c testcase fails at -Os because ICF means that we
generate
nonsecure2:
b nonsecure0
which is OK, but does not match the currently expected
nonsecure2:
...
bl __gnu_cmse_nonsecure_call
(see https://gcc.gnu.org/pipermail/gcc-patches/2020-April/543190.html)
The test has already different expectations for v8-M and v8.1-M.
This patch uses check-function-bodies to account for the
different possibilities:
- v8-M vs v8.1-M via different target selectors where needed
- code generation variants (-0?) via multiple regexps
I've tested that the test now passes with --target-board=-march=armv8-m.main
and --target-board=-march=armv8.1-m.main.
Tom Tromey [Thu, 9 Apr 2020 12:52:55 +0000 (06:52 -0600)]
Merge top-level configury changes from gdb
We recently rearranged the gdb source tree to move a common library
and gdbserver to the top-level. This made the build more uniform and
also a bit faster (due to sharing of built objects).
This patch re-syncs these changes the top-level configury back to gcc.
ChangeLog:
* configure: Rebuild.
* Makefile.in: Rebuild.
* Makefile.def (gdbsupport, gdbserver): New host modules.
(configure-gdb): Depend on all-gdbsupport.
(all-gdb): Depend on all-gdbsupport, all-libctf.
* configure.ac (host_tools): Add gdbserver.
Conditionally build gdbserver and gdbsupport.
Martin Jambor [Thu, 9 Apr 2020 12:37:21 +0000 (14:37 +0200)]
sra: Fix sra_modify_expr handling of partial writes (PR 94482)
when sra_modify_expr is invoked on an expression that modifies only
part of the underlying replacement, such as a BIT_FIELD_REF on a LHS
of an assignment and the SRA replacement's type is not compatible with
what is being replaced (0th operand of the B_F_R in the above
example), it does not work properly, basically throwing away the partd
of the expr that should have stayed intact.
This is fixed in two ways. For BIT_FIELD_REFs, which operate on the
binary image of the replacement (and so in a way serve as a
VIEW_CONVERT_EXPR) we just do not bother with convertsing. For
REALPART_EXPRs and IMAGPART_EXPRs, if the replacement is not a
register, we insert a VIEW_CONVERT_EXPR under
the complex partial access expression, which is always OK, for loads
from registers we take the extra step of converting it to a temporary.
This revealed a bug in fwprop which is fixed with the hunk from Richi.
The testcase for handling REALPART_EXPR and IMAGPART_EXPR is a bit
fragile because SRA prefers complex and vector types over anything
else (and in between the two it decides based on TYPE_UID which in my
testing today always preferred complex types) and so I only run it at
-O1 (which is the only level where the the test fails for me).
Bootstrapped and tested on x86_64-linux, i686-linux and aarch64-linux.
2020-04-09 Martin Jambor <mjambor@suse.cz>
Richard Biener <rguenther@suse.de>
PR tree-optimization/94482
* tree-sra.c (create_access_replacement): Dump new replacement with
TDF_UID.
(sra_modify_expr): Fix handling of cases when the original EXPR writes
to only part of the replacement.
* tree-ssa-forwprop.c (pass_forwprop::execute): Properly verify
the first operand of combinations into REAL/IMAGPART_EXPR and
BIT_FIELD_REF.
testsuite/
* gcc.dg/torture/pr94482.c: New test.
* gcc.dg/tree-ssa/pr94482-2.c: Likewise.
Marek Polacek [Wed, 8 Apr 2020 21:03:53 +0000 (17:03 -0400)]
c++: Fix wrong paren-init of aggregates interference [PR93790]
This PR points out that we are rejecting valid code in C++20. The
problem is that we were surreptitiously transforming
T& t(e)
into
T& t{e}
which is wrong, because the type of e had a conversion function to T,
while aggregate initialization of t from e doesn't work. Therefore, I
was violating a design principle of P0960, which says that any existing
meaning of A(b) should not change. So I think we should only attempt to
aggregate-initialize if the original expression was ill-formed.
Another design principle is that () should work where {} works, so this:
struct S { int i; };
const S& s(1);
has to keep working. Thus the special handling for paren-lists with one
element. (A paren-list with more than one element would give you "error:
expression list treated as compound expression in initializer" C++17.)
PR c++/93790
* call.c (initialize_reference): If the reference binding failed, maybe
try initializing from { }.
* decl.c (grok_reference_init): For T& t(e), set
LOOKUP_AGGREGATE_PAREN_INIT but don't build up a constructor yet.
* g++.dg/cpp2a/paren-init23.C: New test.
* g++.dg/init/aggr14.C: New test.
In g:2171a9207f51bc486ed9c502cb4da706f594615e I'd tried to fix
various ILP32 testsuite failures by restricting some tests to LP64.
Unfortunately, I messed up the check-function-bodies syntax and passed
the target selector as the "option" parameter, which had the effect of
disabling the tests for both ILP32 and LP64.
The fix ought to have been to add "" as the option parameter. However,
check-function-bodies wasn't treating "" in the same way as an omitted
argument. The easiest fix seemed to be turn the argument into a list of
options, which also makes the interface a bit more general.
Having done that, it seemed a good idea to check for things that look
like target/xfail selectors, so that the mistake isn't silent next time.
2020-04-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* doc/sourcebuild.texi (check-function-bodies): Treat the third
parameter as a list of option regexps and require each regexp
to match.
gcc/testsuite/
* lib/scanasm.exp (check-function-bodies): Treat the third
parameter as a list of option regexps and require each regexp
to match. Check for cases in which a target/xfail selector
was mistakenly passed to the options argument.
* gcc.target/aarch64/sve/pcs/args_1.c: Add an empty options list
to the invocation of check-function-bodies.
* gcc.target/aarch64/sve/pcs/args_2.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_3.c: Likewise.
* gcc.target/aarch64/sve/pcs/args_4.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1_2048.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1_256.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_1_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_2.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_3.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4_2048.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4_256.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_4_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_2048.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_256.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_5_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise.
* gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_3.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_4_be.c: Likewise.
* gcc.target/aarch64/sve/pcs/saves_4_le.c: Likewise.
* gcc.target/aarch64/sve/pcs/stack_clash_2_128.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_1.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_f16.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_f32.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_f64.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_s16.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_s32.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_s64.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_s8.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_u16.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_u32.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_u64.c: Likewise.
* gcc.target/aarch64/sve/pcs/varargs_2_u8.c: Likewise.
Richard Biener [Thu, 9 Apr 2020 11:54:01 +0000 (13:54 +0200)]
testsuite/93369 - use -shared to avoid issue with ODR violation
The testcase contains an ODR violation and thus the observed
link failure is an accepted outcome (it originally was for
an ICE during WPA). Thus the following adds -shared to the link.
Bin Cheng [Thu, 9 Apr 2020 08:42:48 +0000 (16:42 +0800)]
Add unsigned type iv_cand for iv_use with non mode-precision type
Precisely, for iv_use if it's not integer/pointer type, or non-mode
precision type, add candidate for the corresponding scev in unsigned
type with the same precision, rather than its original type.
gcc/
PR tree-optimization/93674
* tree-ssa-loop-ivopts.c (langhooks.h): New include.
(add_iv_candidate_for_use): For iv_use of non integer or pointer type,
or non-mode precision type, add candidate in unsigned type with the
same precision.
gcc/testsuite/
PR tree-optimization/93674
* g++.dg/pr93674.C: New test.
coroutines: Add cleanups, where required, to statements with captured references.
When we promote captured temporaries to local variables, we also
remove their initializers from the relevant call expression. This
means that we should recompute the need for a cleanup expression
once the set of temporaries that remains becomes known.
gcc/cp/ChangeLog:
2020-04-08 Iain Sandoe <iain@sandoe.co.uk>
Jun Ma <JunMa@linux.alibaba.com>
* coroutines.cc (maybe_promote_captured_temps): Add a
cleanup expression, if needed, to any call from which
we promoted temporaries captured by reference.
Kewen Lin [Thu, 9 Apr 2020 02:52:00 +0000 (21:52 -0500)]
[testsuite] Fix PR94079 by respecting vect_hw_misalign [PR94079]
This is another vect case which requires special handling with
vect_hw_misalign. The alignment of the second part requires
misaligned vector access supports. This patch is to adjust
the related guard condition and comments.
Verified it on ppc64-redhat-linux (Power7 BE).
2020-04-09 Kewen Lin <linkw@gcc.gnu.org>
gcc/testsuite/ChangeLog
PR testsuite/94023
* gfortran.dg/vect/pr83232.f90: Expect 2 rather than 3 times SLP on
non-vect_hw_misalign targets.
As GDCFLAGS is overriden by the top-level make file with '-O2 -g',
libphobos ends up always being built with all contracts, invariants, and
asserts compiled in. This adds a new configurable that defaults to omit
compiling any run-time checks into the library using '-frelease'.
Other choices either set the flags '-fno-release', enabling all run-time
checks, or '-fassert', which only compiles in asserts.
The omission of compiling in contracts results in a smaller library
size, with faster build times.
libphobos/ChangeLog:
PR d/94305
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add --enable-libphobos-checking and substitute
CHECKING_DFLAGS. Remove -frelease from GDCFLAGS.
* libdruntime/Makefile.am: Add CHECKING_DFLAGS to AM_DFLAGS.
* libdruntime/Makefile.in: Regenerate.
* src/Makefile.am: Add CHECKING_DFLAGS to AM_DFLAGS.
* src/Makefile.in: Regenerate.
* testsuite/Makefile.in: Regenerate.
* testsuite/testsuite_flags.in: Add -fno-release -funittest to
--gdcflags.
This is another old option that doesn't make sense as a configurable.
So the option has been removed, and the check for AC_SEARCH_LIBS moved
into the main configure.ac file.
libphobos/ChangeLog:
* configure: Regenerate.
* configure.ac: Use AC_SEARCH_LIBS for pthread_create.
* m4/druntime/libraries.m4: Remove DRUNTIME_LIBRARIES_THREAD.
This option is not useful on its own as all posix modules require the
compiler to predefine version(Posix) anyway. So the option has been
removed, and logic moved into DRUNTIME_OS_SOURCES, where the conditional
DRUNTIME_OS_POSIX is set instead.
Jakub Jelinek [Wed, 8 Apr 2020 19:23:58 +0000 (21:23 +0200)]
cselib, reload: Fix cselib ICE on m68k/microblaze [PR94526]
The following testcase ICEs on m68k (and another one Jeff mailed me
privately on microblaze).
The problem is that reload creates two DEBUG_INSNs with the same
value of (plus:P (reg:P sp) (const_int 0)), we compute correctly the
same hash value for them, but then don't find them in the cselib hash table,
as rtx_equal_for_cselib_1 thinks it is different from (reg:P sp),
and trigger an assertion failure that requires that from two different debug
insns one doesn't add locations to VALUEs.
The patch has two fixes for this, each fixes the ICE on both targets
separately, but I think we want both.
The cselib.c change ensures that rtx_equal_for_cselib_1 considers
(value:P sp_derived_value) and (plus:P (reg:P sp) (const_int 0)) equivalent.
The reload1.c change makes sure we don't create those bogus plus 0
expressions. I understand the reasons for creating them, but they don't
really apply to DEBUG_INSNs; we don't have validity matching there, all we
care is that the expressions aren't arbitrarily deep, but it is just fine
to fold x + 0 into just x in there.
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/94526
* cselib.c (autoinc_split): Handle e->val_rtx being SP_DERIVED_VALUE_P
with zero offset.
* reload1.c (eliminate_regs_1): Avoid creating
(plus (reg) (const_int 0)) in DEBUG_INSNs.
Jakub Jelinek [Wed, 8 Apr 2020 19:22:05 +0000 (21:22 +0200)]
vect: Fix up lowering of TRUNC_MOD_EXPR by negative constant [PR94524]
The first testcase below is miscompiled, because for the division part
of the lowering we canonicalize negative divisors to their absolute value
(similarly how expmed.c canonicalizes it), but when multiplying the division
result back by the VECTOR_CST, we use the original constant, which can
contain negative divisors.
Fixed by computing ABS_EXPR of the VECTOR_CST. Unfortunately, fold-const.c
doesn't support const_unop (ABS_EXPR, VECTOR_CST) and I think it is too late
in GCC 10 cycle to add it now.
Furthermore, while modulo by most negative constant happens to return the
right value, it does that only by invoking UB in the IL, because
we then expand division by that 1U+INT_MAX and say for INT_MIN % INT_MIN
compute the division as -1, and then multiply by INT_MIN, which is signed
integer overflow. We in theory could do the computation in unsigned vector
types instead, but is it worth bothering. People that are doing % INT_MIN
are either testing for standard conformance, or doing something wrong.
So, I've also added punting on % INT_MIN, both in vect lowering and vect
pattern recognition (we punt already for / INT_MIN).
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/94524
* tree-vect-generic.c (expand_vector_divmod): If any elt of op1 is
negative for signed TRUNC_MOD_EXPR, multiply with absolute value of
op1 rather than op1 itself at the end. Punt for signed modulo by
most negative constant.
* tree-vect-patterns.c (vect_recog_divmod_pattern): Punt for signed
modulo by most negative constant.
* gcc.c-torture/execute/pr94524-1.c: New test.
* gcc.c-torture/execute/pr94524-2.c: New test.
Jakub Jelinek [Wed, 8 Apr 2020 17:54:35 +0000 (19:54 +0200)]
openacc: Fix up declare-pr94120.C testcase [PR94533]
This test has been put in a wrong directory, where OpenACC tests aren't
tested with -fopenacc, and also contained trailing semicolons.
I've moved it where it belongs, added dg-error directives and removed
the extra semicolons.
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/94120
PR testsuite/94533
* g++.dg/declare-pr94120.C: Move test to ...
* g++.dg/goacc/declare-pr94120.C: ... here. Add dg-error directives.
Marek Polacek [Mon, 6 Apr 2020 23:59:04 +0000 (19:59 -0400)]
c++: Fix ICE-on-invalid with lambda template [PR94507]
While reducing something else I noticed that we ICE on the following
invalid code. In tsubst_lambda_expr, tsubst_template_decl has already
reported an error and returned the error_mark_node, so make sure we
don't ICE on that. I'm using a goto here because we still have to
do finish_struct because it does popclass ().
PR c++/94507 - ICE-on-invalid with lambda template.
* pt.c (tsubst_lambda_expr): Cope when tsubst_template_decl or
tsubst_function_decl returns error_mark_node.
dg-require-effective-target arm_fp16_alternative_ok may pass even when
arm_fp16_ok doesn't, and the latter's failure inhibits dg-add-options
arm_fp16_alternative. Requiring arm_fp16_ok would disable the test,
but if we just pass it the -mfp16-format=alternative option, it passes
even without arm_fp16_ok. Sibling test fp16-aapcs-4.c underwent a
similar change, so I'm proposing the explicit option to fp16-aapcs-3.c
as well.
for gcc/testsuite/ChangeLog
* gcc.target/arm/fp16-aapcs-3.c: Explicitly use the
-mfp16-format=alternative option.
H.J. Lu [Wed, 8 Apr 2020 16:47:35 +0000 (09:47 -0700)]
x86: Insert ENDBR if function will be called indirectly
Since constant_call_address_operand has
;; Test for a pc-relative call operand
(define_predicate "constant_call_address_operand"
(match_code "symbol_ref")
{
if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
|| flag_force_indirect_call)
return false;
if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
return false;
return true;
})
even if cgraph_node::get (cfun->decl)->only_called_directly_p () returns
false, the fuction may still be called indirectly. Copy the logic from
constant_call_address_operand to rest_of_insert_endbranch to insert ENDBR
at function entry if function will be called indirectly.
gcc/
PR target/94417
* config/i386/i386-features.c (rest_of_insert_endbranch): Insert
ENDBR at function entry if function will be called indirectly.
Jakub Jelinek [Wed, 8 Apr 2020 16:24:12 +0000 (18:24 +0200)]
i386: Don't use AVX512F integral masks for V*TImode [PR94438]
The ix86_get_mask_mode hook uses int mask for 512-bit vectors or 128/256-bit
vectors with AVX512VL (that is correct), and only for V*[SD][IF]mode if not
AVX512BW (also correct), but with AVX512BW it would stop checking the
elem_size altogether and pretend the hw has masking support for V*TImode
etc., which it doesn't. That can lead to various ICEs later on.
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR target/94438
* config/i386/i386.c (ix86_get_mask_mode): Only use int mask for elem_size
1, 2, 4 and 8.
* gcc.target/i386/avx512bw-pr94438.c: New test.
* gcc.target/i386/avx512vlbw-pr94438.c: New test.
All TLS execution tests require tls_runtime, not just tls; pr78796.c
is the only exception that is not otherwise limited to platforms known
to support it. I suppose that's an oversight. On a platform whose
linker is configured to disregard TLS relocations, this test compiles
and assembles successfully, but execution fails. The tls_runtime
requirement target avoids the noise from the expected failure.
[Arm] Implement CDE predicated intrinsics for MVE registers
These intrinsics are the predicated version of the intrinsics inroduced
in https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542725.html.
These are not yet public on developer.arm.com but we have reached
internal consensus on them.
The approach follows the same method as for the CDE intrinsics for MVE
registers, most notably using the same arm_resolve_overloaded_builtin
function with minor modifications.
The resolver hook has been moved from arm-builtins.c to arm-c.c so it
can access the c-common function build_function_call_vec. This function
is needed to perform the same checks on arguments as a normal C or C++
function would perform.
It is fine to put this resolver in arm-c.c since it's only use is for
the ACLE functions, and these are only available in C/C++.
So that the resolver function has access to information it needs from
the builtins, we put two query functions into arm-builtins.c and use
them from arm-c.c.
We rely on the order that the builtins are defined in
gcc/config/arm/arm_cde_builtins.def, knowing that the predicated
versions come after the non-predicated versions.
The machine description patterns for these builtins are simpler than
those for the non-predicated versions, since the accumulator versions
*and* non-accumulator versions both need an input vector now.
The input vector is needed for the non-accumulator version to describe
the original values for those lanes that are not updated during the
merge operation.
We additionally need to introduce qualifiers for these new builtins,
which follow the same pattern as the non-predicated versions but with an
extra argument to describe the predicate.
Error message changes:
- We directly mention the builtin argument when complaining that an
argument is not in the correct range.
This more closely matches the C error messages.
- We ensure the resolver complains about *all* invalid arguments to a
function instead of just the first one.
- The resolver error messages index arguments from 1 instead of 0 to
match the arguments coming from the C/C++ frontend.
In order to allow the user to give an argument for the merging predicate
when they don't care what data is stored in the 'false' lanes, we also
move the __arm_vuninitializedq* intrinsics from arm_mve.h to
arm_mve_types.h which is shared with arm_cde.h.
We only move the fully type-specified `__arm_vuninitializedq*`
intrinsics and not the polymorphic versions, since moving the
polymorphic versions requires moving the _Generic framework as well as
just the intrinsics we're interested in. This matches the approach taken
for the `__arm_vreinterpret*` functions in this include file.
This patch also contains a slight change in spacing of an existing
assembly instruction to be emitted.
This is just to help writing tests -- vmsr usually has a tab and a space
between the mnemonic and the first argument, but in one case it just has
a tab -- making all the same helps make test regexps simpler.
Testing Done:
Bootstrap and full regtest on arm-none-linux-gnueabihf
Full regtest on arm-none-eabi
All testing done with a local fix for the bugzilla PR below.
That bugzilla currently causes multiple ICE's on the tests added in
this patch.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94341
gcc/ChangeLog:
2020-04-02 Matthew Malcomson <matthew.malcomson@arm.com>
* config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): New.
(CX_BINARY_UNONE_QUALIFIERS): New.
(CX_TERNARY_UNONE_QUALIFIERS): New.
(arm_resolve_overloaded_builtin): Move to arm-c.c.
(arm_expand_builtin_args): Update error message.
(enum resolver_ident): New.
(arm_describe_resolver): New.
(arm_cde_end_args): New.
* config/arm/arm-builtins.h: New file.
* config/arm/arm-c.c (arm_resolve_overloaded_builtin): New.
(arm_resolve_cde_builtin): Moved from arm-builtins.c.
* config/arm/arm_cde.h (__arm_vcx1q_m, __arm_vcx1qa_m,
__arm_vcx2q_m, __arm_vcx2qa_m, __arm_vcx3q_m, __arm_vcx3qa_m):
New.
* config/arm/arm_cde_builtins.def (vcx1q_p_, vcx1qa_p_,
vcx2q_p_, vcx2qa_p_, vcx3q_p_, vcx3qa_p_): New builtin defs.
* config/arm/iterators.md (CDE_VCX): New int iterator.
(a) New int attribute.
* config/arm/mve.md (arm_vcx1q<a>_p_v16qi, arm_vcx2q<a>_p_v16qi,
arm_vcx3q<a>_p_v16qi): New patterns.
* config/arm/vfp.md (thumb2_movhi_fp16): Extra space in assembly.
gcc/testsuite/ChangeLog:
2020-04-02 Matthew Malcomson <matthew.malcomson@arm.com>
Other than the basics required for adding intrinsics this patch consists
of three changes.
** We separate out the MVE types and casts from the arm_mve.h header.
This is so that the types can be used in arm_cde.h without the need to include
the entire arm_mve.h header.
The only type that arm_cde.h needs is `uint8x16_t`, so this separation could be
avoided by using a `typedef` in this file.
Since the introduced intrinsics are all defined to act on the full range of MVE
types, declaring all such types seems intuitive since it will provide their
declaration to the user too.
This arm_mve_types.h header not only includes the MVE types, but also
the conversion intrinsics between them.
Some of the conversion intrinsics are needed for arm_cde.h, but most are
not. We include all conversion intrinsics to keep the definition of
such conversion functions all in one place, on the understanding that
extra conversion functions being defined when including `arm_cde.h` is
not a problem.
** We define the TARGET_RESOLVE_OVERLOADED_BUILTIN hook for the Arm backend.
This is needed to implement the polymorphism for the required intrinsics.
The intrinsics have no specialised version, and the resulting assembly
instruction for all different types should be exactly the same.
Due to this we have implemented these intrinsics via one builtin on one type.
All other calls to the intrinsic with different types are implicitly cast to
the one type that is defined, and hence are all expanded to the same RTL
pattern that is only defined for one machine mode.
** We seperate the initialisation of the CDE intrinsics from others.
This allows us to ensure that the CDE intrinsics acting on MVE registers
are only created when both CDE and MVE are available.
Only initialising these builtins when both features are available is
especially important since they require a type that is only initialised
when the target supports hard float. Hence trying to initialise these
builtins on a soft float target would cause an ICE.
Testing done:
Full bootstrap and regtest on arm-none-linux-gnueabihf
Regression test on arm-none-eabi
Ok for trunk?
gcc/ChangeLog:
2020-03-10 Matthew Malcomson <matthew.malcomson@arm.com>
* config.gcc (arm_mve_types.h): New extra_header for arm.
* config/arm/arm-builtins.c (arm_resolve_overloaded_builtin): New.
(arm_init_cde_builtins): New.
(arm_init_acle_builtins): Remove initialisation of CDE builtins.
(arm_init_builtins): Call arm_init_cde_builtins when target
supports CDE.
* config/arm/arm-c.c (arm_resolve_overloaded_builtin): New declaration.
(arm_register_target_pragmas): Initialise resolve_overloaded_builtin
hook to the implementation for the arm backend.
* config/arm/arm.h (ARM_MVE_CDE_CONST_1): New.
(ARM_MVE_CDE_CONST_2): New.
(ARM_MVE_CDE_CONST_3): New.
* config/arm/arm_cde.h (__arm_vcx1q_u8): New.
(__arm_vcx1qa): New.
(__arm_vcx2q): New.
(__arm_vcx2q_u8): New.
(__arm_vcx2qa): New.
(__arm_vcx3q): New.
(__arm_vcx3q_u8): New.
(__arm_vcx3qa): New.
* config/arm/arm_cde_builtins.def (vcx1q, vcx1qa, vcx2q, vcx2qa, vcx3q,
vcx3qa): New builtins defined.
* config/arm/arm_mve.h: Move typedefs and conversion intrinsics
to arm_mve_types.h header.
* config/arm/arm_mve_types.h: New file.
* config/arm/mve.md (arm_vcx1qv16qi, arm_vcx1qav16qi, arm_vcx2qv16qi,
arm_vcx2qav16qi, arm_vcx3qv16qi, arm_vcx3qav16qi): New patterns.
* config/arm/predicates.md (const_int_mve_cde1_operand,
const_int_mve_cde2_operand, const_int_mve_cde3_operand): New.
gcc/testsuite/ChangeLog:
2020-03-23 Matthew Malcomson <matthew.malcomson@arm.com>
Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/acle/cde-mve-error-1.c: New test.
* gcc.target/arm/acle/cde-mve-error-2.c: New test.
* gcc.target/arm/acle/cde-mve-error-3.c: New test.
* gcc.target/arm/acle/cde-mve-full-assembly.c: New test.
* gcc.target/arm/acle/cde-mve-tests.c: New test.
* lib/target-supports.exp (arm_v8_1m_main_cde_mve_fp): New check
effective.
(arm_v8_1m_main_cde_mve, arm_v8m_main_cde_fp): Use -mfpu=auto
so we only check configurations that make sense.
This patch introduces the scalar CDE (Custom Datapath Extension)
intrinsics for the arm backend.
There is nothing beyond the standard in this patch. We simply build upon what
has been done by Dennis for the vector intrinsics.
We do add `+cdecp6` to the default arguments for `target-supports.exp`, this
allows for using coprocessor 6 in tests. This patch uses an alternate
coprocessor to ease assembler scanning by looking for a use of coprocessor 6.
We also ensure that any DImode registers are put in an even-odd register pair
when compiling for a target with CDE -- this avoids faulty code generation for
-Os when producing the cx*d instructions.
Testing done:
Bootstrapped and regtested for arm-none-linux-gnueabihf.
gcc/ChangeLog:
2020-03-03 Matthew Malcomson <matthew.malcomson@arm.com>
Dennis Zhang [Wed, 8 Apr 2020 14:33:40 +0000 (15:33 +0100)]
arm: CDE intrinsics using FPU/MVE S/D registers
This patch enables the ACLE intrinsics calling VCX1<A>,
VCX2<A>, and VCX3<A> instructions who work with FPU/MVE
32-bit/64-bit registers. This patch also enables DImode for VFP
to support CDE with FPU.
gcc/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
Matthew Malcomson <matthew.malcomson@arm.com>
* config/arm/arm-builtins.c (CX_IMM_QUALIFIERS): New macro.
(CX_UNARY_QUALIFIERS, CX_BINARY_QUALIFIERS): Likewise.
(CX_TERNARY_QUALIFIERS): Likewise.
(ARM_BUILTIN_CDE_PATTERN_START): Likewise.
(ARM_BUILTIN_CDE_PATTERN_END): Likewise.
(arm_init_acle_builtins): Initialize CDE builtins.
(arm_expand_acle_builtin): Check CDE constant operands.
* config/arm/arm.h (ARM_CDE_CONST_COPROC): New macro to set the range
of CDE constant operand.
* config/arm/arm.c (arm_hard_regno_mode_ok): Support DImode for
TARGET_VFP_BASE.
(ARM_VCDE_CONST_1, ARM_VCDE_CONST_2, ARM_VCDE_CONST_3): Likewise.
* config/arm/arm_cde.h (__arm_vcx1_u32): New macro of ACLE interface.
(__arm_vcx1a_u32, __arm_vcx2_u32, __arm_vcx2a_u32): Likewise.
(__arm_vcx3_u32, __arm_vcx3a_u32, __arm_vcx1d_u64): Likewise.
(__arm_vcx1da_u64, __arm_vcx2d_u64, __arm_vcx2da_u64): Likewise.
(__arm_vcx3d_u64, __arm_vcx3da_u64): Likewise.
* config/arm/arm_cde_builtins.def: New file.
* config/arm/iterators.md (V_reg): New attribute of SI.
* config/arm/predicates.md (const_int_coproc_operand): New.
(const_int_vcde1_operand, const_int_vcde2_operand): New.
(const_int_vcde3_operand): New.
* config/arm/unspecs.md (UNSPEC_VCDE, UNSPEC_VCDEA): New.
* config/arm/vfp.md (arm_vcx1<mode>): New entry.
(arm_vcx1a<mode>, arm_vcx2<mode>, arm_vcx2a<mode>): Likewise.
(arm_vcx3<mode>, arm_vcx3a<mode>): Likewise.
gcc/testsuite/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/acle/cde_v_1.c: New test.
* gcc.target/arm/acle/cde_v_1_err.c: New test.
* gcc.target/arm/acle/cde_v_1_mve.c: New test.
Patrick Palka [Mon, 30 Mar 2020 23:55:03 +0000 (19:55 -0400)]
c++: Function type and parameter type disagreements [PR92010]
This resolves parts of Core issues 1001/1322 by rebuilding the function type
of an instantiated function template in terms of its formal parameter types
whenever the original function type and formal parameter types disagree about
the type of a parameter after substitution.
gcc/cp/ChangeLog:
Core issues 1001 and 1322
PR c++/92010
* pt.c (rebuild_function_or_method_type): Split function out from ...
(tsubst_function_type): ... here.
(maybe_rebuild_function_decl_type): New function.
(tsubst_function_decl): Use it.
gcc/testsuite/ChangeLog:
Core issues 1001 and 1322
PR c++/92010
* g++.dg/cpp2a/lambda-uneval11.c: New test.
* g++.dg/template/array33.C: New test.
* g++.dg/template/array34.C: New test.
* g++.dg/template/defarg22.C: New test.
Dennis Zhang [Wed, 8 Apr 2020 14:06:31 +0000 (15:06 +0100)]
arm: CLI for Custom Datapath Extension (CDE)
This patch is part of a series that adds support for the Arm Custom
Datapath Extension. It defines the options cdecp0-cdecp7 for CLI to
enable the CDE on corresponding coprocessor 0-7.
It also adds new target supports for CDE feature testsuite.
gcc/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
* config.gcc: Add arm_cde.h.
* config/arm/arm-c.c (arm_cpu_builtins): Define or undefine
__ARM_FEATURE_CDE and __ARM_FEATURE_CDE_COPROC.
* config/arm/arm-cpus.in (cdecp0, cdecp1, ..., cdecp7): New options.
* config/arm/arm.c (arm_option_reconfigure_globals): Configure
arm_arch_cde and arm_arch_cde_coproc to store the feature bits.
* config/arm/arm.h (TARGET_CDE): New macro.
* config/arm/arm_cde.h: New file.
* doc/invoke.texi: Document CDE options +cdecp[0-7].
* doc/sourcebuild.texi (arm_v8m_main_cde_ok): Document new target
supports option.
(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
gcc/testsuite/ChangeLog:
2020-04-08 Dennis Zhang <dennis.zhang@arm.com>
* gcc.target/arm/pragma_cde.c: New test.
* lib/target-supports.exp (arm_v8m_main_cde_ok): New target support
option.
(arm_v8m_main_cde_fp, arm_v8_1m_main_cde_mve): Likewise.
Jakub Jelinek [Wed, 8 Apr 2020 13:30:16 +0000 (15:30 +0200)]
c++: Further fix for -fsanitize=vptr [PR94325]
For -fsanitize=vptr, we insert a NULL store into the vptr instead of just
adding a CLOBBER of this. build_clobber_this makes the CLOBBER conditional
on in_charge (implicit) parameter whenever CLASSTYPE_VBASECLASSES, but when
adding this conditionalization to the -fsanitize=vptr code in PR87095,
I wanted it to catch some more cases when the class has CLASSTYPE_VBASECLASSES,
but the vptr is still not shared with something else, otherwise the
sanitization would be less effective.
The following testcase shows that the chosen test that CLASSTYPE_PRIMARY_BINFO
is non-NULL and has BINFO_VIRTUAL_P set wasn't sufficient,
the D class has still sizeof(D) == sizeof(void*) and thus contains just
a single vptr, but while in B::~B() this results in the vptr not being
cleared, in C::~C() this condition isn't true, as CLASSTYPE_PRIMARY_BINFO
in that case is B and is not BINFO_VIRTUAL_P, so it clears the vptr, but the
D::~D() dtor after invoking C::~C() invokes A::~A() with an already cleared
vptr, which is then reported.
The following patch is just a shot in the dark, keep looking through
CLASSTYPE_PRIMARY_BINFO until we find BINFO_VIRTUAL_P, but it works on the
existing testcase as well as this new one.
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR c++/94325
* decl.c (begin_destructor_body): For CLASSTYPE_VBASECLASSES class
dtors, if CLASSTYPE_PRIMARY_BINFO is non-NULL, but not BINFO_VIRTUAL_P,
look at CLASSTYPE_PRIMARY_BINFO of its BINFO_TYPE if it is not
BINFO_VIRTUAL_P, and so on.
Marek Polacek [Tue, 7 Apr 2020 18:24:52 +0000 (14:24 -0400)]
c++: ICE with defaulted comparison operator [PR94478]
Here we ICE because early_check_defaulted_comparison passed a null
ctx to same_type_p. The attached test is ill-formed according to
[class.compare.default]/1, so fixed by detecting this case early.
PR c++/94478 - ICE with defaulted comparison operator
* method.c (early_check_defaulted_comparison): Give an error when the
context is null.
Since commit 2f6d557ff82876432be76b1892c6c3783c0095f4 AKA SVN-r269586,
the inform() message suggesting the use of -flax-vector-conversions
has had quotes around the option name, but the testcase still expected
the message without the quotes. This patch adds to the expected
compiler output the quotes that are now issues.
for gcc/testsuite/ChangeLog
* gcc.target/arm/polytypes.c: Add quotes around
-flax-vector-conversions.
Jakub Jelinek [Wed, 8 Apr 2020 10:04:46 +0000 (12:04 +0200)]
postreload: Fix autoinc handling in reload_cse_move2add [PR94516]
The following testcase shows two separate issues caused by the cselib
changes.
One is that through the cselib sp tracking improvements on
... r12 = rsp; rsp -= 8; push cst1; push cst2; push cst3; call
rsp += 32; rsp -= 8; push cst4; push cst5; push cst6; call
rsp += 32; rsp -= 8; push cst7; push cst8; push cst9; call
rsp += 32
reload_cse_simplify_set decides to optimize the rsp += 32 insns
into rsp = r12 because cselib figures that the r12 register holds the right
value. From the pure cost perspective that seems like a win and on its own
at least for -Os that would be beneficial, except that there are those
rsp -= 8 stack adjustments after it, where rsp += 32; rsp -= 8; is optimized
into rsp += 24; by the csa pass, but rsp = r12; rsp -= 8 can't. Dunno
what to do about this part, the PR has a hack in a comment.
Anyway, the following patch fixes the other part, which isn't a missed
optimization, but a wrong-code issue. The problem is that the pushes of
constant are on x86 represented through PRE_MODIFY and while
move2add_note_store has some code to handle {PRE,POST}_{INC,DEC} without
REG_INC note, it doesn't handle {PRE,POST}_MODIFY (that would be enough
to fix this testcase). But additionally it looks misplaced, because
move2add_note_store is only called on the rtxes that are stored into,
while RTX_AUTOINC can happen not just in those, but anywhere else in the
instruction (e.g. pop insn can have autoinc in the SET_SRC MEM).
REG_INC note seems to be required for any autoinc except for stack pointer
autoinc which doesn't have those notes, so this patch just handles
the sp autoinc after the REG_INC note handling loop.
2020-04-08 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/94516
* postreload.c: Include rtl-iter.h.
(reload_cse_move2add): Handle SP autoinc here by FOR_EACH_SUBRTX_VAR
looking for all MEMs with RTX_AUTOINC operand.
(move2add_note_store): Remove {PRE,POST}_{INC,DEC} handling.
[C/C++, OpenACC] Reject vars of different scope in acc declare (PR94120)
gcc/c/
PR middle-end/94120
* c-decl.c (c_check_in_current_scope): New function.
* c-tree.h (c_check_in_current_scope): Declare it.
* c-parser.c (c_parser_oacc_declare): Add check that variables
are declared in the same scope as the directive. Fix handling
of namespace vars.
gcc/cp/
PR middle-end/94120
* paser.c (cp_parser_oacc_declare): Add check that variables
are declared in the same scope as the directive.
Iain Buclaw [Sun, 29 Mar 2020 21:54:01 +0000 (23:54 +0200)]
libphobos: Always build with warning flags enabled
This moves WARN_DFLAGS from GDCFLAGS to AM_DFLAGS so it is always
included in the build and testsuite of libphobos. Currently, this
doesn't happen as GDCFLAGS is overriden by it being set at the
top-level.
libphobos/ChangeLog:
* Makefile.in: Regenerate.
* configure: Regenerate.
* configure.ac: Substite WARN_DFLAGS independently of GDCFLAGS.
* libdruntime/Makefile.am: Add WARN_DFLAGS to AM_DFLAGS.
* libdruntime/Makefile.in: Regenerate.
* src/Makefile.am: Add WARN_DFLAGS to AM_DFLAGS.
* src/Makefile.in: Regenerate.
* testsuite/Makefile.in: Regenerate.
* testsuite/testsuite_flags.in: Add WARN_DFLAGS to --gdcflags.
Jason Merrill [Tue, 7 Apr 2020 04:45:26 +0000 (00:45 -0400)]
c++: requires-expression and tentative parse [PR94480]
The problem here was that cp_parser_requires_expression committing to a
tentative parse confused cp_parser_decltype_expr, which needs to still be
tentative. The only reason to commit here is to get syntax errors within
the requires-expression, which we can still do when the commit is firewalled
from the enclosing context.
gcc/cp/ChangeLog
2020-04-07 Jason Merrill <jason@redhat.com>
PR c++/94480
* parser.c (cp_parser_requires_expression): Use tentative_firewall.
Jakub Jelinek [Tue, 7 Apr 2020 19:30:12 +0000 (21:30 +0200)]
combine: Fix split_i2i3 ICE [PR94291]
The following testcase ICEs on armv7hl-linux-gnueabi.
try_combine is called on:
(gdb) p debug_rtx (i3)
(insn 20 12 22 2 (set (mem/c:SI (plus:SI (reg/f:SI 102 sfp)
(const_int -4 [0xfffffffffffffffc])) [1 x+0 S4 A32])
(reg:SI 125)) "pr94291.c":7:8 241 {*arm_movsi_insn}
(expr_list:REG_DEAD (reg:SI 125)
(nil)))
(gdb) p debug_rtx (i2)
(insn 12 7 20 2 (parallel [
(set (reg:CC 100 cc)
(compare:CC (reg:SI 121 [ <retval> ])
(const_int 0 [0])))
(set (reg:SI 125)
(reg:SI 121 [ <retval> ]))
]) "pr94291.c":7:8 248 {*movsi_compare0}
(expr_list:REG_UNUSED (reg:CC 100 cc)
(nil)))
and tries to recognize cc = r121 cmp 0; [sfp-4] = r121 parallel,
but that isn't recognized, so it splits it into two: split_i2i3
[sfp-4] = r121 followed by cc = r121 cmp 0 which is recognized, but
ICEs because the code below insist that the SET_DEST of newi2pat
(or first set in PARALLEL thereof) must be a REG or SUBREG of REG,
but it is a MEM in this case. I don't see any condition that would
guarantee that, perhaps for the swap_i2i3 case it was somehow guaranteed.
As the code just wants to update LOG_LINKS and LOG_LINKS are only for
registers, not for MEM or anything else, the patch just doesn't update those
if it isn't a REG or SUBREG of REG.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/94291
PR rtl-optimization/84169
* combine.c (try_combine): For split_i2i3, don't assume SET_DEST
must be a REG or SUBREG of REG; if it is not one of these, don't
update LOG_LINKs.
Robin Dapp [Tue, 7 Apr 2020 19:05:38 +0000 (21:05 +0200)]
S/390: Fix PR91628
With this patch we get rid of the usage of the glibc-internal symbol
__tls_get_addr_internal.
If build with multilib, the file
gcc/libphobos/libdruntime/config/systemz/get_tls_offset.S is used
for both configurations: systemz and s390.
Therefore both implementations are now in the systemz file which
uses an "#ifdef __s390x__" in order to distinguish both cases.
The s390 file is just including the systemz one.
libphobos/ChangeLog:
2020-04-07 Robin Dapp <rdapp@linux.ibm.com>
Stefan Liebler <stli@linux.ibm.com>
* configure: Regenerate.
* libdruntime/Makefile.am: Add s390x and s390.
* libdruntime/Makefile.in: Regenerate.
* libdruntime/config/s390/get_tls_offset.S: New file.
* libdruntime/config/systemz/get_tls_offset.S: New file.
* libdruntime/gcc/sections/elf_shared.d: Use ibmz_get_tls_offset.
* m4/druntime/cpu.m4: Add s390x and s390.
Richard Biener [Tue, 7 Apr 2020 14:29:37 +0000 (16:29 +0200)]
middle-end/94479 - fix gimplification of address
When gimplifying an address operand we may expose an indirect
ref via DECL_VALUE_EXPR for example. This is dealt with in the
code already but it fails to consider that INDIRECT_REFs get
gimplified to MEM_REFs.
Fixed which makes the ICE observed on x86_64-netbsd go away.
2020-04-07 Richard Biener <rguenther@suse.de>
PR middle-end/94479
* gimplify.c (gimplify_addr_expr): Also consider generated
MEM_REFs.
The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port. The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases. All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR target/94488
* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
Assume it is a REG after that instead of testing it and doing FAIL
otherwise. Formatting fix.
Jonathan Wakely [Tue, 7 Apr 2020 16:18:21 +0000 (17:18 +0100)]
libstdc++: Restore ability to use <charconv> in C++14 (PR 94520)
This C++17 header is supported in C++14 as a GNU extension, but stopped
working last year because I made it depend on an internal helper which
is only defined for C++17 and up.
PR libstdc++/94520
* include/std/charconv (__integer_to_chars_result_type)
(__integer_from_chars_result_type): Use __or_ instead of __or_v_ to
allow use in C++14.
* testsuite/20_util/from_chars/1.cc: Run test as C++14 and replace
use of std::string_view with std::string.
* testsuite/20_util/from_chars/2.cc: Likewise.
* testsuite/20_util/to_chars/1.cc: Likewise.
* testsuite/20_util/to_chars/2.cc: Likewise.
coroutines, ensure placeholder var is properly declared.
In cases that we need to extended the lifetime of a temporary captured
by reference, we make a replacement var for the temporary. This will
be then used to define a coroutine frame entry (so that the var created
is elided by a later phase). However, we should ensure that the var
is correctly declared anyway.
gcc/cp/ChangeLog:
2020-04-07 Iain Sandoe <iain@sandoe.co.uk>
* coroutines.cc (maybe_promote_captured_temps): Ensure that
reference capture placeholder vars are properly declared.
arm: MVE: Add C++ polymorphism and fix some more issues
This patch adds C++ polymorphism for the MVE intrinsics, by using the native C++
polymorphic functions when C++ is used.
It also moves the PRESERVE name macro definitions to the right place so that the
variants without the '__arm_' prefix are not available if we define the PRESERVE
NAMESPACE macro.
This patch further fixes two testisms that were brought to light by C++ testing
added in this patch.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Add C++ polymorphism and fix preserve MACROs.
gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
arm: MVE: Fixes for pointers used in intrinsics for c++
This patch fixes the passing of some pointers to builtins that expect slightly
different types of pointers. In C this didn't prove an issue, but when
compiling for C++ gcc complains.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Cast some pointers to expected types.
arm: MVE: make sure we only use the Arm namespace variant of vuninitializedq
This patch replaces all uses of 'vuninitializedq_*' by the same function but
under the __arm_ namespace. In case we define the PRESERVE MACRO the variant
without the '__arm_' prefix will not be available.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Replace all uses of vuninitializedq_* with the
same with '__arm_' prefix.
This patch fixes vec extracts to memory that can arise from code as seen in the
testcase added. The patch fixes this by allowing mem operands in the set of
mve_vec_extract patterns, which given the only '=r' constraint will lead to the
scalar value being written to a register and then stored in memory using scalar
store pattern.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/mve.md (mve_vec_extract*): Allow memory operands in set.
gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/mve/intrinsics/mve_vec_extracts_from_memory.c: New
test.
arm: MVE Fix immediate constraints on some vector instructions
Hi,
This patch fixes the immediate checks on vcvt and vqshr(u)n[bt] instructions.
It also removes the 'arm_mve_immediate_check' as the check was wrong and the
error message is not much better than the constraint one, which albeit isn't
great either.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
After fixing the v[id]wdups using the "moving the wrap parameter" into the
top-end of a DImode operand using a shift, I noticed we were using lsll for
32-bit shifts in scalars, where we don't need to, as we can simply do a move,
which is much better if we don't need to use the bottom part.
We can solve this in a better way, but for now this will do.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.d (ashldi3): Don't use lsll for constant 32-bit shifts.
This patch fixes v[id]wdup intrinsics. They had two issues:
1) the predicated versions did not link the incoming inactive vector parameter
to the output
2) The backend didn't enforce the wrap limit operand be in an odd register.
1) was fixed like we did for all other predicated intrinsics
2) requires a temporary hack where we pass the value in the top end of DImode
operand. The proper fix would be to add a register CLASS but this interacted
badly with other existing targets codegen. We will look to fix this properly in GCC 11.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
arm: MVE: Do not use typeof for pointer parameters
To make sure our inlining of _Generic doesn't go crazy we added an in between
declaration of the parameters used for _Generic selection. However, this will
not work if the parameter being passed in is an array. Since none of our
intrinsics return pointers we do not need to use typeof here as we will never be
able to nest intrinsics through this parameter. I also removed the unnecessary
const pointers in mve_typeid.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
and remove const_ptr enums.
arm: MVE: Fix polymorphism for scalars and constants
This patch merges some polymorphic functions that were uncorrectly separating
scalar variants. It also simplifies the way we detect scalars and constants in
mve_typeid.
I also fixed some polymorphic intrinsics that were splitting of scalar cases.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
Stefan Liebler [Tue, 7 Apr 2020 14:14:40 +0000 (16:14 +0200)]
S/390: Fix layout of struct sigaction_t
The ordering of some fields in struct sigaction on s390x (64bit)
differs compared to s390 and other architectures.
This patch adjusts this order according to the definition of
<glibc-src>/sysdeps/unix/sysv/linux/s390/bits/sigaction.h
Without this fix e.g. the call
sigaction( suspendSignalNumber, &sigusr1, null ) in thread.d
leads to setting the sa_restorer field to 0xffffffffffffffff.
In case a signal, the signal handler returns to this address
and the process stops with a SIGILL.
This was observable in several execution testcases on s390x:
libphobos.druntime/core/thread.d
libphobos.druntime_shared/core/thread.d
libphobos.thread/tlsgc_sections.d
libphobos.allocations/tls_gc_integration.d
libphobos.phobos/std/parallelism.d
libphobos.phobos_shared/std/parallelism.d
libphobos.shared/host.c
libphobos.shared/linkD.c
libphobos.shared/linkDR.c
libphobos.shared/link_linkdep.d
libphobos.shared/load.d
libphobos.shared/loadDR.c
libphobos.shared/load_linkdep.d
libphobos.shared/load_loaddep.d
libphobos/ChangeLog:
2020-04-07 Stefan Liebler <stli@linux.ibm.com>
* libdruntime/core/sys/posix/signal.d:
Add struct sigaction_t for SystemZ.
Patrick Palka [Mon, 6 Apr 2020 18:05:44 +0000 (14:05 -0400)]
c++: Fix usage of CONSTRUCTOR_PLACEHOLDER_BOUNDARY inside array initializers [PR90996]
This PR reports that ever since the introduction of the
CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag, we are sometimes failing to resolve
PLACEHOLDER_EXPRs inside array initializers that refer to some inner
constructor. In the testcase in the PR, we have as the initializer for "S c[];"
the following
where CONSTRUCTOR_PLACEHOLDER_BOUNDARY is set on the middle constructor. When
calling replace_placeholders from store_init_value, we pass the entire
initializer to it, and as a result we fail to resolve the PLACEHOLDER_EXPR
within due to the CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag on the middle
constructor blocking replace_placeholders_r from reaching it.
To fix this, we could perhaps either call replace_placeholders in more places,
or we could change where we set CONSTRUCTOR_PLACEHOLDER_BOUNDARY. This patch
takes this latter approach -- when building up an array initializer, we now
bubble any CONSTRUCTOR_PLACEHOLDER_BOUNDARY flag from the element initializers
up to the array initializer so that the boundary doesn't later impede us when we
call replace_placeholders from store_init_value.
Besides fixing the kind of code like in the testcase, this shouldn't cause any
other differences in PLACEHOLDER_EXPR resolution because we don't create or use
PLACEHOLDER_EXPRs of array type in the frontend, as far as I can tell.
gcc/cp/ChangeLog:
PR c++/90996
* tree.c (replace_placeholders): Look through all handled components,
not just COMPONENT_REFs.
* typeck2.c (process_init_constructor_array): Propagate
CONSTRUCTOR_PLACEHOLDER_BOUNDARY up from each element initializer to
the array initializer.
The following testcases are miscompiled, because expand_vec_perm_pshufb
incorrectly thinks it can use vpshufb instruction for the permutations
when it can't.
The
if (vmode == V32QImode)
{
/* vpshufb only works intra lanes, it is not
possible to shuffle bytes in between the lanes. */
for (i = 0; i < nelt; ++i)
if ((d->perm[i] ^ i) & (nelt / 2))
return false;
}
intra-lane check which is correct has been copied and adjusted for 64-byte
modes into:
if (vmode == V64QImode)
{
/* vpshufb only works intra lanes, it is not
possible to shuffle bytes in between the lanes. */
for (i = 0; i < nelt; ++i)
if ((d->perm[i] ^ i) & (nelt / 4))
return false;
}
which is not correct, because 64-byte modes have 4 lanes rather than just
two and the above is only testing that the permutation grabs even lane elts
from even lanes and odd lane elts from odd lanes, but not that they are
from the same 256-bit half.
The following patch fixes it by using 3 * nelt / 4 instead of nelt / 4,
so we actually check the most significant 2 bits rather than just one.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR target/94509
* config/i386/i386-expand.c (expand_vec_perm_pshufb): Fix the check
for inter-lane permutation for 64-byte modes.
* gcc.target/i386/avx512bw-pr94509-1.c: New test.
* gcc.target/i386/avx512bw-pr94509-2.c: New test.
We need to set OMP_PARALLEL_COMBINED only if the parsing of omp_master
succeeded, because otherwise there is no nested master construct in the
parallel.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR c++/94512
* c-parser.c (c_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
if c_parser_omp_master succeeded.
* parser.c (cp_parser_omp_parallel): Set OMP_PARALLEL_COMBINED
if cp_parser_omp_master succeeded.
The following testcase ICEs on aarch64 apparently since the introduction of
the aarch64 port. The reason is that the {ashl,ashr,lshr}<mode>3 expanders
completely unnecessarily FAIL; if operands[2] is something other than
a CONST_INT or REG or MEM and the middle-end code can't cope with the
pattern giving up in these cases. All the expanders use general_operand
predicate for the shift amount operand, but then have just a special case
for CONST_INT (if in-bound, emit an immediate shift, otherwise force into
REG), or MEM (force into REG), or REG (that is the case it handles).
In the testcase, operands[2] is a lowpart SUBREG of a REG, which is valid
general_operand.
I don't see any reason what is magic about MEMs that it should be forced
into REG and others like SUBREGs that it shouldn't, there isn't even a
reason to check for !REG_P because force_reg will do nothing if the operand
is already a REG, and otherwise can handle general_operand just fine.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR target/94488
* config/aarch64/aarch64-simd.md (ashl<mode>3, lshr<mode>3,
ashr<mode>3): Force operands[2] into reg whenever it is not CONST_INT.
Assume it is a REG after that instead of testing it and doing FAIL
otherwise. Formatting fix.
Jakub Jelinek [Tue, 7 Apr 2020 06:27:49 +0000 (08:27 +0200)]
i386: Fix emit_reduc_half on V{64Q,32H}Imode [PR94500]
The following testcase is miscompiled in 8.x, because emit_reduc_half is
prepared to handle for 512-bit modes only i equal to 512, 256, 128 and 64.
V32HImode also needs i equal to 32 and V64QImode i equal to 32 and 16,
but emit_reduc_half in that case performs a redundant permutation exactly
like i == 32. In 9+ the testcase works because Richard in r9-3393
changed the reduc_* expanders so that they actually don't call
ix86_expand_reduc on 512-bit modes, but only 128-bit ones.
The patch fixes emit_reduc_half to handle also i of 32 and 16 similarly to
how V32QImode/V16HImode are handled for AVX2. I think it shouldn't hurt
to fix the function even on the trunk and 9 branch even when nothing uses
it ATM.
2020-04-07 Jakub Jelinek <jakub@redhat.com>
PR target/94500
* config/i386/i386-expand.c (emit_reduc_half): For V{64QI,32HI}mode
handle i < 64 using avx512bw_lshrv4ti3. Formatting fixes.
Jason Merrill [Mon, 6 Apr 2020 22:19:07 +0000 (18:19 -0400)]
c++: Fix ICE with implicit operator== [PR94462]
duplicate_decls assumed that any TREE_ARTIFICIAL function at namespace scope
was a built-in function, but now in C++20 it's possible to have an
implicitly declared hidden friend operator==. We just need to move the
assert into the if condition.
gcc/cp/ChangeLog
2020-04-06 Jason Merrill <jason@redhat.com>
PR c++/94462
* decl.c (duplicate_decls): Fix handling of DECL_HIDDEN_FRIEND_P.
libgomp/test: Remove a build sysroot fix regression
Fix a problem with commit c8e759b4215b ("libgomp/test: Fix compilation
for build sysroot") that caused a regression in some standalone test
environments where testsuite/libgomp-test-support.exp is used, but the
compiler is expected to be determined by `[find_gcc]', and set the
GCC_UNDER_TEST TCL variable in testsuite/libgomp-site-extra.exp instead.
libgomp/
* configure.ac: Add testsuite/libgomp-site-extra.exp to output
files.
* configure: Regenerate.
* testsuite/libgomp-site-extra.exp.in: New file.
* testsuite/libgomp-test-support.exp.in (GCC_UNDER_TEST): Remove
variable.
* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
variable.
* testsuite/Makefile.in: Regenerate.
Fix a problem with the libatomic testsuite using a method to determine
the compiler to use resulting in the tool being different from one the
library has been built with, and causing a catastrophic failure from the
lack of a suitable `--sysroot=' option where the `--with-build-sysroot='
configuration option has been used to build the compiler resulting in
the inability to link executables.
Address this problem by providing a DejaGNU configuration file defining
the compiler to use, via the GCC_UNDER_TEST TCL variable, set from $CC
by autoconf, which will have all the required options set for the target
compiler to build executables in the environment configured, removing
failures like:
.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm
collect2: error: ld returned 1 exit status
compiler exited with status 1
FAIL: libatomic.c/atomic-compare-exchange-1.c (test for excess errors)
Excess errors:
.../bin/riscv64-linux-gnu-ld: cannot find crt1.o: No such file or directory
.../bin/riscv64-linux-gnu-ld: cannot find -lm
UNRESOLVED: libatomic.c/atomic-compare-exchange-1.c compilation failed to produce executable
and bringing overall test results for the `riscv64-linux-gnu' target
(here with the `x86_64-linux-gnu' host and RISC-V QEMU in the Linux user
emulation mode as the target board) from:
=== libatomic Summary ===
# of unexpected failures 27
# of unresolved testcases 27
to:
=== libatomic Summary ===
# of expected passes 54
libatomic/
* configure.ac: Add testsuite/libatomic-site-extra.exp to output
files.
* configure: Regenerate.
* libatomic/testsuite/libatomic-site-extra.exp.in: New file.
* testsuite/Makefile.am (EXTRA_DEJAGNU_SITE_CONFIG): New
variable.
* testsuite/Makefile.in: Regenerate.
Jakub Jelinek [Mon, 6 Apr 2020 22:27:10 +0000 (00:27 +0200)]
cselib: Fix endless cselib loop on (plus:P (reg) (const_int 0))
getopt.c hangs the compiler on h8300-elf with -O2 -g, because the
IL contains addition of constant 0, the first PLUS operand is determined
to have the SP_DERIVED_VALUE_P and the new code in cselib recurses
indefinitely on seeing SP_DERIVED_VALUE_P with locs of
(plus:P SP_DERIVED_VALUE_P (const_int 0)).
Fixed by making sure cselib_subst_to_values canonicalizes it, hashing
already hashes it the same too.
2020-04-06 Jakub Jelinek <jakub@redhat.com>
* cselib.c (cselib_subst_to_values): For SP_DERIVED_VALUE_P
+ const0_rtx return the SP_DERIVED_VALUE_P.
projects / thirdparty / gcc.git / log
