rsandifo [Thu, 15 Aug 2019 09:23:06 +0000 (09:23 +0000)]
Add missing check for BUILT_IN_MD (PR 91444)
In this PR we were passing an ordinary non-built-in function to
targetm.vectorize.builtin_md_vectorized_function, which is only
supposed to handle BUILT_IN_MD.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR middle-end/91444
* tree-vect-stmts.c (vectorizable_call): Check that the function
is a BUILT_IN_MD function before passing it to
targetm.vectorize.builtin_md_vectorized_function.
rsandifo [Thu, 15 Aug 2019 09:00:22 +0000 (09:00 +0000)]
[AArch64] Add a aarch64_sve_mode_p query
This patch adds an exported function for testing whether a mode is
an SVE mode. The ACLE will make more use of it, but there's already
one place that can benefit.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_sve_mode_p): Declare.
* config/aarch64/aarch64.c (aarch64_sve_mode_p): New function.
(aarch64_select_early_remat_modes): Use it.
rsandifo [Thu, 15 Aug 2019 08:57:29 +0000 (08:57 +0000)]
[AArch64] Fix predicate alignment for fixed-length SVE
aarch64_simd_vector_alignment was only giving predicates 16-bit
alignment in VLA mode, not VLS mode. I think the problem is latent
because we can't yet create an ABI predicate type, but it seemed worth
fixing in a standalone patch rather than as part of the main ACLE series.
The ACLE patches have tests for this.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_simd_vector_alignment): Return
16 for SVE predicates even if they are fixed-length.
rsandifo [Thu, 15 Aug 2019 08:52:28 +0000 (08:52 +0000)]
[AArch64] Pass a pattern to aarch64_output_sve_cnt_immediate
This patch makes us always pass an explicit vector pattern to
aarch64_output_sve_cnt_immediate, rather than assuming it's ALL.
The ACLE patches need to be able to pass in other values.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take
the vector pattern as an aarch64_svpattern argument. Update the
overloaded caller accordingly.
(aarch64_output_sve_scalar_inc_dec): Update call accordingly.
(aarch64_output_sve_vector_inc_dec): Likewise.
rsandifo [Thu, 15 Aug 2019 08:50:00 +0000 (08:50 +0000)]
[AArch64] Optimise aarch64_add_offset for SVE VL constants
aarch64_add_offset contains code to decompose all SVE VL-based constants
into native operations. The worst-case fallback is to load the number
of SVE elements into a register and use a general multiplication.
This patch improves that fallback by reusing expand_mult if
can_create_pseudo_p, rather than emitting a MULT pattern directly.
In order to increase the chances of being able to use a simple
add-and-shift, the patch also tries to compute VG * the lowest set
bit of the multiplier, rather than always using CNTD as the basis
for the multiplication path.
This is tested by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_add_offset): In the fallback
multiplication case, try to compute VG * (lowest set bit) directly
rather than always basing the multiplication on VG. Use
expand_mult for the multiplication if we can.
gcc/testsuite/
* gcc.target/aarch64/sve/loop_add_4.c: Expect 10 INCWs and
INCDs rather than 8.
rsandifo [Thu, 15 Aug 2019 08:47:25 +0000 (08:47 +0000)]
[AArch64] Rework SVE INC/DEC handling
The scalar addition patterns allowed all the VL constants that
ADDVL and ADDPL allow, but wrote the instructions as INC or DEC
if possible (i.e. adding or subtracting a number of elements * [1, 16]
when the source and target registers the same). That works for the
cases that the autovectoriser needs, but there are a few constants
that INC and DEC can handle but ADDPL and ADDVL can't. E.g.:
inch x0, all, mul #9
is not a multiple of the number of bytes in an SVE register, and so
can't use ADDVL. It represents 36 times the number of bytes in an
SVE predicate, putting it outside the range of ADDPL.
This patch therefore adds separate alternatives for INC and DEC,
tied to a new Uai constraint. It also adds an explicit "scalar"
or "vector" to the function names, to avoid a clash with the
existing support for vector INC and DEC.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
(aarch64_output_sve_scalar_inc_dec): Declare.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.
* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
(aarch64_output_sve_scalar_inc_dec): New functions.
(aarch64_output_sve_addvl_addpl): Remove the base and offset
arguments. Only handle true ADDVL and ADDPL instructions;
don't emit an INC or DEC.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
(aarch64_sve_plus_immediate): New predicates.
(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
rather than aarch64_sve_addvl_addpl_immediate.
(aarch64_sve_inc_dec_immediate): Rename to...
(aarch64_sve_vector_inc_dec_immediate): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
(aarch64_sve_add_operand): Update accordingly.
* config/aarch64/constraints.md (Uai): New constraint.
(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
operand into a register if it satisfies aarch64_sve_plus_immediate.
(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
for Uai. Update calls to aarch64_output_sve_addvl_addpl.
* config/aarch64/aarch64-sve.md (add<mode>3): Call
aarch64_output_sve_vector_inc_dec instead of
aarch64_output_sve_inc_dec_immediate.
rsandifo [Thu, 15 Aug 2019 08:43:36 +0000 (08:43 +0000)]
[AArch64] Rework SVE REV[BHW] patterns
The current SVE REV patterns follow the AArch64 scheme, in which
UNSPEC_REV<NN> reverses elements within an <NN>-bit granule.
E.g. UNSPEC_REV64 on VNx8HI reverses the four 16-bit elements
within each 64-bit granule.
The native SVE scheme is the other way around: UNSPEC_REV64 is seen
as an operation on 64-bit elements, with REVB swapping bytes within
the elements, REVH swapping halfwords, and so on. This fits SVE more
naturally because the operation can then be predicated per <NN>-bit
granule/element.
Making the patterns use the Advanced SIMD scheme was more natural
when all we cared about were permutes, since we could then use
the source and target of the permute in their original modes.
However, the ACLE does need patterns that follow the native scheme,
treating them as operations on integer elements. This patch defines
the patterns that way instead and updates the existing uses to match.
This also brings in a couple of helper routines from the ACLE branch.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (UNSPEC_REVB, UNSPEC_REVH)
(UNSPEC_REVW): New constants.
(elem_bits): New mode attribute.
(SVE_INT_UNARY): New int iterator.
(optab): Handle UNSPEC_REV[BHW].
(sve_int_op): New int attribute.
(min_elem_bits): Handle VNx16QI and the predicate modes.
* config/aarch64/aarch64-sve.md (*aarch64_sve_rev64<mode>)
(*aarch64_sve_rev32<mode>, *aarch64_sve_rev16vnx16qi): Delete.
(@aarch64_pred_<SVE_INT_UNARY:optab><SVE_I:mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_sve_data_mode): New function.
(aarch64_sve_int_mode, aarch64_sve_rev_unspec): Likewise.
(aarch64_split_sve_subreg_move): Use UNSPEC_REV[BHW] instead of
unspecs based on the total width of the reversed data.
(aarch64_evpc_rev_local): Likewise (for SVE only). Use a
reinterpret followed by a subreg on big-endian targets.
gcc/testsuite/
* gcc.target/aarch64/sve/revb_1.c: Restrict to little-endian targets.
Avoid including stdint.h.
* gcc.target/aarch64/sve/revh_1.c: Likewise.
* gcc.target/aarch64/sve/revw_1.c: Likewise.
* gcc.target/aarch64/sve/revb_2.c: New big-endian test.
* gcc.target/aarch64/sve/revh_2.c: Likewise.
* gcc.target/aarch64/sve/revw_2.c: Likewise.
rsandifo [Thu, 15 Aug 2019 08:39:42 +0000 (08:39 +0000)]
[AArch64] Add more SVE FMLA and FMAD /z alternatives
This patch makes the floating-point conditional FMA patterns provide the
same /z alternatives as the integer patterns added by a previous patch.
We can handle cases in which individual inputs are allocated to the same
register as the output, so we don't need to force all registers to be
different.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
alternatives in which one of the inputs is in the same register
as the output.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
and FMSB as well as FMLS.
rsandifo [Thu, 15 Aug 2019 08:37:14 +0000 (08:37 +0000)]
[AArch64] Add MOVPRFX alternatives for SVE EXT patterns
We use EXT both to implement vec_extract for large indices and as a
permute. In both cases we can use MOVPRFX to handle the case in which
the first input and output can't be tied.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
rsandifo [Thu, 15 Aug 2019 08:34:40 +0000 (08:34 +0000)]
[AArch64] Remove unneeded FSUB alternatives and add a new one
The floating-point subtraction patterns don't need to handle
subtraction of constants, since those go through the addition
patterns instead. There was a missing MOVPRFX alternative for
FSUBR though.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR.
rsandifo [Thu, 15 Aug 2019 08:29:11 +0000 (08:29 +0000)]
[AArch64] Use SVE reversed shifts in preference to MOVPRFX
This patch makes us use reversed SVE shifts when the first operand
can't be tied to the output but the second can. This is tested
more thoroughly by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3):
Add an alternative that uses reversed shifts.
ktkachov [Thu, 15 Aug 2019 08:26:50 +0000 (08:26 +0000)]
[aarch64] Use neoversen1 tuning struct for -mcpu=cortex-a76
The neoversen1 tuning struct gives better performance on the Cortex-A76, so use that.
The only difference from the current tuning is the function and label alignment settings.
This gives about 1.3% improvement on SPEC2006 int and 0.3% on SPEC2006 fp.
* config/aarch64/aarch64-cores.def (cortex-a76): Use neoversen1 tuning
struct.
rsandifo [Thu, 15 Aug 2019 08:22:07 +0000 (08:22 +0000)]
[AArch64] Use SVE MLA, MLS, MAD and MSB for conditional arithmetic
This patch uses predicated MLA, MLS, MAD and MSB to implement
conditional "FMA"s on integers. This also requires providing
the unpredicated optabs (fma and fnma) since otherwise
tree-ssa-math-opts.c won't try to use the conditional forms.
We still want to use shifts and adds in preference to multiplications,
so the patch makes the optab expanders check for that.
The tests cover floating-point types too, which are already handled,
and which were already tested to some extent by gcc.dg/vect.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
rsandifo [Thu, 15 Aug 2019 08:18:03 +0000 (08:18 +0000)]
[AArch64] Use SVE binary immediate instructions for conditional arithmetic
This patch lets us use the immediate forms of FADD, FSUB, FSUBR,
FMUL, FMAXNM and FMINNM for conditional arithmetic. (We already
use them for normal unconditional arithmetic.)
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64.c (aarch64_print_vector_float_operand):
Print 2.0 naturally.
(aarch64_sve_float_mul_immediate_p): Return true for 2.0.
* config/aarch64/predicates.md
(aarch64_sve_float_negated_arith_immediate): New predicate,
renamed from aarch64_sve_float_arith_with_sub_immediate.
(aarch64_sve_float_arith_with_sub_immediate): Test for both
positive and negative constants.
(aarch64_sve_float_arith_with_sub_operand): Redefine as a register
or an aarch64_sve_float_arith_with_sub_immediate.
* config/aarch64/constraints.md (vsN): Use
aarch64_sve_float_negated_arith_immediate.
* config/aarch64/iterators.md (SVE_COND_FP_BINARY_I1): New int
iterator.
(sve_pred_fp_rhs2_immediate): New int attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>): Use
sve_pred_fp_rhs1_operand and sve_pred_fp_rhs2_operand.
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_2_const)
(*cond_<SVE_COND_FP_BINARY_I1:optab><SVE_F:mode>_any_const)
(*cond_add<SVE_F:mode>_2_const, *cond_add<SVE_F:mode>_any_const)
(*cond_sub<mode>_3_const, *cond_sub<mode>_any_const): New patterns.
rsandifo [Thu, 15 Aug 2019 08:12:41 +0000 (08:12 +0000)]
[AArch64] Use SVE FABD in conditional arithmetic
This patch extends the FABD support so that it handles conditional
arithmetic. We're relying on combine for this, since there's no
associated IFN_COND_* (yet?).
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_abd<SVE_F:mode>_2)
(*aarch64_cond_abd<SVE_F:mode>_3)
(*aarch64_cond_abd<SVE_F:mode>_any): New patterns.
rsandifo [Thu, 15 Aug 2019 08:08:49 +0000 (08:08 +0000)]
[AArch64] Use SVE [SU]ABD in conditional arithmetic
This patch extends the [SU]ABD support so that it handles
conditional arithmetic. We're relying on combine for this,
since there's no associated IFN_COND_* (yet?).
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*aarch64_cond_<su>abd<mode>_2)
(*aarch64_cond_<su>abd<mode>_any): New patterns.
rsandifo [Thu, 15 Aug 2019 08:05:50 +0000 (08:05 +0000)]
Add support for conditional shifts
This patch adds support for IFN_COND shifts left and shifts right.
This is mostly mechanical, but since we try to handle conditional
operations in the same way as unconditional operations in match.pd,
we need to support IFN_COND shifts by scalars as well as vectors.
E.g.:
IFN_COND_SHL (cond, a, { 1, 1, ... }, fallback)
and:
IFN_COND_SHL (cond, a, 1, fallback)
are the same operation, with:
(for shiftrotate (lrotate rrotate lshift rshift)
...
/* Prefer vector1 << scalar to vector1 << vector2
if vector2 is uniform. */
(for vec (VECTOR_CST CONSTRUCTOR)
(simplify
(shiftrotate @0 vec@1)
(with { tree tem = uniform_vector_p (@1); }
(if (tem)
(shiftrotate @0 { tem; }))))))
preferring the latter. The patch copes with this by extending
create_convert_operand_from to handle scalar-to-vector conversions.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
marxin [Thu, 15 Aug 2019 06:58:09 +0000 (06:58 +0000)]
Properly register dead cgraph_nodes in passes.c.
2019-08-15 Martin Liska <mliska@suse.cz>
PR ipa/91404
* passes.c (order): Remove.
(uid_hash_t): Likewise).
(remove_cgraph_node_from_order): Remove from set
of pointers (cgraph_node *).
(insert_cgraph_node_to_order): New.
(duplicate_cgraph_node_to_order): New.
(do_per_function_toporder): Register all 3 cgraph hooks.
Skip removed_nodes now as we know about all of them.
redi [Wed, 14 Aug 2019 19:52:58 +0000 (19:52 +0000)]
PR c++/91436 fix C++ dialect for std::make_unique fix-it hint
The std::make_unique function wasn't added until C++14, and neither was
the std::complex_literals namespace.
gcc/cp:
PR c++/91436
* name-lookup.c (get_std_name_hint): Fix min_dialect field for
complex_literals and make_unique entries.
gcc/testsuite:
PR c++/91436
* g++.dg/lookup/missing-std-include-5.C: Limit test to C++14 and up.
* g++.dg/lookup/missing-std-include-6.C: Don't check make_unique in
test that runs for C++11.
* g++.dg/lookup/missing-std-include-8.C: Check make_unique here.
uros [Wed, 14 Aug 2019 18:43:16 +0000 (18:43 +0000)]
* config/i386/i386-expand.c (ix86_expand_vector_init_one_nonzero)
<case E_V8QImode>: Use vector_set path for
TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
(ix86_expand_vector_init_one_nonzero) <case E_V8QImode>:
Do not widen for TARGET_MMX_WITH_SSE && TARGET_SSE4_1.
mpolacek [Wed, 14 Aug 2019 14:44:55 +0000 (14:44 +0000)]
PR c++/91391 - bogus -Wcomma-subscript warning.
* parser.c (cp_parser_postfix_open_square_expression): Don't warn about
a deprecated comma here. Pass warn_comma_subscript down to
cp_parser_expression.
(cp_parser_expression): New bool parameter. Warn about uses of a comma
operator within a subscripting expression.
(cp_parser_skip_to_closing_square_bracket): Revert to pre-r274121 state.
(cp_parser_skip_to_closing_square_bracket_1): Remove.
clyon [Wed, 14 Aug 2019 13:14:59 +0000 (13:14 +0000)]
Add generic support for noinit attribute.
Similar to what already exists for TI msp430 or in TI compilers for
arm, this patch adds support for the "noinit" attribute.
It is convenient for embedded targets where the user wants to keep the
value of some data when the program is restarted: such variables are
not zero-initialized. It is mostly a helper/shortcut to placing
variables in a dedicated section.
It's probably desirable to add the following chunk to the GNU linker:
diff --git a/ld/emulparams/armelf.sh b/ld/emulparams/armelf.sh
index 272a8bc..9555cec 100644
--- a/ld/emulparams/armelf.sh
+++ b/ld/emulparams/armelf.sh
@@ -10,7 +10,19 @@ OTHER_TEXT_SECTIONS='*(.glue_7t) *(.glue_7)
*(.vfp11_veneer) *(.v4_bx)'
OTHER_BSS_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__bss_start__ =
.${CREATE_SHLIB+)};"
OTHER_BSS_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}_bss_end__ =
.${CREATE_SHLIB+)}; ${CREATE_SHLIB+PROVIDE (}__bss_end__ =
.${CREATE_SHLIB+)};"
OTHER_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__end__ = .${CREATE_SHLIB+)};"
-OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
+OTHER_SECTIONS='
+.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /* This section contains data that is not initialised during load
+ *or* application reset. */
+ .noinit (NOLOAD) :
+ {
+ . = ALIGN(2);
+ PROVIDE (__noinit_start = .);
+ *(.noinit)
+ . = ALIGN(2);
+ PROVIDE (__noinit_end = .);
+ }
+'
so that the noinit section has the "NOLOAD" flag.
I added a testcase if gcc.c-torture/execute, gated by the new noinit
effective-target.
Finally, I tested on arm-eabi, but not on msp430 for which I do not
have the environment.
rguenth [Wed, 14 Aug 2019 12:04:05 +0000 (12:04 +0000)]
2019-08-14 Richard Biener <rguenther@suse.de>
Uroš Bizjak <ubizjak@gmail.com>
PR target/91154
* config/i386/i386-features.h (scalar_chain::scalar_chain): Add
mode arguments.
(scalar_chain::smode): New member.
(scalar_chain::vmode): Likewise.
(dimode_scalar_chain): Rename to...
(general_scalar_chain): ... this.
(general_scalar_chain::general_scalar_chain): Take mode arguments.
(timode_scalar_chain::timode_scalar_chain): Initialize scalar_chain
base with TImode and V1TImode.
* config/i386/i386-features.c (scalar_chain::scalar_chain): Adjust.
(general_scalar_chain::vector_const_cost): Adjust for SImode
chains.
(general_scalar_chain::compute_convert_gain): Likewise. Add
{S,U}{MIN,MAX} support.
(general_scalar_chain::replace_with_subreg): Use vmode/smode.
(general_scalar_chain::make_vector_copies): Likewise. Handle
non-DImode chains appropriately.
(general_scalar_chain::convert_reg): Likewise.
(general_scalar_chain::convert_op): Likewise.
(general_scalar_chain::convert_insn): Likewise. Add
fatal_insn_not_found if the result is not recognized.
(convertible_comparison_p): Pass in the scalar mode and use that.
(general_scalar_to_vector_candidate_p): Likewise. Rename from
dimode_scalar_to_vector_candidate_p. Add {S,U}{MIN,MAX} support.
(scalar_to_vector_candidate_p): Remove by inlining into single
caller.
(general_remove_non_convertible_regs): Rename from
dimode_remove_non_convertible_regs.
(remove_non_convertible_regs): Remove by inlining into single caller.
(convert_scalars_to_vector): Handle SImode and DImode chains
in addition to TImode chains.
* config/i386/i386.md (<maxmin><MAXMIN_IMODE>3): New expander.
(*<maxmin><MAXMIN_IMODE>3_1): New insn-and-split.
(*<maxmin>di3_doubleword): Likewise.
rsandifo [Wed, 14 Aug 2019 11:00:45 +0000 (11:00 +0000)]
[AArch64] Use SVE UXT[BHW] as a form of predicated AND
UXTB, UXTH and UXTW are equivalent to predicated ANDs with the constants
0xff, 0xffff and 0xffffffff respectively. This patch uses them in the
patterns for IFN_COND_AND.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_print_operand): Allow %e to
take the equivalent mask, as well as a bit count.
* config/aarch64/predicates.md (aarch64_sve_uxtb_immediate)
(aarch64_sve_uxth_immediate, aarch64_sve_uxt_immediate)
(aarch64_sve_pred_and_operand): New predicates.
* config/aarch64/iterators.md (sve_pred_int_rhs2_operand): New
code attribute.
* config/aarch64/aarch64-sve.md
(cond_<SVE_INT_BINARY:optab><SVE_I:mode>): Use it.
(*cond_uxt<mode>_2, *cond_uxt<mode>_any): New patterns.
rsandifo [Wed, 14 Aug 2019 10:56:57 +0000 (10:56 +0000)]
[AArch64] Add SVE conditional conversion patterns
This patch adds patterns to match conditional conversions between
integers and like-sized floats. The patterns are actually more
general than that, but the other combinations can only be tested
via the ACLE.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FCVTI:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
(*cond_<SVE_COND_ICVTF:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>):
New patterns.
rsandifo [Wed, 14 Aug 2019 10:53:10 +0000 (10:53 +0000)]
[AArch64] Add SVE conditional floating-point unary patterns
This patch adds patterns to match conditional unary operations
on floating-point modes. At the moment we rely on combine to merge
separate arithmetic and vcond_mask operations, and since the latter
doesn't accept zero operands, we miss out on the opportunity to use
the movprfx /z alternative. (This alternative is tested by the ACLE
patches though.)
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_2): New pattern.
(*cond_<SVE_COND_FP_UNARY:optab><SVE_F:mode>_any): Likewise.
rsandifo [Wed, 14 Aug 2019 10:48:50 +0000 (10:48 +0000)]
[AArch64] Add SVE conditional integer unary patterns
This patch adds patterns to match conditional unary operations
on integers. At the moment we rely on combine to merge separate
arithmetic and vcond_mask operations, and since the latter doesn't
accept zero operands, we miss out on the opportunity to use the
movprfx /z alternative. (This alternative is tested by the ACLE
patches though.)
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_2): New pattern.
(*cond_<SVE_INT_UNARY:optab><SVE_I:mode>_any): Likewise.
pmderodat [Wed, 14 Aug 2019 09:52:58 +0000 (09:52 +0000)]
[Ada] Improve performance of Containers.Functional_Base
This patch modifies the implementation of Functional_Base to damp the
cost of its subprograms at runtime in specific cases. Instead of copying
the entire underlying array to create a new container, containers can
share the same Array_Base attribute. Performance on common use cases of
formal and functional containers is improved with this patch.
2019-08-14 Joffrey Huguet <huguet@adacore.com>
gcc/ada/
* libgnat/a-cofuba.ads: Add a Length attribute to type
Container. Add a type Array_Base which replaces the previous
Elements attribute of Container.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
* libgnat/a-cofuba.adb (Resize): New subprogram. It is used to
resize the underlying array of a container if necessary.
(=, <=, Find, Get, Intersection, Length, Num_Overlaps, Set,
Union): Update to match changes in type declarations.
(Add): Modify body to damp the time and space cost in a specific
case.
(Content_Init): New subprogram. It is used to initialize the
Base attribute of Container.
(Remove): Modify body to damp the time and space cost in a
specific case.
pmderodat [Wed, 14 Aug 2019 09:52:54 +0000 (09:52 +0000)]
[Ada] Alignment may be specified as zero
An Alignment clause or an aspect_specification for Alignment may be
specified as 0, which is treated the same as 1.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_ch13.adb (Get_Alignment_Value): Return 1 for Alignment 0,
and do not give an error.
* doc/gnat_rm/representation_clauses_and_pragmas.rst: Update the
corresponding documentation.
* gnat_rm.texi: Regenerate.
pmderodat [Wed, 14 Aug 2019 09:52:39 +0000 (09:52 +0000)]
[Ada] Do not crash with -gnatR3 on Ghost aspects
2019-08-14 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* sem_aux.adb (Next_Rep_Item): If a node in the rep chain
involves a Ghost aspect it may have been replaced by a null
statement; use the original node to find next Rep_Item.
* repinfo.adb (List_Entities): Do not list an Ignored
Ghost_Entity, for which information may have been deleted.
pmderodat [Wed, 14 Aug 2019 09:52:34 +0000 (09:52 +0000)]
[Ada] Warn about unknown condition in Compile_Time_Warning
The compiler now warns if the condition in a pragma Compile_Time_Warning
or Compile_Time_Error does not have a compile-time-known value. The
warning is not given for pragmas in a generic template, but is given for
pragmas in an instance.
The -gnatw_c and -gnatw_C switches turn the warning on and off. The
default is on.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_prag.ads, sem_prag.adb
(Process_Compile_Time_Warning_Or_Error): In parameterless
version, improve detection of whether we are in a generic unit
to cover the case of an instance within a generic unit.
(Process_Compile_Time_Warning_Or_Error): Rename the
two-parameter version to be
Validate_Compile_Time_Warning_Or_Error, and do not export it.
Issue a warning if the condition is not known at compile time.
The key point is that the warning must be given only for pragmas
deferred to the back end, because the back end discovers
additional values that are known at compile time. Previous
changes in this ticket have enabled this by deferring to the
back end without checking for special cases such as 'Size.
(Validate_Compile_Time_Warning_Or_Error): Rename to be
Defer_Compile_Time_Warning_Error_To_BE.
* warnsw.ads, warnsw.adb (Warn_On_Unknown_Compile_Time_Warning):
Add new switches -gnatw_c and -gnatw_C to control the above
warning.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Document new switches.
* gnat_ugn.texi: Regenerate.
pmderodat [Wed, 14 Aug 2019 09:52:24 +0000 (09:52 +0000)]
[Ada] Incorrect error on inline protected function
This patch fixes a bug where if a protected function has a pragma
Inline, and has no local variables, and the body consists of a single
extended_return_statement, and the result type is an indefinite
composite subtype, and inlining is enabled, the compiler gives an error,
even though the program is legal.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* inline.adb (Check_And_Split_Unconstrained_Function): Ignore
protected functions to get rid of spurious error. The
transformation done by this procedure triggers legality errors
in the generated code in this case.
gcc/testsuite/
* gnat.dg/inline19.adb, gnat.dg/inline19.ads: New testcase.
pmderodat [Wed, 14 Aug 2019 09:52:20 +0000 (09:52 +0000)]
[Ada] Defer processing of unknown CTW/E conditions to the back end
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_prag.adb (Process_Compile_Time_Warning_Or_Error): Defer
processing to the back end in all cases where the pragma's
condition is not known at compile time during the front end
(except in generics), as opposed to detecting 'Size attributes
and the like. This ensures that we take advantage of whatever
can be compile-time known after running the back end, as opposed
to having the front end guess what the back end can do. Remove
a little duplicated code at the call site.
* gnat1drv.adb (Post_Compilation_Validation_Checks): Unlock the
Elists while in Validate_Compile_Time_Warning_Errors, because it
does analysis and name resolution, which sometimes involves
adding Elists.
pmderodat [Wed, 14 Aug 2019 09:52:15 +0000 (09:52 +0000)]
[Ada] Compiler speedup with inlining across units
This change is aimed at speeding up the inlining across units done by
the Ada compiler when -gnatn is specified and in the presence of units
instantiating a lot of generic packages.
The current implementation is as follows: when a generic package is
being instantiated, the compiler scans its spec for the presence of
subprograms with an aspect/pragma Inline and, upon finding one,
schedules the instantiation of its body. That's not very efficient
because the compiler doesn't know yet if one of those inlined
subprograms will eventually be called from the main unit.
The new implementation arranges for the compiler to instantiate the body
on demand, i.e. when it encounters a call to one of the inlined
subprograms. That's still not optimal because, at this point, the
compiler has not yet computed whether the call itself is reachable from
the main unit (it will do this computation at the very end of the
processing, just before sending the inlined units to the code generator)
but that's nevertheless a net progress.
The patch also enhances the -gnatd.j option to make it output the list
of instances "inlined" this way. The following package is a simple
example:
with Q;
procedure P is
begin
Q.Proc;
end;
package Q is
procedure Proc;
pragma Inline (Proc);
end Q;
with G;
package body Q is
package My_G is new G (1);
procedure Proc is
Val : constant Integer := My_G.Func;
begin
if Val /= 1 then
raise Program_Error;
end if;
end;
end Q;
generic
Value : Integer;
package G is
function Func return Integer;
pragma Inline (Func);
end G;
package body G is
function Func return Integer is
begin
return Value;
end;
end G;
2019-08-14 Eric Botcazou <ebotcazou@adacore.com>
gcc/ada/
* einfo.ads (Is_Called): Document new usage on E_Package
entities.
* einfo.adb (Is_Called): Accept E_Package entities.
(Set_Is_Called): Likewise.
* exp_ch6.adb (Expand_Call_Helper): Move code dealing with
instances for back-end inlining to Add_Inlined_Body.
* inline.ads: Remove with clauses for Alloc and Table.
(Pending_Instantiations): Move to...
* inline.adb: Add with clauses for Alloc, Uintp, Table and
GNAT.HTable.
(Backend_Instances): New variable.
(Pending_Instantiations): ...here.
(Called_Pending_Instantiations): New table.
(Node_Table_Size): New constant.
(Node_Header_Num): New subtype.
(Node_Hash): New function.
(To_Pending_Instantiations): New hash table.
(Add_Inlined_Body): Bail out early for subprograms in the main
unit or subunit. Likewise if the Is_Called flag is set. If the
subprogram is an instance, invoke Add_Inlined_Instance. Call
Set_Is_Called earlier. If the subrogram is within an instance,
invoke Add_Inlined_Instance. Also deal with the case where the
call itself is within an instance.
(Add_Inlined_Instance): New procedure.
(Add_Inlined_Subprogram): Remove conditions always fulfilled.
(Add_Pending_Instantiation): Move the defence against ludicruous
number of instantiations to here. When back-end inlining is
enabled, associate an instantiation with its index in table and
mark a few selected kinds of instantiations as always needed.
(Initialize): Set Backend_Instances to No_Elist.
(Instantiate_Body): New procedure doing the work extracted
from...
(Instantiate_Bodies): ...here. When back-end inlining is
enabled, loop over Called_Pending_Instantiations instead of
Pending_Instantiations.
(Is_Nested): Minor tweak.
(List_Inlining_Info): Also list the contents of
Backend_Instances.
* sem_ch12.adb (Might_Inline_Subp): Return early if Is_Inlined
is set and otherwise set it before returning true.
(Analyze_Package_Instantiation): Remove the defence against
ludicruous number of instantiations. Invoke
Remove_Dead_Instance instead of doing the removal manually if
there is a guaranteed ABE.
pmderodat [Wed, 14 Aug 2019 09:52:10 +0000 (09:52 +0000)]
[Ada] Equality for nonabstract type derived from interface treated as abstract
The compiler was creating an abstract function for the equality
operation of a (nonlimited) interface type, and that could result in
errors on generic instantiations that are passed nonabstract types
derived from the interface type along with the derived type's inherited
equality operation (complaining about an abstract subprogram being
passed to a nonabstract formal). The "=" operation of an interface is
supposed to be nonabstract (a direct consequence of the rule in RM
4.5.2(6-7)), so we now create an expression function rather than an
abstract function. The function returns False, but the result is
unimportant since a function of an abstract type can never actually be
invoked (its arguments must generally be class-wide, since there can be
no objects of the type, and calling it will dispatch).
2019-08-14 Gary Dismukes <dismukes@adacore.com>
gcc/ada/
* exp_ch3.adb (Predef_Spec_Or_Body): For an equality operation
of an interface type, create an expression function (that
returns False) rather than declaring an abstract function.
* freeze.adb (Check_Inherited_Conditions): Set Needs_Wrapper to
False unconditionally at the start of the loop creating wrappers
for inherited operations.
gcc/testsuite/
* gnat.dg/equal11.adb, gnat.dg/equal11_interface.ads,
gnat.dg/equal11_record.adb, gnat.dg/equal11_record.ads: New
testcase.
pmderodat [Wed, 14 Aug 2019 09:52:06 +0000 (09:52 +0000)]
[Ada] Strengthen Locked flag
This patch strengthens the Locked flag, by Asserting that it is False on
operations that might cause reallocation.
No change in behavior (except in the presence of compiler bugs), so no
test.
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* table.adb: Assert that the table is not locked when increasing
Last, even if it doesn't cause reallocation. In other words,
assert that on operations that MIGHT cause reallocation.
* table.ads: Fix comment accordingly.
pmderodat [Wed, 14 Aug 2019 09:51:57 +0000 (09:51 +0000)]
[Ada] Tweak the sloc of Compile_Time_Warning warnings
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem_prag.adb (Validate_Compile_Time_Warning_Error): Attach the
warning to the Sloc of the first pragma argument, rather than to
the pragma itself. This is to make pragmas processed after the
back end use the same Sloc as pragmas processed earlier, in the
front end. There's no reason for this discrepancy, and it
hinders further work on this ticket.
pmderodat [Wed, 14 Aug 2019 09:51:52 +0000 (09:51 +0000)]
[Ada] Minor: remove a ??? comment
Minor: remove the ??? comment for the Inside_A_Generic flag. The current
name is clear and concise, even though we are noun-ing the adjective
"generic".
2019-08-14 Bob Duff <duff@adacore.com>
gcc/ada/
* sem.ads (Inside_A_Generic): Remove the ??? comment.
pmderodat [Wed, 14 Aug 2019 09:51:39 +0000 (09:51 +0000)]
[Ada] Fix internal error on inlined subprogram instance
This fixes a long-standing oddity in the procedure analyzing the
instantiation of a generic subprogram, which would set the
Is_Generic_Instance flag on the enclosing package generated for the
instantiation but only to reset it a few lines below. Now this flag is
relied upon by the machinery which computes the set of public entities
to be exposed by a package.
2019-08-14 Eric Botcazou <ebotcazou@adacore.com>
gcc/ada/
* sem_ch12.adb (Analyze_Instance_And_Renamings): Do not reset
the Is_Generic_Instance flag previously set on the package
generated for the instantiation of a generic subprogram.
gcc/testsuite/
* gnat.dg/generic_inst11.adb, gnat.dg/generic_inst11_pkg.adb,
gnat.dg/generic_inst11_pkg.ads: New testcase.
pmderodat [Wed, 14 Aug 2019 09:51:34 +0000 (09:51 +0000)]
[Ada] Crash on quantified expression in disabled assertion
The defining identifier of a quantified expression may be the freeze
point of its type. If the quantified expression appears in an assertion
that is disavbled, the freeze node for that type may appear in a tree
that will be discarded when the enclosing pragma is elaborated. To
ensure that the freeze node is reachable for subsquent uses we must
generate its freeze node explicitly when the quantified expression is
analyzed.
2019-08-14 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* exp_ch4.adb (Expand_N_Quantified_Expression): Freeze
explicitly the type of the loop parameter.
gcc/testsuite/
* gnat.dg/assert2.adb, gnat.dg/assert2.ads: New testcase.
pmderodat [Wed, 14 Aug 2019 09:51:25 +0000 (09:51 +0000)]
[Ada] Expose part of ownership checking for use in GNATprove
GNATprove needs to be able to call a subset of the ownership legality
rules from marking. This is provided by a new function
Sem_SPARK.Is_Legal.
There is no impact on compilation.
2019-08-14 Yannick Moy <moy@adacore.com>
gcc/ada/
* sem_spark.adb, sem_spark.ads (Is_Legal): New function exposed
for use in GNATprove, to test legality rules not related to
permissions.
(Check_Declaration_Legality): Extract the part of
Check_Declaration that checks rules not related to permissions.
(Check_Declaration): Call the new Check_Declaration_Legality.
(Check_Type_Legality): Rename of Check_Type. Introduce
parameters to force or not checking, and update a flag detecting
illegalities.
(Check_Node): Ignore attribute references in statement position.
pmderodat [Wed, 14 Aug 2019 09:51:21 +0000 (09:51 +0000)]
[Ada] Check SPARK restriction on Old/Loop_Entry with pointers
--#! r336866
--#! no-mail
SPARK RM rule 3.10(14) restricts the use of Old and Loop_Entry
attributes on prefixes of an owning or observing type (i.e. a type with
access inside).
There is no impact on compilation.
2019-08-14 Yannick Moy <moy@adacore.com>
gcc/ada/
* sem_spark.adb (Check_Old_Loop_Entry): New procedure to check
correct use of Old and Loop_Entry.
(Check_Node): Check subprogram contracts.
(Check_Pragma): Check Loop_Variant.
(Check_Safe_Pointers): Apply checking to library-level
subprogram declarations as well, in order to check their
contract.
pmderodat [Wed, 14 Aug 2019 09:51:16 +0000 (09:51 +0000)]
[Ada] Fix spurious ownership error in GNATprove
Like Is_Path_Expression, function Is_Subpath_Expression should consider
the possibility that the subpath is a type conversion or type
qualification over the actual subpath node. This avoids spurious
ownership errors in GNATprove.
There is no impact on compilation.
2019-08-14 Yannick Moy <moy@adacore.com>
gcc/ada/
* sem_spark.adb (Is_Subpath_Expression): Take into account
conversion and qualification.
pmderodat [Wed, 14 Aug 2019 09:51:12 +0000 (09:51 +0000)]
[Ada] Fix discrepancy in mechanism tracking private and full views
This fixes a discrepancy in the mechanism tracking the private and full
views of entities when entering and leaving scopes. This mechanism
records private entities that are dependent on other private entities,
so that the exchange done on entering and leaving scopes can be
propagated.
The propagation is done recursively on entering child units, but it was
not done recursively on leaving them, which would leave the dependency
chains in a uncertain state in this case. That's mostly visible when
inlining across units is enabled for code involving a lot of generic
units.
2019-08-14 Eric Botcazou <ebotcazou@adacore.com>
gcc/ada/
* sem_ch7.adb (Install_Private_Declarations)
<Swap_Private_Dependents>: Do not rely solely on the
Is_Child_Unit flag on the unit to recurse.
(Uninstall_Declarations) <Swap_Private_Dependents>: New
function. Use it to recurse on the private dependent entities
for child units.
pmderodat [Wed, 14 Aug 2019 09:51:00 +0000 (09:51 +0000)]
[Ada] Crash on precondition involving quantified expression
This patch fixes a compiler abort on a precondition whose condition
includes a quantified expression.
2019-08-14 Ed Schonberg <schonberg@adacore.com>
gcc/ada/
* sem_util.adb (New_Copy_Tree, Visit_Entity): A quantified
expression includes the implicit declaration of the loop
parameter. When a quantified expression is copied during
expansion, for example when building the precondition code from
the generated pragma, a new loop parameter must be created for
the new tree, to prevent duplicate declarations for the same
symbol.
gcc/testsuite/
* gnat.dg/predicate12.adb, gnat.dg/predicate12.ads: New
testcase.
pmderodat [Wed, 14 Aug 2019 09:50:55 +0000 (09:50 +0000)]
[Ada] Fix failing assertions on SPARK elaboration
Checking of SPARK elaboration rules may lead to assertion failures on a
compiler built with assertions. Now fixed.
There is no impact on compilation.
2019-08-14 Yannick Moy <moy@adacore.com>
gcc/ada/
* sem_disp.adb (Check_Dispatching_Operation): Update assertion
for the separate declarations created in GNATprove mode.
* sem_disp.ads (Is_Overriding_Subprogram): Update comment.
* sem_elab.adb (SPARK_Processor): Fix test for checking of
overriding primitives.
pmderodat [Wed, 14 Aug 2019 09:50:46 +0000 (09:50 +0000)]
[Ada] Illegal selection of first object in a task type's body not detected
The compiler was improperly allowing selection of an object declared
within a task body when the prefix was of the task type, specifically in
the case where the object was the very first declared in the body
(selections of later body declarations were being flagged). The flag
Is_Private_Op was only set at the point of the first "private"
declaration of the type in cases where the first declaration's name
didn't match the selector.
2019-08-14 Gary Dismukes <dismukes@adacore.com>
gcc/ada/
* sem_ch4.adb (Analyze_Selected_Component): In the case where
the prefix is of a concurrent type, and the selected entity
matching the selector is the first private declaration of the
type (such as the first local variable in a task's body), set
Is_Private_Op.
rguenth [Wed, 14 Aug 2019 09:38:15 +0000 (09:38 +0000)]
2019-08-14 Richard Biener <rguenther@suse.de>
PR testsuite/91419
* lib/target-supports.exp (natural_alignment_32): Amend target
list based on BIGGEST_ALIGNMENT.
(natural_alignment_64): Targets not natural_alignment_32 cannot
be natural_alignment_64.
* gcc.dg/tree-ssa/pr91091-2.c: XFAIL for !natural_alignment_32.
* gcc.dg/tree-ssa/ssa-fre-77.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-61.c: Require natural_alignment_32.
rsandifo [Wed, 14 Aug 2019 09:18:14 +0000 (09:18 +0000)]
[AArch64] Make more use of SVE conditional constant moves
This patch extends the SVE UNSPEC_SEL patterns so that they can use:
(1) MOV /M of a duplicated integer constant
(2) MOV /M of a duplicated floating-point constant bitcast to an integer,
accepting the same constants as (1)
(3) FMOV /M of a duplicated floating-point constant
(4) MOV /Z of a duplicated integer constant
(5) MOV /Z of a duplicated floating-point constant bitcast to an integer,
accepting the same constants as (4)
(6) MOVPRFXed FMOV /M of a duplicated floating-point constant
We already handled (4) with a special pattern; the rest are new.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64.c (aarch64_bit_representation): New function.
(aarch64_print_vector_float_operand): Also handle 8-bit floats.
(aarch64_print_operand): Add support for %I.
(aarch64_sve_dup_immediate_p): Handle scalars as well as vectors.
Bitcast floating-point constants to the corresponding integer constant.
(aarch64_float_const_representable_p): Handle vectors as well
as scalars.
(aarch64_expand_sve_vcond): Make sure that the operands are valid
for the new vcond_mask_<mode><vpred> expander.
* config/aarch64/predicates.md (aarch64_sve_dup_immediate): Also
test aarch64_float_const_representable_p.
(aarch64_sve_reg_or_dup_imm): New predicate.
* config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Use
gen_vcond_mask_<mode><vpred> instead of
gen_aarch64_sve_dup<mode>_const.
(vcond_mask_<mode><vpred>): Turn into a define_expand that
accepts aarch64_sve_reg_or_dup_imm and aarch64_simd_reg_or_zero
for operands 1 and 2 respectively. Force operand 2 into a
register if operand 1 is a register. Fold old define_insn...
(aarch64_sve_dup<mode>_const): ...and this define_insn...
(*vcond_mask_<mode><vpred>): ...into this new pattern. Handle
floating-point constants that can be moved as integers. Add
alternatives for MOV /M and FMOV /M.
(vcond<mode><v_int_equiv>, vcondu<mode><v_int_equiv>)
(vcond<mode><v_fp_equiv>): Accept nonmemory_operand for operands
1 and 2 respectively.
* config/aarch64/constraints.md (Ufc): Handle vectors as well
as scalars.
(vss): New constraint.
rsandifo [Wed, 14 Aug 2019 09:14:31 +0000 (09:14 +0000)]
[AArch64] Add support for SVE F{MAX,MIN}NM immediate
This patch uses the immediate forms of FMAXNM and FMINNM for
unconditional arithmetic.
The same rules apply to FMAX and FMIN, but we only generate those
via the ACLE.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/predicates.md (aarch64_sve_float_maxmin_immediate)
(aarch64_sve_float_maxmin_operand): New predicates.
* config/aarch64/constraints.md (vsB): New constraint.
(vsM): Fix typo.
* config/aarch64/iterators.md (sve_pred_fp_rhs2_operand): Use
aarch64_sve_float_maxmin_operand for UNSPEC_COND_FMAXNM and
UNSPEC_COND_FMINNM.
* config/aarch64/aarch64-sve.md (<maxmin_uns><SVE_F:mode>3):
Use aarch64_sve_float_maxmin_operand for operand 2.
(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Likewise.
Add alternatives for the constant forms.
gcc/testsuite/
* gcc.target/aarch64/sve/fmaxnm_1.c: New test.
* gcc.target/aarch64/sve/fminnm_1.c: Likewise.
rsandifo [Wed, 14 Aug 2019 09:10:05 +0000 (09:10 +0000)]
[AArch64] Add support for SVE [SU]{MAX,MIN} immediate
This patch adds support for the immediate forms of SVE SMAX, SMIN, UMAX
and UMIN. SMAX and SMIN take the same range as MUL, so the patch
basically just moves and generalises the existing MUL patterns.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/constraints.md (vsb): New constraint.
(vsm): Generalize description.
* config/aarch64/iterators.md (SVE_INT_BINARY_IMM): New code
iterator.
(sve_imm_con): Handle smax, smin, umax and umin.
(sve_imm_prefix): New code attribute.
* config/aarch64/predicates.md (aarch64_sve_vsb_immediate)
(aarch64_sve_vsb_operand): New predicates.
(aarch64_sve_mul_immediate): Rename to...
(aarch64_sve_vsm_immediate): ...this.
(aarch64_sve_mul_operand): Rename to...
(aarch64_sve_vsm_operand): ...this.
* config/aarch64/aarch64-sve.md (mul<mode>3): Generalize to...
(<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...this.
(*mul<mode>3, *post_ra_mul<mode>3): Generalize to...
(*<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3)
(*post_ra_<SVE_INT_BINARY_IMM:optab><SVE_I:mode>3): ...these and
add movprfx support for the immediate alternatives.
(<su><maxmin><mode>3, *<su><maxmin><mode>3): Delete in favor
of the above.
(*<SVE_INT_BINARY_SD:optab><SVE_SDI:mode>3): Fix incorrect predicate
for operand 3.
rsandifo [Wed, 14 Aug 2019 09:06:12 +0000 (09:06 +0000)]
[AArch64] Add support for SVE CNOT
This patch adds support for predicated and unpredicated CNOT
(logical NOT on integers). In RTL terms, this is a select between
1 and 0 in which the predicate is fed by a comparison with zero.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/predicates.md (aarch64_simd_imm_one): New predicate.
* config/aarch64/aarch64-sve.md (*cnot<mode>): New pattern.
(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.
rsandifo [Wed, 14 Aug 2019 08:54:33 +0000 (08:54 +0000)]
[AArch64] Handle more SVE predicate constants
This patch handles more predicate constants by using TRN1, TRN2
and EOR. For now, only one operation is allowed before we fall
back to loading from memory or doing an integer move and a compare.
The EOR support includes the important special case of an inverted
predicate.
The real motivating case for this is the ACLE svdupq function,
which allows a repeating 16-bit predicate to be built from
individual scalar booleans. It's not easy to test properly
before that support is merged.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor)
(aarch64_expand_sve_const_pred_trn): New functions.
(aarch64_expand_sve_const_pred_1): Add a recurse_p parameter and
use the above functions when the parameter is true.
(aarch64_expand_sve_const_pred): Update call accordingly.
* config/aarch64/aarch64-sve.md (*aarch64_sve_<perm_insn><mode>):
Rename to...
(@aarch64_sve_<perm_insn><mode>): ...this.
gcc/testsuite/
* gcc.target/aarch64/sve/peel_ind_1.c: Look for an inverted .B VL1.
* gcc.target/aarch64/sve/peel_ind_2.c: Likewise .S VL7.
paolo [Wed, 14 Aug 2019 08:54:16 +0000 (08:54 +0000)]
/cp
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (grokdeclarator): Check here for typedef a function
definition or a member function definition.
(start_function): Adjust.
(grokmethod): Likewise.
/testsuite
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
paolo [Wed, 14 Aug 2019 08:53:28 +0000 (08:53 +0000)]
/cp
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (grokdeclarator): Check here for typedef a function
definition or a member function definition.
(start_function): Adjust.
(grokmethod): Likewise.
/testsuite
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
paolo [Wed, 14 Aug 2019 08:50:55 +0000 (08:50 +0000)]
/cp
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (grokdeclarator): Check here for typedef a function
definition or a member function definition.
(start_function): Adjust.
(grokmethod): Likewise.
/testsuite
2019-08-14 Paolo Carlini <paolo.carlini@oracle.com>
rsandifo [Wed, 14 Aug 2019 08:50:10 +0000 (08:50 +0000)]
[AArch64] Rework SVE integer comparisons
The remaining uses of UNSPEC_MERGE_PTRUE were in integer comparison
patterns. These aren't actually merging operations but zeroing ones,
although there's no practical difference when the predicate is a PTRUE.
All comparisons produced by expand are predicated on a PTRUE,
although we try to pattern-match a compare-and-AND as a predicated
comparison during combine.
Like previous patches, this one rearranges things in a way that works
better with the ACLE, where the initial predicate might or might not
be a PTRUE. The new patterns use UNSPEC_PRED_Z to represent zeroing
predication, with a aarch64_sve_ptrue_flag to record whether the
predicate is all-true (as for UNSPEC_PTEST).
See the block comment in the patch for more details.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_sve_same_pred_for_ptest_p):
Declare.
* config/aarch64/aarch64.c (aarch64_sve_same_pred_for_ptest_p)
(aarch64_sve_emit_int_cmp): New functions.
(aarch64_convert_sve_data_to_pred): Use aarch64_sve_emit_int_cmp.
(aarch64_sve_cmp_operand_p, aarch64_emit_sve_ptrue_op_cc): Delete.
(aarch64_expand_sve_vec_cmp_int): Use aarch64_sve_emit_int_cmp.
* config/aarch64/aarch64.md (UNSPEC_MERGE_PTRUE): Delete.
(UNSPEC_PRED_Z): New unspec.
(set_clobber_cc_nzc): Delete.
* config/aarch64/aarch64-sve.md: Add a block comment about
UNSPEC_PRED_Z.
(*cmp<SVE_INT_CMP:cmp_op><mode>): Rename to...
(@aarch64_pred_cmp<SVE_INT_CMP:cmp_op><mode>): ...this, replacing
the old pattern with that name. Use UNSPEC_PRED_Z instead of
UNSPEC_MERGE_PTRUE.
(*cmp<SVE_INT_CMP:cmp_op><mode>_cc): Use UNSPEC_PRED_Z instead of
UNSPEC_MERGE_PTRUE. Use aarch64_sve_same_pred_for_ptest_p to
check for compatible predicates.
(*cmp<cmp_op><SVE_INT_CMP:mode>_ptest): Likewise.
(*cmp<cmp_op><mode>_and): Match a known-ptrue UNSPEC_PRED_Z instead
of UNSPEC_MERGE_PTRUE. Split into the new form of predicated
comparisons above.
rsandifo [Wed, 14 Aug 2019 08:45:49 +0000 (08:45 +0000)]
[AArch64] Use "x" predication for SVE integer arithmetic patterns
The SVE patterns used an UNSPEC_MERGE_PTRUE unspec to attach a predicate
to an otherwise unpredicated integer arithmetic operation. As its name
suggests, this was designed to be a wrapper used for merging instructions
in which the predicate is known to be a PTRUE.
This unspec dates from the very early days of the port and nothing has
ever taken advantage of the PTRUE guarantee for arithmetic (as opposed
to comparisons). This patch replaces it with the less stringent
guarantee that:
(a) the values of inactive lanes don't matter and
(b) it is valid to make extra lanes active if there's a specific benefit
Doing this makes the patterns suitable for the ACLE _x functions, which
have the above semantics.
See the block comment in the patch for more details.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
rsandifo [Wed, 14 Aug 2019 08:39:48 +0000 (08:39 +0000)]
[AArch64] Rearrange SVE conversion patterns
The SVE int<->float conversion patterns need to handle various
combinations of modes, making sure that the predicate mode is based
on the widest element size. We did this using separate patterns for
conversions involving:
- HF (converting to/from [HSD]I, predicated based on the int operand)
- SF (converting to/from [SD]I, predicated based on the int operand)
- DF (converting to/from [SD]I, predicated based on the float operand)
This worked, and meant that there were no redundant patterns. However,
the ACLE needs various new predicated patterns too, and having three
versions of each one seemed excessive.
This patch instead splits the patterns into two groups rather than three.
For conversions to integers:
- truncating (predicated based on the source type, DF->SI only)
- non-truncating (predicated based on the destination type)
For conversions from integers:
- extending (predicated based on the destination type, SI->DF only)
- non-extending (predicated based on the source type)
This means that we still don't create pattern names for the invalid
combinations DF<->HI and SF<->HI. The downside is that we need to
use C conditions to exclude the SI<->DF case from the non-truncating/
non-extending patterns. We therefore have two pattern names for SI<->DF,
but genconditions ensures that the invalid one always has the value
CODE_FOR_nothing.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (VNx4SI_ONLY, VNx2DF_ONLY): New mode
iterators.
(SVE_BHSI, SVE_SDI): Tweak comment.
(SVE_HSDI): Likewise. Fix definition.
(SVE_SDF): New mode iterator.
(elem_bits): New mode attribute.
(SVE_COND_FCVT): New int iterator.
* config/aarch64/aarch64-sve.md
(*<SVE_COND_ICVTF:optab>v16hsf<SVE_HSDI:mode>2)
(*<SVE_COND_ICVTF:optab>vnx4sf<SVE_SDI:mode>2)
(*<SVE_COND_ICVTF:optab>vnx2df<SVE_SDI:mode>2): Merge into...
(*aarch64_sve_<SVE_COND_ICVTF:optab>_nontrunc<SVE_F:mode><SVE_HSDI:mode>)
(*aarch64_sve_<SVE_COND_ICVTF:optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
...these new patterns.
(*<SVE_COND_FCVTI:optab><SVE_HSDI:mode>vnx8hf2)
(*<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx4sf2)
(aarch64_sve_<SVE_COND_FCVTI:optab><SVE_SDI:mode>vnx2df2):
Merge into...
(*aarch64_sve_<SVE_COND_FCVTI:optab>_nonextend<SVE_HSDI:mode><SVE_F:mode>)
(aarch64_sve_<SVE_COND_FCVTI:optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>):
...these new patterns.
(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Update accordingly.
(*trunc<Vwide><SVE_SDF:mode>2): Replace with...
(*aarch64_sve_<SVE_COND_FCVT:optab>_trunc<SVE_SDF:mode><SVE_HSF:mode>):
...this new pattern.
(aarch64_sve_extend<SVE_HSDF:mode><Vwide>2): Replace with...
(aarch64_sve_<SVE_COND_FCVT:optab>_nontrunc<SVE_HSF:mode><SVE_SDF:mode>):
...this new pattern.
(vec_unpacks_<perm_hilo>_<mode>): Update accordingly.
rsandifo [Wed, 14 Aug 2019 08:34:12 +0000 (08:34 +0000)]
[AArch64] Use unspecs for SVE conversions involving floats
This patch changes the SVE FP<->FP and FP<->INT patterns so that
they use unspecs rather than rtx codes, continuing the series
to make the patterns work with predicates that might not be all-true.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.md (UNSPEC_FLOAT_CONVERT): Delete.
* config/aarch64/iterators.md (UNSPEC_COND_FCVT, UNSPEC_COND_FCVTZS)
(UNSPEC_COND_FCVTZU, UNSPEC_COND_SCVTF, UNSPEC_COND_UCVTF): New
unspecs.
(optab, su): Handle them.
(SVE_COND_FCVTI, SVE_COND_ICVTF): New int iterators.
* config/aarch64/aarch64-sve.md
(<fix_trunc_optab><SVE_F:mode><v_int_equiv>2): Replace with...
(<SVE_COND_FCVTI:optab><SVE_F:mode><v_int_equiv>2): ...this.
(*<fix_trunc_optab>v16hsf<:SVE_HSDImode>2): Replace with...
(*<SVE_COND_FCVTI:optab>v16hsf<SVE_F:mode>2): ...this.
(*<fix_trunc_optab>vnx4sf<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx4sf<SVE_SDI:mode>2): ...this.
(*<fix_trunc_optab>vnx2df<SVE_SDI:mode>2): Replace with...
(*<SVE_COND_FCVTI:optab>vnx2df<SVE_SDI:mode>2): ...this.
(vec_pack_<su>fix_trunc_vnx2df): Use SVE_COND_FCVTI instead of
FIXUORS.
(<FLOATUORS:optab><v_int_equiv><SVE_F:mode>2): Replace with...
(<SVE_COND_ICVTF:optab><v_int_equiv><SVE_F:mode>2): ...this.
(*<FLOATUORS:optab><SVE_HSDI:mode>vnx8hf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_HSDI:mode>vnx8hf2): ...this.
(*<FLOATUORS:optab><SVE_SDI:mode>vnx4sf2): Replace with...
(*<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx4sf2): ...this.
(aarch64_sve_<FLOATUORS:optab><SVE_SDI:mode>vnx2df2): Replace with...
(aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2): ...this.
(vec_unpack<su_optab>_float_<perm_hilo>_vnx4si): Pass a GP strictness
operand to aarch64_sve_<SVE_COND_ICVTF:optab><SVE_SDI:mode>vnx2df2.
(vec_pack_trunc_<SVE_HSF:Vwide>, *trunc<Vwide><SVE_HSF:mode>2)
(aarch64_sve_extend<mode><Vwide>2): Use UNSPEC_COND_FCVT instead
of UNSPEC_FLOAT_CONVERT.
(vec_unpacks_<perm_hilo>_<mode>): Pass a GP strictness operand to
aarch64_sve_extend<mode><Vwide>2.
rsandifo [Wed, 14 Aug 2019 08:29:56 +0000 (08:29 +0000)]
[AArch64] Rework SVE FP comparisons
This patch rewrites the SVE FP comparisons so that they always use
unspecs and so that they have an additional operand to indicate
whether the predicate is known to be a PTRUE. It's part of a series
that rewrites the SVE FP patterns so that they can cope with non-PTRUE
predicates.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (UNSPEC_COND_FCMUO): New unspec.
(cmp_op): Handle it.
(SVE_COND_FP_CMP): Rename to...
(SVE_COND_FP_CMP_I0): ...this.
(SVE_FP_CMP): Remove.
* config/aarch64/aarch64-sve.md
(*fcm<SVE_FP_CMP:cmp_op><SVE_F:mode>): Replace with...
(*fcm<SVE_COND_FP_CMP_I0:cmp_op><SVE_F:mode>): ...this new pattern,
using unspecs to represent the comparison.
(*fcmuo<SVE_F:mode>): Use UNSPEC_COND_FCMUO.
(*fcm<cmp_op><mode>_and_combine, *fcmuo<mode>_and_combine): Update
accordingly.
* config/aarch64/aarch64.c (aarch64_emit_sve_ptrue_op): Delete.
(aarch64_unspec_cond_code): Move after integer code. Handle
UNORDERED.
(aarch64_emit_sve_predicated_cond): Replace with...
(aarch64_emit_sve_fp_cond): ...this new function.
(aarch64_emit_sve_or_conds): Replace with...
(aarch64_emit_sve_or_fp_conds): ...this new function.
(aarch64_emit_sve_inverted_cond): Replace with...
(aarch64_emit_sve_invert_fp_cond): ...this new function.
(aarch64_expand_sve_vec_cmp_float): Update accordingly.
rsandifo [Wed, 14 Aug 2019 08:21:01 +0000 (08:21 +0000)]
[AArch64] Commonise some SVE FP patterns
This patch uses a single expander for generic FP binary optabs
that map to predicated SVE instructions. This makes them consistent
with the associated conditional optabs, which already work this way.
The patch also generalises the division handling to be one example
of a register-only predicated FP operation. The ACLE patches will
add FMULX to the same category.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/iterators.md (SVE_COND_FP_BINARY_REG): New int
iterator.
(sve_pred_fp_rhs1_operand, sve_pred_fp_rhs1_operand): New int
attributes.
* config/aarch64/aarch64-sve.md (add<SVE_F:mode>3, sub<SVE_F:mode>3)
(mul<SVE_F:mode>3, div<SVE_F:mode>3)
(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3): Merge into...
(<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this new expander.
(*div<SVE_F:mode>3): Generalize to...
(*<SVE_COND_FP_BINARY:optab><SVE_F:mode>3): ...this.
rsandifo [Wed, 14 Aug 2019 08:16:04 +0000 (08:16 +0000)]
[AArch64] Add a "GP strictness" operand to SVE FP unspecs
This patch makes the SVE unary, binary and ternary FP unspecs
take a new "GP strictness" operand that indicates whether the
predicate has to be taken literally, or whether it is valid to
make extra lanes active (up to and including using a PTRUE).
This again is laying the groundwork for the ACLE patterns,
in which the value can depend on the FP command-line flags.
At the moment it's only needed for addition, subtraction and
multiplication, which have unpredicated forms that can only
be used when operating on all lanes is safe. But in future
it might be useful for optimising predicate usage.
The strict mode requires extra alternatives for addition,
subtraction and multiplication, but I've left those for the
main ACLE patch.
2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64.md (SVE_RELAXED_GP, SVE_STRICT_GP): New
constants.
* config/aarch64/predicates.md (aarch64_sve_gp_strictness): New
predicate.
* config/aarch64/aarch64-protos.h (aarch64_sve_pred_dominates_p):
Declare.
* config/aarch64/aarch64.c (aarch64_sve_pred_dominates_p): New
function.
* config/aarch64/aarch64-sve.md: Add a block comment about the
handling of predicated FP operations.
(<SVE_COND_FP_UNARY:optab><SVE_F:mode>2, add<SVE_F:mode>3)
(sub<SVE_F:mode>3, mul<SVE_F:mode>3, div<SVE_F:mode>3)
(<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
(<SVE_COND_FP_MAXMIN_PUBLIC:maxmin_uns><SVE_F:mode>3)
(<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4): Add an SVE_RELAXED_GP
operand.
(cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>)
(cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>): Add an SVE_STRICT_GP
operand.
(*<SVE_COND_FP_UNARY:optab><SVE_F:mode>2)
(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_2)
(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_3)
(*cond_<SVE_COND_FP_BINARY:optab><SVE_F:mode>_any)
(*fabd<SVE_F:mode>3, *div<SVE_F:mode>3)
(*<SVE_COND_FP_MAXMIN_PUBLIC:optab><SVE_F:mode>3)
(*<SVE_COND_FP_TERNARY:optab><SVE_F:mode>4)
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_2)
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_4)
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Match the
strictness operands. Use aarch64_sve_pred_dominates_p to check
whether the predicate on the conditional operation is suitable
for merging. Split patterns into the canonical equal-predicate form.
(*add<SVE_F:mode>3, *sub<SVE_F:mode>3, *mul<SVE_F:mode>3): Likewise.
Restrict the unpredicated alternatives to SVE_RELAXED_GP.
projects / thirdparty / gcc.git / log
